first week of revision
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# [Bachelor in embedded system](/bachelor/)
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<header>
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<h1>Yggdrasil</h1>
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</header>
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Yggdrasil is a collections of notes around IT, OT and other geeks stuff
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<br>
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<br>
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<br>
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## [PTR](/bachelor/PTR/)
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## [SDi](/bachelor/SDi/)
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- [transmission_process.md](/bachelor/SDi/transmission_process.md)
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## [Eln](/bachelor/Eln/)
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- [AD/DA](/bachelor/Eln/ADDA.md)
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## [SEm](/bachelor/SEm/)
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- [PLA - Programmation en langage assembleur](/bachelor/SEm/PLA.md)
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- [ASM - Assembleur ARM](/bachelor/SEm/ASM.md)
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# [Bachelor in embedded system](/infotro/)
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Here notes I take during my bachelor in embedded systems
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Mainly some topics:
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- [PTR - Programmation Temps Réel](/infotro/PTR/)
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- [SDi - Système Distribué](/infotro/SDi/)
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- [Eln - Électronique](/infotro/Eln/)
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- [SEm - Systèmes Embarqué](/infotro/SEm/)
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# [STM32](/STM32/)
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Here some note specific about STM32
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@@ -1,9 +1,6 @@
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* [PTR](/bachelor/PTR)
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* [SDi](/bachelor/SDi)
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* [Transmission Process](/bachelor/SDi/transmission_process.md)
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* [Eln](/bachelor/Eln/)
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* [AD/DA](/bachelor/Eln/ADDA.md)
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* [SEm](/bachelor/SEm/)
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* [PLA - Programmation en langage assembleur](/bachelor/SEm/PLA.md)
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* [ASM - Assembleur ARM](/bachelor/SEm/ASM.md)
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* [Bachelor Infotro](/infotro/)
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* [PTR - Programmation Temps Réel](/infotro/PTR/)
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* [SDi - Systèmes Distribués](/infotro/SDi)
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* [Eln - Électronique](/infotro/Eln/)
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* [SEm - Systèmes Embarqués](/infotro/SEm/)
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* [STM32](/STM32/)
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@@ -1,3 +0,0 @@
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# Interfaces et convertisseur
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- [AD/DA](/bachelor/Eln/ADDA.md)
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@@ -1,18 +0,0 @@
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# Bachelor in embedded system
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## [PTR](/bachelor/PTR/)
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## [SDi](/bachelor/SDi/)
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- [transmission_process.md](/bachelor/SDi/transmission_process.md)
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## [Eln](/bachelor/Eln/)
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- [Interfaces et convertisseurs](/bachelor/Eln/README.md#Interfaces-et-convertisseur)
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- [AD/DA](/bachelor/Eln/ADDA.md)
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## [SEm](/bachelor/SEm/)
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- [PLA - Programmation en langage assembleur](/bachelor/SEm/PLA.md)
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- [ASM - Assembleur ARM](/bachelor/SEm/ASM.md)
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@@ -1,4 +0,0 @@
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# Taille des paquets de bits
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[PLA](/bachelor/arm/PLA.md)
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[ASM(/bachelor/arm/ASM.md)
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@@ -3,7 +3,7 @@ $$
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E=mc^2
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$$
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[transmission_process.md](../bachelor/SDi/transmission_process.md)
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[transmission_process.md](../infotro/SDi/transmission_process.md)
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## embedding it directly
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```mermaid
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@@ -26,7 +26,7 @@ Alice <-- Bob: another authentication Response
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## load from external files
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## Wavedrom
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```wavedrom
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File renamed without changes.
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@@ -22,23 +22,11 @@
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repo: 'https://git.kb28.ch/Klagarge/Yggdrasil.git',
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maxLevel: 3,
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coverpage: false,
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autoHeader: true,
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loadNavbar: true,
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loadNavbar: true, // Nav bar on top - was true
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subMaxLevel: 3,
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auto2top: true,
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mergeNavbar: true,
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search: {
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maxAge: 86400000, // Expiration time, the default one day
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paths: [
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'/',
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'/bachelor',
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'/STM32',
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],
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placeholder: 'Type to search',
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noData: 'No Results!',
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depth: 5,
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hideOtherSidebarContent: false, // whether or not to hide other sidebar content
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},
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auto2top: true, // was true
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mergeNavbar: true, // was true
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//search: 'auto',
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pagination: {
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previousText: {
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'/en/': 'PREV',
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@@ -79,6 +67,42 @@
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}
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}
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},
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darklightTheme: {
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defaultTheme : 'light',
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codeFontFamily : 'Roboto Mono, Monaco, courier, monospace',
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bodyFontSize : '17px',
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dark: {
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accent: '#42b983',
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toogleBackground : '#ffffff',
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textColor: '#b4b4b4',
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codeTextColor : '#ffffff',
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codeBackgroundColor : '#0e2233',
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sidebarSublink : '#b4b4b4',
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codeTypeColor : '#ffffff',
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coverBackground : 'linear-gradient(to left bottom, hsl(118, 100%, 85%) 0%,hsl(181, 100%, 85%) 100%)',
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toogleImage : 'url(https://cdn.jsdelivr.net/npm/docsify-darklight-theme@latest/icons/sun.svg)'
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},
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light: {
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accent: '#42b983',
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toogleBackground : '#091a28',
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background: '#ffffff',
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textColor: '#34495e',
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codeTextColor : '#525252',
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codeBackgroundColor : '#f8f8f8',
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borderColor : 'rgba(0, 0, 0, 0.07)',
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blockQuoteColor : '#858585',
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highlightColor : '#d22778',
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sidebarSublink : '#b4b4b4',
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codeTypeColor : '#091a28',
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coverBackground : 'linear-gradient(to left bottom, hsl(118, 100%, 85%) 0%,hsl(181, 100%, 85%) 100%)',
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toogleImage : 'url(https://cdn.jsdelivr.net/npm/docsify-darklight-theme@latest/icons/moon.svg)'
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}
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},
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};
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</script>
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<!-- Docsify v4 -->
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@@ -1,13 +1,14 @@
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# AD/DA
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<header>
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<h1>AD/DA</h1>
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</header>
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## AD
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# AD
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Il existe 4 méthodes principales pour une conversion Analogique vers Digital:
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- Parallèle
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- Par pesée
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- Par comptage
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- Sigma-delta
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# Conversion D/A
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| | + (Avantage) | - (Inconvénient) |
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|-------------------------|------------------------|-----------------------------|
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| **Parallèle<br>Unaire** | Simplicité<br>Monotone | Taille du circuit ~$2^{n}$ |
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@@ -16,11 +17,11 @@ Il existe 4 méthodes principales pour une conversion Analogique vers Digital:
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### Parallèle
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## Parallèle
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### Par comptage
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## Par comptage
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Un seul switch mais avec une fréquence de commutation très rapide
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$$
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V_{a} = \frac{t_{on}}{T}\cdot V_{ref}
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@@ -28,7 +29,7 @@ $$
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### Par pesée
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## Par pesée
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Un switch par bit.
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@@ -46,3 +47,15 @@ Pour un $V_{red} = 1[V]$ on a:
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| 1 | 1 | 0 | 0,750 |
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| 1 | 1 | 1 | 0,875 |
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# DA
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## Échantillonneur avec maintien
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# Caractéristique de convertisseurs
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## Digits et affichage
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$$
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nBits = Ceiling\left[log_2\cdot \frac{plage}{pas}\right]
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$$
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<header>
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<h1>Électronique</h1>
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</header>
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# Convertisseurs
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- [AD/DA](/infotro/Eln/ADDA)
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- [Sigma / Delta](/infotro/Eln/Sigma-Delta)
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@@ -0,0 +1,234 @@
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<header>
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<h1>Sigma / Delta</h1>
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</header>
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```drawio
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```
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|
||||
# Principe
|
||||
Un convertisseur analogique-numérique (AD) ou numérique-analogique (DA) delta-sigma se compose toujours d'un modulateur
|
||||
delta-sigma produisant un "flux binaire" ou "signal binaire séquentiel" et d'un filtre passe-bas.
|
||||
|
||||
Le modulateur peut être mis en œuvre comme un circuit numérique pour un signal numérique ou comme un circuit analogique
|
||||
pour un signal analogique. De même, le filtre passe-bas peut être analogique pour générer un signal de sortie
|
||||
analogique ou numérique, réalisé soit par un circuit numérique soit par un algorithme dans un processeur de signal.
|
||||
Cette structure permet d'explorer le flux binaire et le filtre passe-bas avant d'approfondir l'étude du
|
||||
modulateur delta-sigma.
|
||||
|
||||
## Le flux binaire
|
||||
Le flux binaire peut être interprété comme un signal digital ou analogique.
|
||||
Il s'agit d'un signal séquentiel à un bit avec une fréquence d'horloge significativement plus élevée que le débit des
|
||||
données numériques de l'ADC ou du DAC. Sa caractéristique essentielle est que sa moyenne correspond à la moyenne du
|
||||
signal d'entrée. Un niveau logique "haut" représente la valeur maximale de sortie, tandis qu'un niveau logique "bas"
|
||||
représente la valeur minimale de sortie.
|
||||
|
||||
- **Sortie analogique:** Le flux binaire est converti par un DA à un bit en un signal analogique.
|
||||
Les valeurs d'entrée "bas" et "haut" se traduisent respectivement par deux tensions analogiques précises, par exemple,
|
||||
1V et +1V.
|
||||
|
||||
- **Sortie digitale:** Dans le cas d'une sortie digitale, un niveau "haut" (ou "bas") dans le flux binaire représente
|
||||
la valeur maximale (ou minimale) de la plage de valeurs digitales. Par exemple, dans un système à 8 bits, un niveau
|
||||
"haut" pourrait correspondre à FF en hexadécimal, tandis qu'un niveau "bas" pourrait correspondre à 00 en hexadécimal.
|
||||
|
||||
Un flux binaire similaire existe dans un signal modulé en largeur d‘impulsions (PWM), mais il présente quelques
|
||||
désavantages par rapport au flux binaire d'un convertisseur delta-sigma, également appelé signal modulé en rapport
|
||||
d’impulsions (PPM). La transmission en série d'une valeur numérique, telle que la sortie en série d'un ADC conventionnel
|
||||
par pesée, est quant à elle appelée modulation par codage d'impulsions (PCM).
|
||||
|
||||
#
|
||||
|
||||
Un convertisseur sigma-delta est un type de convertisseur
|
||||
analogique-numérique (CAN) qui utilise une boucle de contre-réaction pour
|
||||
échantillonner et quantifier un signal analogique en un signal numérique.
|
||||
Le principe de fonctionnement d'un convertisseur sigma-delta peut être
|
||||
expliqué en plusieurs étapes :
|
||||
|
||||
1. Échantillonnage : Tout d'abord, le signal analogique est échantillonné
|
||||
à une fréquence d'échantillonnage beaucoup plus élevée que la bande
|
||||
passante du signal. Cette haute fréquence d'échantillonnage permet de
|
||||
réduire considérablement les effets des distorsions et du bruit dans le
|
||||
domaine fréquentiel.
|
||||
2. Quantification : Le signal échantillonné est ensuite quantifié en un
|
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signal numérique à l'aide d'un comparateur qui compare le signal avec une
|
||||
référence de tension fixe. La sortie du comparateur est une suite de bits
|
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représentant la valeur du signal analogique à chaque instant.
|
||||
3. Contre-réaction : Le signal quantifié est ensuite utilisé pour régler
|
||||
un oscillateur numérique qui produit un signal d'erreur. Ce signal
|
||||
d'erreur est ajouté au signal d'entrée dans la boucle de contre-réaction,
|
||||
ce qui permet de compenser les erreurs de quantification et de réduire le
|
||||
bruit dans le signal quantifié.
|
||||
4. Suréchantillonnage : Le signal numérique produit par le convertisseur
|
||||
sigma-delta est suréchantillonné à une fréquence beaucoup plus élevée que
|
||||
la fréquence d'échantillonnage initiale, ce qui permet de réduire encore
|
||||
davantage les effets du bruit dans le signal.
|
||||
5. Décimation : Enfin, le signal suréchantillonné est décimé à la
|
||||
fréquence d'échantillonnage désirée en utilisant un filtre passe-bas
|
||||
numérique qui élimine les composantes de hautes fréquences indésirables.
|
||||
|
||||
Le résultat final est un signal numérique représentant fidèlement le
|
||||
signal analogique d'origine, avec une faible distorsion et un faible
|
||||
bruit. La boucle de contre-réaction permet au convertisseur sigma-delta
|
||||
d'atteindre des performances supérieures à celles des autres types de
|
||||
convertisseurs analogique-numérique en termes de résolution et de
|
||||
précision.
|
||||
|
||||
$$
|
||||
SNR = 6,02n + 1,76[dB]
|
||||
$$
|
||||
|
||||

|
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File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
@@ -0,0 +1,151 @@
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<mxPoint x="710" y="320" as="targetPoint" />
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<Array as="points">
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</mxGraphModel>
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</mxfile>
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|
After Width: | Height: | Size: 11 KiB |
@@ -0,0 +1,73 @@
|
||||
<header>
|
||||
<h1>XF</h1>
|
||||
</header>
|
||||
|
||||
# Services
|
||||
|
||||
## Reactive
|
||||
|
||||
``` plantuml
|
||||
@startuml
|
||||
|
||||
participant MainLand as main
|
||||
participant Queue as queue
|
||||
participant Behavior as behavior
|
||||
participant XF as xf
|
||||
|
||||
main -> behavior: push(event)
|
||||
behavior -> queue: add(event)
|
||||
|
||||
xf -> xf: dispatchEvent()
|
||||
activate xf
|
||||
xf -> queue : getEvent()
|
||||
queue --> xf
|
||||
xf -> behavior: processEvent()
|
||||
deactivate xf
|
||||
|
||||
@enduml
|
||||
```
|
||||
|
||||
## Timeout
|
||||
``` plantuml
|
||||
@startuml
|
||||
|
||||
participant TimerQueue as tq #cyan
|
||||
participant Timeout as t #LawnGreen
|
||||
participant TimeoutManager as tm #cyan
|
||||
participant EventQueue as eq #cyan
|
||||
participant MainLand as main #cyan
|
||||
participant Reactive as r #yellow
|
||||
|
||||
r ->> tm: scheduleTimeout(tmid, evid, duration)
|
||||
activate r #magenta
|
||||
deactivate r
|
||||
|
||||
create t
|
||||
tm -->> t: <<create>>
|
||||
tm ->> tq: add(tm) <<synchronized>>
|
||||
tm ->> tq: tick()
|
||||
tq ->> t: decrement()
|
||||
tm ->> tq: tick()
|
||||
tq ->> t: decrement()
|
||||
|
||||
tm ->> eq: pushEvent(tm) <<synchronized>>
|
||||
tm ->> tq: remove(id) <<synchronized>>
|
||||
|
||||
main ->> eq: popEvent() <<synchronized>>
|
||||
activate main #yellow
|
||||
eq -->> main: ev
|
||||
main ->> t: getTarget()
|
||||
t -->> main: reactive
|
||||
main ->> r: processEvent(ev)
|
||||
activate r #magenta
|
||||
r -->> main
|
||||
deactivate r
|
||||
main -->> t !!: <<destroy>>
|
||||
|
||||
@enduml
|
||||
```
|
||||
|
||||
## Protection
|
||||
- Mutex, sémaphore
|
||||
- éviter les conflits mémoire
|
||||
|
||||
@@ -0,0 +1,19 @@
|
||||
# Bachelor in embedded system
|
||||
|
||||
## [PTR - Programmation Temps Réel](/infotro/PTR/)
|
||||
- [XF](/infotro/PTR/XF.md)
|
||||
|
||||
|
||||
## [SDi - Système Distribué](/infotro/SDi/)
|
||||
- [Transmission process](/infotro/SDi/transmission_process.md)
|
||||
|
||||
|
||||
## [Eln - Électronique](/infotro/Eln/)
|
||||
- [AD/DA](/infotro/Eln/ADDA)
|
||||
- [Sigma / Delta](/infotro/Eln/Sigma-Delta)
|
||||
|
||||
|
||||
## [SEm - Système Embarqué](/infotro/SEm/)
|
||||
- [PLA - Programmation en langage assembleur](/infotro/SEm/PLA.md)
|
||||
- [ASM - Assembleur ARM](/infotro/SEm/ASM.md)
|
||||
|
||||
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
@@ -0,0 +1,4 @@
|
||||
# Taille des paquets de bits
|
||||
|
||||
[PLA](/infotro/arm/PLA.md)
|
||||
[ASM](/infotro/arm/ASM.md)
|
||||
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
@@ -0,0 +1,10 @@
|
||||
* [PTR - Programmation Temps Réel](/infotro/PTR/)
|
||||
* [XF](/infotro/PTR/XF)
|
||||
* [SDi - Systèmes Distribués](/infotro/SDi)
|
||||
* [Transmission process](/infotro/SDi/transmission_process.md)
|
||||
* [Eln - Électronique](/infotro/Eln/)
|
||||
* [AD/DA](/infotro/Eln/ADDA)
|
||||
* [Sigma / Delta](/infotro/Eln/Sigma-Delta)
|
||||
* [SEm - Systèmes Embarqués](/infotro/SEm/)
|
||||
* [PLA - Programmation en langage assembleur](/infotro/SEm/PLA.md)
|
||||
* [ASM - Assembleur ARM](/infotro/SEm/ASM.md)
|
||||
Reference in new issue
Block a user