30 lines
1.8 KiB
Markdown
30 lines
1.8 KiB
Markdown
# NEORV32 Test Setup for the Digilent Arty A7-35 FPGA Board
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This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Digilent Arty A7-35 board.
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It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor
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top entity that provides a minimalistic interface (clock, reset, UART and 4 LEDs).
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* FPGA Board: :books: [Digilent Arty A7-35 FPGA Board](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual)
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* FPGA: Xilinx Artix-7 `XC7A35TICSG324-1L`
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* Toolchain: Xilinx Vivado (tested with Vivado 2019.2)
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## NEORV32 Configuration
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:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for
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configuration and entity details and [`arty_a7_35_test_setup.xdc`](https://github.com/stnolting/neorv32/blob/master/boards/arty-a7-35-test-setup/arty_a7_35_test_setup.xdc)
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for the according FPGA pin mapping.
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* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors)
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* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM
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* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT`
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* Tested with version [`1.5.3.3`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
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* Clock: 100MHz from on-board oscillator
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* Reset: Via dedicated on-board "RESET" button
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* GPIO output port `gpio_o`
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* bits 0..3 are connected to the green on-board LEDs (LD4 - LD7); LD4 is the bootloader status LED
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* bits 4..7 are (not actually used) connected to PMOD `JA` connector pins 1-4
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* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the on-board USB-UART chip
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