63 lines
4.3 KiB
Markdown
63 lines
4.3 KiB
Markdown
# NEORV32 Test Setup for the Terasic DE0-Nano FPGA Board
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This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Terasic DE0-Nano board.
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It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor
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top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs).
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* FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593)
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* FPGA: Intel Cyclone-IV `EP4CE22F17C6N`
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* Toolchain: Intel Quartus Prime (tested with Quartus Prime 20.1.0 - Lite Edition)
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### NEORV32 Configuration
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:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for
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configuration and entity details and `create_project.tcl` for the according FPGA pin mapping.
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* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors, 40-bit wide)
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* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM
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* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT`
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* Tested with version [`1.5.7.6`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
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* Clock: 50MHz from on-board oscillator
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* Reset: via on-board button "KEY0"
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* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0")
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* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the 40-pin **GPIO_0** header
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* `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4")
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* `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6")
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:warning: The default [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity
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is configured for a 100MHz input clock. Since the on-board oscillator of the DE0-nano board generates a 50MHz clock, the test setup has to be modified.
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This is automatically done by the `create_project.tcl` TCL script, which makes a local copy of the original test setup VHDL file
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(in *this* folder) and uses `sed` to configure the `CLOCK_FREQUENCY` generic (in the local copy) for 50MHz. The local copy is then used as actual
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top entity.
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### FPGA Utilization
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```
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Total logic elements 4,009 / 22,320 ( 18 % )
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Total registers 1860
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Total pins 12 / 154 ( 8 % )
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Total virtual pins 0
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Total memory bits 230,400 / 608,256 ( 38 % )
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Embedded Multiplier 9-bit elements 0 / 132 ( 0 % )
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Total PLLs 0 / 4 ( 0 % )
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```
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## How To Run
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The `create_project.tcl` TCL script in this directory can be used to create a complete Quartus project.
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If not already available, this script will create a `work` folder in this directory.
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1. start Quartus (in GUI mode)
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2. in the menu line click "View/Utility Windows/Tcl console" to open the Tcl console
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3. use the console to naviagte to **this** folder: `cd .../neorv32/boards/de0-nano-test-setup`
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4. execute `source create_project.tcl` - this will create and open the actual Quartus project in this folder
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5. if a "select family" prompt appears select the "Cyclone IV E" family and click OK
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6. double click on "Compile Design" in the "Tasks" window. This will synthesize, map and place & route your design and will also generate the actual FPGA bitstream
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7. when the process is done open the programmer (for example via "Tools/Programmer") and click "Start" in the programmer window to upload the bitstream to your FPGA
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8. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration:
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19200 Baud, 8 data bits, 1 stop bit, no parity bits, no transmission / flow control protocol (raw bytes only), newline on `\r\n` (carriage return & newline)
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9. now you can communicate with the bootloader console and upload a new program. Check out the [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example)
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and see section "Let's Get It Started" of the :page_facing_up: [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) for further resources.
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