60 lines
2.4 KiB
Markdown
60 lines
2.4 KiB
Markdown
# NEORV32 Test Setup using the NEORV32 with AvalonMM Master Interface wrapper
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This setup provides a very simple "demo setup" that uses the NEORV32 with a AvalonMM
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Interface wrapper. This makes if possible to connect you own modules using a simple
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version of the AvalonMM Master interface.
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Note that the AvalonMM Master is a very simple version providing only basic features:
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* Single read and write access
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* Flow control (variable wait-states)
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* 8/16/32 bit data access
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* Aligned and unaligned access supported
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The AvalonMM Master does **not** support:
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* Burst access
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* Pipeline transfer
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* Pending reads
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The design is based on the de0-nano-test-setup, but added a AvalonMM Master wrapper.
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The wrapper file can be found here [`AvalonMM wrapper`](../../../rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd).
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As a test an "external" DMEM is conneced to the NEORV32 over the AvalonMM Master Interface.
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It uses the simplified and simple example top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs).
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* FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593)
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* FPGA: Intel Cyclone-IV `EP4CE22F17C6N`
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* Toolchain: Intel Quartus Prime (tested with Quartus Prime 18.1.1 - Lite Edition)
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### NEORV32 Configuration
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For NEORV32 configuration the default values of the neorv32_top in version 1.6.0 are used
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with a few exceptions:
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* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (external DMEM), No bootloader
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* Tested with version [`1.6.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
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* Clock: 50MHz from on-board oscillator
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* Reset: via on-board button "KEY0"
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* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0")
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* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the 40-pin **GPIO_0** header
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* `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4")
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* `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6")
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### FPGA Utilization
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```
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Total logic elements 3,439 / 22,320 ( 15 % )
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Total registers 1674
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Total pins 12 / 154 ( 8 % )
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Total virtual pins 0
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Total memory bits 197,632 / 608,256 ( 32 % )
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Embedded Multiplier 9-bit elements 0 / 132 ( 0 % )
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Total PLLs 0 / 4 ( 0 % )
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```
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## How To Run
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Open the Quartus project file, compile and upload to FPGA. |