Initial commit

VHD/hdl/ex_24_1_2_studentVersion.vhd

@@ -0,0 +1,25 @@
+architecture studentVersion of ex_24_1_2 is
+
+  signal mySignal: std_ulogic;
+
+begin
+
+  process(motorOn, pwm) begin
+    if motorOn = '1' then
+      mySignal <= pwm;
+    else
+      mySignal <= '0';
+    end if;
+  end process;
+
+  process(mySignal, right_left) begin
+    if right_left = '1' then
+      side1 <= mySignal;
+      side2 <= '0';
+    else
+      side1 <= '0';
+      side2 <= mySignal;
+    end if;
+  end process;
+
+end studentVersion;