26 lines
437 B
VHDL
26 lines
437 B
VHDL
architecture studentVersion of ex_24_1_2 is
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signal mySignal: std_ulogic;
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begin
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process(motorOn, pwm) begin
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if motorOn = '1' then
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mySignal <= pwm;
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else
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mySignal <= '0';
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end if;
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end process;
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process(mySignal, right_left) begin
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if right_left = '1' then
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side1 <= mySignal;
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side2 <= '0';
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else
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side1 <= '0';
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side2 <= mySignal;
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end if;
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end process;
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end studentVersion;
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