Initial commit

Libs/Sequential/hdl/DFFE_pre_sim.vhd

@@ -0,0 +1,16 @@
+ARCHITECTURE sim OF DFFE_pre IS
+BEGIN
+
+  process(clk, pre)
+  begin
+    if pre = '1' then
+      q <= '1' after delay;
+    elsif rising_edge(clk) then
+      if e = '1' then
+        q <= d after delay;
+      end if;
+    end if;
+  end process;
+
+END ARCHITECTURE sim;
+

Libs/Sequential/hdl/DFFE_sim.vhd

@@ -0,0 +1,16 @@
+ARCHITECTURE sim OF DFFE IS
+BEGIN
+
+  process(clk, clr)
+  begin
+    if clr = '1' then
+      q <= '0' after delay;
+    elsif rising_edge(clk) then
+      if e = '1' then
+        q <= d after delay;
+      end if;
+    end if;
+  end process;
+
+END ARCHITECTURE sim;
+

Libs/Sequential/hdl/DFFE_sim1.vhd

@@ -0,0 +1,16 @@
+ARCHITECTURE sim OF DFFE_pre IS
+BEGIN
+
+  process(clk, pre)
+  begin
+    if pre = '1' then
+      q <= '1' after delay;
+    elsif rising_edge(clk) then
+      if e = '1' then
+        q <= d after delay;
+      end if;
+    end if;
+  end process;
+
+END ARCHITECTURE sim;
+

Libs/Sequential/hdl/DFF_pre_sim.vhd

@@ -0,0 +1,13 @@
+ARCHITECTURE sim OF DFF_pre IS
+BEGIN
+
+  process(clk, pre)
+  begin
+    if pre = '1' then
+      q <= '1' after delay;
+    elsif rising_edge(clk) then
+      q <= d after delay;
+    end if;
+  end process;
+
+END sim;

Libs/Sequential/hdl/DFF_sim.vhd

@@ -0,0 +1,13 @@
+ARCHITECTURE sim OF DFF IS
+BEGIN
+
+  process(clk, clr)
+  begin
+    if clr = '1' then
+      q <= '0' after delay;
+    elsif rising_edge(clk) then
+      q <= d after delay;
+    end if;
+  end process;
+
+END sim;

Libs/Sequential/hdl/DFF_sim1.vhd

@@ -0,0 +1,18 @@
+ARCHITECTURE sim OF TFF IS
+
+  signal q_int: std_ulogic;
+
+BEGIN
+
+  process(clk, clr)
+  begin
+    if clr = '1' then
+      q_int <= '0' after delay;
+    elsif rising_edge(clk) then
+      q_int <= t xor q_int after delay;
+    end if;
+  end process;
+
+  q <= q_int;
+
+END sim;

Libs/Sequential/hdl/DFF_sim11.vhd

@@ -0,0 +1,18 @@
+ARCHITECTURE sim OF TFF_pre IS
+
+  signal q_int: std_ulogic;
+
+BEGIN
+
+  process(clk, pre)
+  begin
+    if pre = '1' then
+      q_int <= '1' after delay;
+    elsif rising_edge(clk) then
+      q_int <= t xor q_int after delay;
+    end if;
+  end process;
+
+  q <= q_int;
+
+END sim;

Libs/Sequential/hdl/DFF_sim2.vhd

@@ -0,0 +1,13 @@
+ARCHITECTURE sim OF DFF_pre IS
+BEGIN
+
+  process(clk, pre)
+  begin
+    if pre = '1' then
+      q <= '1' after delay;
+    elsif rising_edge(clk) then
+      q <= d after delay;
+    end if;
+  end process;
+
+END sim;

Libs/Sequential/hdl/TFF_pre_sim.vhd

@@ -0,0 +1,18 @@
+ARCHITECTURE sim OF TFF_pre IS
+
+  signal q_int: std_ulogic;
+
+BEGIN
+
+  process(clk, pre)
+  begin
+    if pre = '1' then
+      q_int <= '1' after delay;
+    elsif rising_edge(clk) then
+      q_int <= t xor q_int after delay;
+    end if;
+  end process;
+
+  q <= q_int;
+
+END sim;

Libs/Sequential/hdl/TFF_sim.vhd

@@ -0,0 +1,18 @@
+ARCHITECTURE sim OF TFF IS
+
+  signal q_int: std_ulogic;
+
+BEGIN
+
+  process(clk, clr)
+  begin
+    if clr = '1' then
+      q_int <= '0' after delay;
+    elsif rising_edge(clk) then
+      q_int <= t xor q_int after delay;
+    end if;
+  end process;
+
+  q <= q_int;
+
+END sim;

Libs/Sequential/hdl/accumulator_RTL.vhd

@@ -0,0 +1,46 @@
+--------------------------------------------------------------------------------
+-- Copyright 2013 HES-SO Valais Wallis (www.hevs.ch)
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program IS distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License along with
+-- this program. If not, see <http://www.gnu.org/licenses/>
+--------------------------------------------------------------------------------
+-- Accumulator
+--   Accumulator with the step as signal and a synchronous clear signal.
+--
+--   Created on 2013-03-03
+--
+--   Version: 1.0
+--   Author: Oliver A. Gubler (oliver.gubler@hevs.ch)
+--------------------------------------------------------------------------------
+--
+ARCHITECTURE RTL OF accumulator IS
+  signal sum_s : unsigned(bitNb-1 downto 0);
+begin
+  
+  process (clock, reset)
+	begin
+	  if reset = '1' then
+	    sum_s <= (OTHERS => '0');
+    elsif rising_edge(clock)	then
+      if enable = '1' then
+    	   sum_s <= unsigned(step) + sum_s;
+      end if;
+      if clear = '1' then
+    	   sum_s <= (OTHERS => '0');
+  	   end if;
+  	 end if;
+	end process;
+
+  acc <= sum_s;
+
+END ARCHITECTURE RTL;
+

Libs/Sequential/hdl/counterEnableResetSync_rtl.vhd

@@ -0,0 +1,46 @@
+--------------------------------------------------------------------------------
+-- Copyright 2013 HES-SO Valais Wallis (www.hevs.ch)
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program IS distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License along with
+-- this program. If not, see <http://www.gnu.org/licenses/>
+--------------------------------------------------------------------------------
+-- Counter
+--   Simple counter with a generic width of nbBits.
+--
+--   Created on 2013-08-10
+--
+--   Version: 1.0
+--   Author: Oliver A. Gubler (oliver.gubler@hevs.ch)
+--------------------------------------------------------------------------------
+--
+ARCHITECTURE rtl OF counterEnableResetSync IS
+  
+  signal sCountOut: unsigned(countOut'range);
+
+BEGIN
+
+  countEndlessly: process(reset, clock)
+  begin
+    if reset = '1' then
+      sCountOut <= (others => '0');
+    elsif rising_edge(clock) then
+      if resetSync = '1' then
+        sCountOut <= (others => '0');
+      elsif enable = '1' then
+        sCountOut <= sCountOut + 1;
+      end if;
+    end if;
+  end process countEndlessly;
+
+  countOut <= sCountOut after delay;
+
+END ARCHITECTURE RTL;

Libs/Sequential/hdl/counterEnable_rtl.vhd

@@ -0,0 +1,44 @@
+--------------------------------------------------------------------------------
+-- Copyright 2013 HES-SO Valais Wallis (www.hevs.ch)
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program IS distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License along with
+-- this program. If not, see <http://www.gnu.org/licenses/>
+--------------------------------------------------------------------------------
+-- Counter
+--   Simple counter with a generic width of nbBits.
+--
+--   Created on 2013-08-10
+--
+--   Version: 1.0
+--   Author: Oliver A. Gubler (oliver.gubler@hevs.ch)
+--------------------------------------------------------------------------------
+--
+ARCHITECTURE rtl OF counterEnable IS
+  
+  signal sCountOut: unsigned(countOut'range);
+
+BEGIN
+
+  countEndlessly: process(reset, clock)
+  begin
+    if reset = '1' then
+      sCountOut <= (others => '0');
+    elsif rising_edge(clock) then
+      if enable = '1' then
+        sCountOut <= sCountOut + 1;
+      end if;
+    end if;
+  end process countEndlessly;
+  
+  countOut <= sCountOut after delay;
+
+END ARCHITECTURE RTL;

Libs/Sequential/hdl/counterRestart_RTL.vhd

@@ -0,0 +1,22 @@
+ARCHITECTURE RTL OF counterRestart IS
+
+  signal count: unsigned(countOut'range);
+
+BEGIN
+
+  countWithRestart: process(reset, clock)
+  begin
+    if reset = '1' then
+      count <= (others => '0');
+    elsif rising_edge(clock) then
+      if restart = '1' then
+        count <= (others => '0');
+      else
+        count <= count+1;
+      end if;
+    end if;
+  end process countWithRestart;
+
+  countOut <= count after delay;
+
+END ARCHITECTURE RTL;

Libs/Sequential/hdl/counterUpDownEnable_RTL.vhd

@@ -0,0 +1,24 @@
+ARCHITECTURE RTL OF counterUpDownEnable IS
+
+  signal sCountOut: unsigned(countOut'range);
+
+BEGIN
+
+  count: process(reset, clock)
+  begin
+    if reset = '1' then
+      sCountOut <= (others => '0');
+    elsif rising_edge(clock) then
+      if enable = '1' then
+        if up = '1' then
+          sCountOut <= sCountOut + 1;
+        elsif down = '1' then
+          sCountOut <= sCountOut - 1;
+        end if;
+      end if;
+    end if;
+  end process count;
+
+  countOut <= sCountOut after delay;
+
+END ARCHITECTURE RTL;

Libs/Sequential/hdl/counterUpDown_RTL.vhd

@@ -0,0 +1,22 @@
+ARCHITECTURE RTL OF counterUpDown IS
+
+  signal sCountOut: unsigned(countOut'range);
+
+BEGIN
+
+  count: process(reset, clock)
+  begin
+    if reset = '1' then
+      sCountOut <= (others => '0');
+    elsif rising_edge(clock) then
+      if up = '1' then
+        sCountOut <= sCountOut + 1;
+      elsif down = '1' then
+        sCountOut <= sCountOut - 1;
+      end if;
+    end if;
+  end process count;
+
+  countOut <= sCountOut after delay;
+
+END ARCHITECTURE RTL;

Libs/Sequential/hdl/counter_rtl.vhd

@@ -0,0 +1,18 @@
+ARCHITECTURE RTL OF counter IS
+
+  signal count: unsigned(countOut'range);
+
+BEGIN
+
+  countEndlessly: process(reset, clock)
+  begin
+    if reset = '1' then
+      count <= (others => '0');
+    elsif rising_edge(clock) then
+      count <= count+1;
+    end if;
+  end process countEndlessly;
+
+  countOut <= count after delay;
+
+END ARCHITECTURE RTL;

Libs/Sequential/hdl/edgeDetector_arch.vhd

@@ -0,0 +1,50 @@
+--------------------------------------------------------------------------------
+-- Copyright 2014 HES-SO Valais Wallis (www.hevs.ch)
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program IS distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License along with
+-- this program. If not, see <http://www.gnu.org/licenses/>
+--------------------------------------------------------------------------------
+-- EdgeDetector
+--   Detect rising and falling edges of a signal.
+--
+--   Created on 2014-04-02
+--
+--   Version: 1.0
+--   Author: Oliver A. Gubler (oliver.gubler@hevs.ch)
+--------------------------------------------------------------------------------
+ARCHITECTURE arch OF edgeDetector IS
+  
+  SIGNAL signal_s : std_ulogic;
+  SIGNAL rising_detected_s : std_ulogic;
+  SIGNAL falling_detected_s : std_ulogic;
+
+BEGIN
+
+  -- sync
+  reg : PROCESS (reset,clock)
+  BEGIN
+    IF reset = '1' THEN
+      signal_s <= '0';
+    ELSIF rising_edge(clock) THEN
+      signal_s <= input;  
+    END IF;    
+  END PROCESS reg ;
+  
+  -- edge detection
+  rising_detected_s <= input AND NOT signal_s; 
+  falling_detected_s <= NOT input AND signal_s;
+  
+  -- output
+  rising_detected <= rising_detected_s;
+  falling_detected <= falling_detected_s;
+  
+END ARCHITECTURE arch;

Libs/Sequential/hdl/freqDividerEnable_RTL.vhd

@@ -0,0 +1,28 @@
+LIBRARY Common;
+  USE Common.CommonLib.all;
+
+ARCHITECTURE RTL OF freqDividerEnable IS
+
+  signal count: unsigned(requiredBitNb(divideValue)-1 downto 0);
+
+BEGIN
+
+  countEndlessly: process(reset, clock)
+  begin
+    if reset = '1' then
+      count <= (others => '0');
+    elsif rising_edge(clock) then
+      if enIn = '1' then
+        if count = 0 then
+          count <= to_unsigned(divideValue-1, count'length);
+        else
+          count <= count-1 ;
+        end if;
+      end if;
+    end if;
+  end process countEndlessly;
+
+  enOut <= '1' after delay when count = 0
+    else '0' after delay;
+
+END ARCHITECTURE RTL;

Libs/Sequential/hdl/freqDivider_RTL.vhd

@@ -0,0 +1,26 @@
+LIBRARY Common;
+  USE Common.CommonLib.all;
+
+ARCHITECTURE RTL OF freqDivider IS
+
+  signal count: unsigned(requiredBitNb(divideValue)-1 downto 0);
+
+BEGIN
+
+  countEndlessly: process(reset, clock)
+  begin
+    if reset = '1' then
+      count <= (others => '0');
+    elsif rising_edge(clock) then
+      if count = 0 then
+        count <= to_unsigned(divideValue-1, count'length);
+      else
+        count <= count-1 ;
+      end if;
+    end if;
+  end process countEndlessly;
+
+  enable <= '1' after delay when count = 0
+    else '0' after delay;
+
+END ARCHITECTURE RTL;

Libs/Sequential/hdl/registerLogicVector_sim.vhd

@@ -0,0 +1,16 @@
+ARCHITECTURE sim OF registerLogicVector IS
+BEGIN
+
+  registerData: process(reset, clock)
+  begin
+    if reset = '1' then
+      dataOut <= (others => '0') after delay;
+    elsif rising_edge(clock) then
+      if enable = '1' then
+        dataOut <= dataIn after delay;
+      end if;
+    end if;
+  end process registerData;
+
+END ARCHITECTURE sim;
+

Libs/Sequential/hdl/registerSigned_sim.vhd

@@ -0,0 +1,16 @@
+ARCHITECTURE sim OF registerSigned IS
+BEGIN
+
+  registerData: process(reset, clock)
+  begin
+    if reset = '1' then
+      dataOut <= (others => '0') after delay;
+    elsif rising_edge(clock) then
+      if enable = '1' then
+        dataOut <= dataIn after delay;
+      end if;
+    end if;
+  end process registerData;
+
+END ARCHITECTURE sim;
+

Libs/Sequential/hdl/registerULogicVectorTo_RTL.vhd

@@ -0,0 +1,16 @@
+ARCHITECTURE sim OF registerULogicVectorTo IS
+BEGIN
+
+  registerData: process(reset, clock)
+  begin
+    if reset = '1' then
+      dataOut <= (others => '0') after delay;
+    elsif rising_edge(clock) then
+      if enable = '1' then
+        dataOut <= dataIn after delay;
+      end if;
+    end if;
+  end process registerData;
+
+END ARCHITECTURE sim;
+

Libs/Sequential/hdl/registerULogicVector_sim.vhd

@@ -0,0 +1,16 @@
+ARCHITECTURE sim OF registerULogicVector IS
+BEGIN
+
+  registerData: process(reset, clock)
+  begin
+    if reset = '1' then
+      dataOut <= (others => '0') after delay;
+    elsif rising_edge(clock) then
+      if enable = '1' then
+        dataOut <= dataIn after delay;
+      end if;
+    end if;
+  end process registerData;
+
+END ARCHITECTURE sim;
+

Libs/Sequential/hdl/registerULogicVector_sim1.vhd

@@ -0,0 +1,16 @@
+ARCHITECTURE sim OF registerLogicVector IS
+BEGIN
+
+  registerData: process(reset, clock)
+  begin
+    if reset = '1' then
+      dataOut <= (others => '0') after delay;
+    elsif rising_edge(clock) then
+      if enable = '1' then
+        dataOut <= dataIn after delay;
+      end if;
+    end if;
+  end process registerData;
+
+END ARCHITECTURE sim;
+

Libs/Sequential/hdl/registerUnsigned_sim.vhd

@@ -0,0 +1,16 @@
+ARCHITECTURE sim OF registerUnsigned IS
+BEGIN
+
+  registerData: process(reset, clock)
+  begin
+    if reset = '1' then
+      dataOut <= (others => '0') after delay;
+    elsif rising_edge(clock) then
+      if enable = '1' then
+        dataOut <= dataIn after delay;
+      end if;
+    end if;
+  end process registerData;
+
+END ARCHITECTURE sim;
+