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17 lines
339 B
VHDL
17 lines
339 B
VHDL
ARCHITECTURE sim OF registerSigned IS
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BEGIN
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registerData: process(reset, clock)
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begin
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if reset = '1' then
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dataOut <= (others => '0') after delay;
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elsif rising_edge(clock) then
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if enable = '1' then
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dataOut <= dataIn after delay;
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end if;
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end if;
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end process registerData;
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END ARCHITECTURE sim;
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