David Stadelmann 663614056e feat: Expose cardinal sub-anchors on pentagon-shaped ports
Wire up each port as a CeTZ group carrying, in addition to the
default attach anchor, four world-cardinal sub-anchors
`.east`, `.west`, `.north`, `.south` sitting on the pentagon's
bounding-box midpoints. This lets wires attach to any face of a
pentagon port instead of only the default outer/inner point:

  wire.wire("w", ("src", "blk-port-a.east"), ...)

Sub-anchor semantics are world-oriented (not rotated with the shape),
so the tip's cardinal name follows its actual world direction:

  - west  side, kind "in"  → tip = .east    (kind "out" → .west)
  - east  side, kind "in"  → tip = .west    (kind "out" → .east)
  - north side, kind "in"  → tip = .south   (kind "out" → .north)
  - south side, kind "in"  → tip = .north   (kind "out" → .south)

Bounding-box extents depend only on side orientation (horizontal for
east/west, vertical for north/south); `kind` mirrors the shape but
preserves the bbox, so cardinal names stay stable.

Non-pentagon ports degenerate all four sub-anchors to the default
attach point, so user code can address `.east`/`.west`/etc.
uniformly regardless of port shape. The bare port anchor name
(`<elmt-id>-port-<port-id>`) resolves to the same coordinate as
before via a custom "default" anchor, preserving backward
compatibility. Debug mode still marks only the default attach point.

Add `examples.port-shape-attach` demonstrating attaching wires to
the `.west`, `.east` and `.north` faces of a single pentagon port.
2026-09-14 18:22:31 +02:00
2024-05-16 21:34:50 +00:00
2026-07-28 14:45:49 +02:00
2026-07-04 01:35:35 +02:00

circuiteria

Circuiteria is a Typst package for drawing block circuit diagrams using the CeTZ package.

A platypus / Perry the Platypus meme made with colored rounded rectangles

Examples

Block diagram of a multi-cycle RISC-V FPGA processor
A bit of everything
Block diagram of a single-cycle RISC-V processor
Wires everywhere
Top-level block diagram of a single-cycle RISC-V processor Block diagram of a simple single-cycle RISC-V ALU
Groups Rotated

Note


These circuit layouts were copied from a digital design course given by prof. S. Zahno and recreated using this package

Click on the example image to jump to the code.

Usage

For more information, see the manual

To use this package, simply import circuiteria and call the circuit function:

#import "@preview/circuiteria:0.2.1"
#circuiteria.circuit({
  import circuiteria: *
  ...
})
V0.2.1
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