circuiteria

Add Verilog parsing and rendering support enhancement

#26

opened 2026-09-10 11:04:52 +00:00 by purpl3F0x

main

purpl3F0x:main

1

Release v0.2.1

#25

by HEL was merged 2026-07-03 23:37:38 +00:00

main

dev

Release v0.2.1

#24

by HEL was merged 2026-07-03 23:36:46 +00:00

dev

release/0.2.1

CeTZ, Tidy and Typst version updates

#23

opened 2026-07-01 09:16:42 +00:00 by dstadelm

main

dstadelm:version-update

1

fix: handle y port alignment with gates

#22

by HEL was merged 2026-06-30 19:08:48 +00:00

dev

fix/15-gate-y-port-alignment

Update manual and gallery documentation

#21

by HEL was merged 2026-06-30 17:18:26 +00:00

dev

feat/update-manual-and-gallery

Update CeTZ

#20

by HEL was merged 2026-06-30 16:54:30 +00:00

dev

feat/18-update-cetz

chore: expose package name

#19

by HEL was merged 2026-06-30 16:34:28 +00:00

dev

feat/17-expose-name

feature: added guided wire style enhancement

#14

by Shmerlard was merged 2025-08-24 11:01:02 +00:00

dev

Shmerlard:dev

1 approval

1

Add radius parameter to block enhancement

#12

by Shmerlard was merged 2025-08-17 12:36:04 +00:00

dev

Shmerlard:main

1 approval

6

feature: add IEC gates new component

#11

by bono was merged 2025-06-29 13:19:57 +00:00

dev

bono:add_iec_gates

1 approval

6

Update Electrical Components and Add Examples

#9

opened 2025-04-17 00:32:59 +00:00 by Mathemensch

main

Mathemensch:main

3

v0.2.0: Updates

#5

by HEL was merged 2025-03-01 21:28:24 +00:00

main

dev

updated compiler version + dependencies

#4

by HEL was merged 2025-03-01 21:17:27 +00:00

dev

feat/updates-1