Add Verilog parsing and rendering support #26

2026-09-10T11:04:52Z

purpl3F0x commented

2026-09-10 11:04:52 +00:00

First-time contributor

Hi, the above changes add some support for parsing a Verilog file and autogenerating a circuit module. The lib also supports bundling AXI buses and indicating active low resets.

Testing is limited, happy to make changes if needed.

Example

Hi, the above changes add some support for parsing a Verilog file and autogenerating a circuit module. The lib also supports bundling AXI buses and indicating active low resets. Testing is limited, happy to make changes if needed. Example <img width="353" alt="{8CE34B23-70F4-4DFD-9883-ABAB63814DEF}.png" src="attachments/23b8cbd9-9ef8-4a86-af11-3623cd547c2c">

{8CE34B23-70F4-4DFD-9883-ABAB63814DEF}.png

14 KiB

purpl3F0x added 1 commit 2026-09-10 11:18:26 +00:00

Add Verilog parsing and rendering support 0c1272e35e

- Introduced `verilog.typ` for parsing Verilog/SystemVerilog source code, supporting both ANSI and non-ANSI port styles.
- Implemented functions to analyze modules, infer AXI4, AXI4-Lite, and AXI4-Stream buses, as well as clock and reset signals.
- Added rendering capabilities for Verilog modules, allowing for visual representation of ports and buses.
- Created a new `gallery/verilog.typ` file to facilitate the drawing of Verilog blocks in diagrams.

Signed-off-by: Stavros Avramidis <stavros9899@gmail.com>

purpl3F0x force-pushed main from 55ea5cdef6 to 0c1272e35e

2026-09-10 11:18:26 +00:00

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HEL added the enhancement label 2026-09-14 05:13:14 +00:00

HEL commented

2026-09-15 10:30:34 +00:00

This looks great, thank you for your contribution !
I'm not very familiar with Verilog but I will try to review this soon

This looks great, thank you for your contribution ! I'm not very familiar with Verilog but I will try to review this soon

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Reference: HEL/circuiteria#26

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