forked from HEL/circuiteria
98 lines
1.5 KiB
Typst
98 lines
1.5 KiB
Typst
#import "@preview/cetz:0.3.2": draw
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#import "../src/lib.typ": circuit, element, util, wire
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#set page(width: auto, height: auto, margin: .5cm)
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#circuit({
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element.iec-gate-buf(
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x: 0,
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y: 0,
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w: 2,
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h: 2,
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id: "iec-buf",
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inputs: 1,
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)
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wire.stub("iec-buf-port-in0", "west")
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element.iec-gate-not(
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x: 3,
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y: 0,
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w: 2,
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h: 2,
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id: "iec-not",
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inputs: 1,
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)
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wire.stub("iec-not-port-in0", "west")
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element.iec-gate-and(
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id: "iec-and",
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x: 0,
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y: -3,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-and-port-in" + str(i), "west")
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}
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element.iec-gate-nand(
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id: "iec-nand",
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x: 3,
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y: -3,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-nand-port-in" + str(i), "west")
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}
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element.iec-gate-or(
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id: "iec-or",
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x: 0,
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y: -6,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-or-port-in" + str(i), "west")
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}
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element.iec-gate-nor(
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id: "iec-nor",
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x: 3,
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y: -6,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-nor-port-in" + str(i), "west")
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}
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element.iec-gate-xor(
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id: "iec-xor",
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x: 0,
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y: -9,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-xor-port-in" + str(i), "west")
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}
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element.iec-gate-xnor(
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id: "iec-nxor",
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x: 3,
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y: -9,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-nxor-port-in" + str(i), "west")
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}
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}) |