forked from HEL/circuiteria
added test5 in gallery
This commit is contained in:
BIN
gallery/test5.pdf
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BIN
gallery/test5.pdf
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Binary file not shown.
435
gallery/test5.typ
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435
gallery/test5.typ
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#import "@preview/cetz:0.2.2": draw
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#import "../src/lib.typ": *
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#set page(flipped: true, paper: "a3")
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#circuit({
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element.multiplexer(
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x: 0, y: 0, w: .5, h: 1.5, id: "PCMux",
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entries: 2,
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||||||
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fill: util.colors.blue,
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h-ratio: 80%
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)
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element.block(
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x: (rel: 2, to: "PCMux.east"),
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y: (from: "PCMux-port-out", to: "in"),
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w: 1, h: 1.5, id: "PCBuf",
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ports: (
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north: ((id: "clk", clock: true),),
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west: ((id: "in"),),
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east: ((id: "out"),)
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),
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fill: util.colors.green
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)
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element.block(
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x: (rel: 2, to: "PCBuf.east"),
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y: (from: "PCBuf-port-out", to: "A"),
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w: 3, h: 4, id: "IMem",
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ports: (
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|
west: (
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(id: "A", name: "A"),
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|
),
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|
east: (
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(id: "RD", name: "RD"),
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|
)
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|
),
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|
ports-margins: (
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|
west: (0%, 50%),
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|
east: (0%, 50%)
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|
),
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|
fill: util.colors.green,
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name: "Instruction\nMemory"
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|
)
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|
element.block(
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|
x: (rel: 3, to: "IMem.east"),
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y: (from: "IMem-port-RD", to: "A1"),
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|
w: 4.5, h: 4, id: "RegFile",
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|
ports: (
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|
north: (
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(id: "clk", clock: true, small: true),
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|
(id: "WE3", name: "WE3"),
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||||||
|
(id: "dummy1")
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|
),
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|
west: (
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|
(id: "dummy2"),
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|
(id: "A1", name: "A1"),
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|
(id: "dummy3"),
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|
(id: "A2", name: "A2"),
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|
(id: "A3", name: "A3"),
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|
(id: "dummy4"),
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|
(id: "WD3", name: "WD3"),
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|
),
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|
east: (
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|
(id: "RD1", name: "RD1"),
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||||||
|
(id: "RD2", name: "RD2"),
|
||||||
|
)
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|
),
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|
ports-margins: (
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|
north: (-20%, -20%),
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|
east: (0%, 10%)
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|
),
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|
fill: util.colors.green,
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|
name: "Register\nFile"
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|
)
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|
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element.alu(
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|
x: (rel: -.7, to: "IMem.center"),
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y: -7,
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w: 1.4, h: 2.8, id: "PCAdd",
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name: text("+", size: 1.5em),
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name-anchor: "name",
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fill: util.colors.pink
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|
)
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|
element.extender(
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|
x: (rel: 0, to: "RegFile.west"),
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y: (from: "PCAdd-port-out", to: "in"),
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|
w: 4, h: 1.5, id: "Ext",
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|
h-ratio: 50%,
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name: "Extend",
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name-anchor: "south",
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align-out: false,
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|
fill: util.colors.green
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|
)
|
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|
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|
element.multiplexer(
|
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|
x: (rel: 3, to: "RegFile.east"),
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|
y: (from: "RegFile-port-RD2", to: "in0"),
|
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|
w: .5, h: 1.5, id: "SrcBMux",
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|
fill: util.colors.blue,
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|
h-ratio: 80%
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|
)
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|
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|
element.alu(
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|
x: (rel: 2, to: "SrcBMux.east"),
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y: (from: "SrcBMux-port-out", to: "in2"),
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|
w: 1.4, h: 2.8, id: "ALU",
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name: rotate("ALU", -90deg),
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|
name-anchor: "name",
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|
fill: util.colors.pink
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|
)
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|
element.alu(
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|
x: (rel: 2, to: "SrcBMux.east"),
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|
y: (from: "Ext-port-out", to: "in2"),
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|
w: 1.4, h: 2.8, id: "JumpAdd",
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|
name: text("+", size: 1.5em),
|
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|
name-anchor: "name",
|
||||||
|
fill: util.colors.pink
|
||||||
|
)
|
||||||
|
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|
element.block(
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|
x: (rel: 4, to: "ALU.east"),
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y: (from: "ALU-port-out", to: "A"),
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|
w: 3, h: 4, id: "DMem",
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name: "Data\nMemory",
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ports: (
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|
north: (
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(id: "clk", clock: true, small: true),
|
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|
(id: "dummy1"),
|
||||||
|
(id: "WE", name: "WE")
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|
),
|
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|
west: (
|
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|
(id: "A", name: "A"),
|
||||||
|
(id: "WD", name: "WD")
|
||||||
|
),
|
||||||
|
east: (
|
||||||
|
(id: "RD", name: "RD"),
|
||||||
|
(id: "dummy2")
|
||||||
|
)
|
||||||
|
),
|
||||||
|
ports-margins: (
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|
north: (-10%, -10%),
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||||||
|
west: (-20%, -30%),
|
||||||
|
east: (-10%, -20%)
|
||||||
|
),
|
||||||
|
fill: util.colors.green
|
||||||
|
)
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|
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|
element.multiplexer(
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|
x: (rel: 3, to: "DMem.east"),
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y: (from: "DMem-port-RD", to: "in1"),
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w: .5, h: 1.5, id: "ResMux",
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entries: 2,
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||||||
|
fill: util.colors.blue,
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|
h-ratio: 80%
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|
)
|
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|
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element.block(
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x: (rel: 0, to: "RegFile.west"),
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y: 3.5, w: 2.5, h: 5, id: "Ctrl",
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|
name: "Control\nUnit",
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|
name-anchor: "north",
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|
ports: (
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west: (
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(id: "op", name: "op"),
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(id: "funct3", name: "funct3"),
|
||||||
|
(id: "funct7", name: [funct7#sub("[5]")]),
|
||||||
|
(id: "zero", name: "Zero"),
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||||||
|
),
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|
east: (
|
||||||
|
(id: "PCSrc"),
|
||||||
|
(id: "ResSrc"),
|
||||||
|
(id: "MemWrite"),
|
||||||
|
(id: "ALUCtrl"),
|
||||||
|
(id: "ALUSrc"),
|
||||||
|
(id: "ImmSrc"),
|
||||||
|
(id: "RegWrite"),
|
||||||
|
)
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||||||
|
),
|
||||||
|
ports-margins: (
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|
west: (40%, 0%)
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||||||
|
),
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||||||
|
fill: util.colors.orange
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|
)
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|
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|
// Wires
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wire.wire(
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"wPCNext", ("PCMux-port-out", "PCBuf-port-in"),
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name: "PCNext"
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|
)
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|
wire.stub("PCBuf-port-clk", "north", name: "clk", length: 0.25)
|
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|
wire.wire(
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||||||
|
"wPC1", ("PCBuf-port-out", "IMem-port-A"),
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name: "PC"
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|
)
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|
wire.wire(
|
||||||
|
"wPC2", ("PCBuf-port-out", "JumpAdd-port-in1"),
|
||||||
|
style: "zigzag",
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||||||
|
zigzag-ratio: 1
|
||||||
|
)
|
||||||
|
wire.wire(
|
||||||
|
"wPC3", ("PCBuf-port-out", "PCAdd-port-in1"),
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||||||
|
style: "zigzag",
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|
zigzag-ratio: 1
|
||||||
|
)
|
||||||
|
wire.intersection("wPC2.zig", radius: 2pt)
|
||||||
|
wire.intersection("wPC2.zag", radius: 2pt)
|
||||||
|
wire.stub("PCAdd-port-in2", "west", name: "4", length: 1.5)
|
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|
wire.wire(
|
||||||
|
"wPC+4", ("PCAdd-port-out", "PCMux-port-in0"),
|
||||||
|
style: "dodge",
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|
dodge-sides: ("east", "west"),
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||||||
|
dodge-y: -7.5,
|
||||||
|
dodge-margins: (1.2, .5),
|
||||||
|
name: "PC+4",
|
||||||
|
name-pos: "start"
|
||||||
|
)
|
||||||
|
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|
let mid = ("IMem-port-RD", 50%, "RegFile-port-A1")
|
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|
wire.wire(
|
||||||
|
"wInstr", ("IMem-port-RD", mid),
|
||||||
|
bus: true,
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||||||
|
name: "Instr",
|
||||||
|
name-pos: "start"
|
||||||
|
)
|
||||||
|
draw.hide({
|
||||||
|
draw.line(name: "bus-top",
|
||||||
|
mid,
|
||||||
|
(horizontal: (), vertical: "Ctrl-port-op")
|
||||||
|
)
|
||||||
|
draw.line(name: "bus-bot",
|
||||||
|
mid,
|
||||||
|
(horizontal: (), vertical: "Ext-port-in")
|
||||||
|
)
|
||||||
|
})
|
||||||
|
wire.wire(
|
||||||
|
"wInstrBus", ("bus-top.end", "bus-bot.end"),
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|
bus: true
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|
)
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|
wire.wire(
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||||||
|
"wOp", ("Ctrl-port-op", (horizontal: mid, vertical: ())),
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|
bus: true,
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|
reverse: true,
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||||||
|
slice: (6, 0)
|
||||||
|
)
|
||||||
|
wire.wire(
|
||||||
|
"wF3", ("Ctrl-port-funct3", (horizontal: mid, vertical: ())),
|
||||||
|
bus: true,
|
||||||
|
reverse: true,
|
||||||
|
slice: (14, 12)
|
||||||
|
)
|
||||||
|
wire.wire(
|
||||||
|
"wF7", ("Ctrl-port-funct7", (horizontal: mid, vertical: ())),
|
||||||
|
bus: true,
|
||||||
|
reverse: true,
|
||||||
|
slice: (30,)
|
||||||
|
)
|
||||||
|
wire.wire(
|
||||||
|
"wA1", ("RegFile-port-A1", (horizontal: mid, vertical: ())),
|
||||||
|
bus: true,
|
||||||
|
reverse: true,
|
||||||
|
slice: (19, 15)
|
||||||
|
)
|
||||||
|
wire.wire(
|
||||||
|
"wA2", ("RegFile-port-A2", (horizontal: mid, vertical: ())),
|
||||||
|
bus: true,
|
||||||
|
reverse: true,
|
||||||
|
slice: (24, 20)
|
||||||
|
)
|
||||||
|
wire.wire(
|
||||||
|
"wA3", ("RegFile-port-A3", (horizontal: mid, vertical: ())),
|
||||||
|
bus: true,
|
||||||
|
reverse: true,
|
||||||
|
slice: (11, 7)
|
||||||
|
)
|
||||||
|
wire.wire(
|
||||||
|
"wExt", ("Ext-port-in", (horizontal: mid, vertical: ())),
|
||||||
|
bus: true,
|
||||||
|
reverse: true,
|
||||||
|
slice: (31, 7)
|
||||||
|
)
|
||||||
|
wire.intersection("wF3.end", radius: 2pt)
|
||||||
|
wire.intersection("wF7.end", radius: 2pt)
|
||||||
|
wire.intersection("wA1.end", radius: 2pt)
|
||||||
|
wire.intersection("wA2.end", radius: 2pt)
|
||||||
|
wire.intersection("wA3.end", radius: 2pt)
|
||||||
|
|
||||||
|
wire.stub("RegFile-port-clk", "north", name: "clk", length: 0.25)
|
||||||
|
wire.wire("wRD2", ("RegFile-port-RD2", "SrcBMux-port-in0"))
|
||||||
|
wire.wire(
|
||||||
|
"wWD", ("RegFile-port-RD2", "DMem-port-WD"),
|
||||||
|
style: "zigzag",
|
||||||
|
zigzag-ratio: 1.5,
|
||||||
|
name: "WriteData",
|
||||||
|
name-pos: "end"
|
||||||
|
)
|
||||||
|
wire.intersection("wWD.zig", radius: 2pt)
|
||||||
|
|
||||||
|
wire.wire(
|
||||||
|
"wImmALU", ("Ext-port-out", "SrcBMux-port-in1"),
|
||||||
|
style: "zigzag",
|
||||||
|
zigzag-ratio: 2.5,
|
||||||
|
name: "ImmExt",
|
||||||
|
name-pos: "start"
|
||||||
|
)
|
||||||
|
wire.wire(
|
||||||
|
"wImmJump", ("Ext-port-out", "JumpAdd-port-in2")
|
||||||
|
)
|
||||||
|
wire.intersection("wImmALU.zig", radius: 2pt)
|
||||||
|
wire.wire(
|
||||||
|
"wJumpPC", ("JumpAdd-port-out", "PCMux-port-in1"),
|
||||||
|
style: "dodge",
|
||||||
|
dodge-sides: ("east", "west"),
|
||||||
|
dodge-y: -8,
|
||||||
|
dodge-margins: (1, 1),
|
||||||
|
name: "PCTarget",
|
||||||
|
name-pos: "start"
|
||||||
|
)
|
||||||
|
|
||||||
|
wire.wire(
|
||||||
|
"wSrcA", ("RegFile-port-RD1", "ALU-port-in1"),
|
||||||
|
name: "SrcA",
|
||||||
|
name-pos: "end"
|
||||||
|
)
|
||||||
|
wire.wire(
|
||||||
|
"wSrcB", ("SrcBMux-port-out", "ALU-port-in2"),
|
||||||
|
name: "SrcB",
|
||||||
|
name-pos: "end"
|
||||||
|
)
|
||||||
|
|
||||||
|
wire.wire(
|
||||||
|
"wZero", (
|
||||||
|
("ALU.north-east", 50%, "ALU-port-out"),
|
||||||
|
"Ctrl-port-zero"
|
||||||
|
),
|
||||||
|
style: "dodge",
|
||||||
|
dodge-sides: ("east", "west"),
|
||||||
|
dodge-y: 3,
|
||||||
|
dodge-margins: (1.5, 1),
|
||||||
|
name: "Zero",
|
||||||
|
name-pos: "start"
|
||||||
|
)
|
||||||
|
wire.wire(
|
||||||
|
"wALURes1", ("ALU-port-out", "DMem-port-A"),
|
||||||
|
name: "ALUResult",
|
||||||
|
name-pos: "start"
|
||||||
|
)
|
||||||
|
wire.wire(
|
||||||
|
"wALURes2", ("ALU-port-out", "ResMux-port-in0"),
|
||||||
|
style: "dodge",
|
||||||
|
dodge-sides: ("east", "west"),
|
||||||
|
dodge-y: 2,
|
||||||
|
dodge-margins: (3, 2)
|
||||||
|
)
|
||||||
|
wire.intersection("wALURes2.start2", radius: 2pt)
|
||||||
|
|
||||||
|
wire.stub("DMem-port-clk", "north", name: "clk", length: 0.25)
|
||||||
|
wire.wire(
|
||||||
|
"wRD", ("DMem-port-RD", "ResMux-port-in1"),
|
||||||
|
name: "ReadData",
|
||||||
|
name-pos: "start"
|
||||||
|
)
|
||||||
|
|
||||||
|
wire.wire(
|
||||||
|
"wRes", ("ResMux-port-out", "RegFile-port-WD3"),
|
||||||
|
style: "dodge",
|
||||||
|
dodge-sides: ("east", "west"),
|
||||||
|
dodge-y: -7.5,
|
||||||
|
dodge-margins: (1, 2)
|
||||||
|
)
|
||||||
|
draw.content(
|
||||||
|
"wRes.dodge-start",
|
||||||
|
"Result",
|
||||||
|
anchor: "south-east",
|
||||||
|
padding: 5pt
|
||||||
|
)
|
||||||
|
|
||||||
|
// Other wires
|
||||||
|
draw.group({
|
||||||
|
draw.stroke(util.colors.blue)
|
||||||
|
draw.line(name: "wPCSrc",
|
||||||
|
"Ctrl-port-PCSrc",
|
||||||
|
(horizontal: "RegFile.east", vertical: ()),
|
||||||
|
(horizontal: (), vertical: (rel: (0, 0.5), to: "Ctrl.north")),
|
||||||
|
(horizontal: "PCMux.north", vertical: ()),
|
||||||
|
"PCMux.north"
|
||||||
|
)
|
||||||
|
draw.line(name: "wResSrc",
|
||||||
|
"Ctrl-port-ResSrc",
|
||||||
|
(horizontal: "ResMux.north", vertical: ()),
|
||||||
|
"ResMux.north"
|
||||||
|
)
|
||||||
|
draw.line(name: "wMemWrite",
|
||||||
|
"Ctrl-port-MemWrite",
|
||||||
|
(horizontal: "DMem-port-WE", vertical: ()),
|
||||||
|
"DMem-port-WE"
|
||||||
|
)
|
||||||
|
draw.line(name: "wALUCtrl",
|
||||||
|
"Ctrl-port-ALUCtrl",
|
||||||
|
(horizontal: "ALU.north", vertical: ()),
|
||||||
|
"ALU.north"
|
||||||
|
)
|
||||||
|
draw.line(name: "wALUSrc",
|
||||||
|
"Ctrl-port-ALUSrc",
|
||||||
|
(horizontal: "SrcBMux.north", vertical: ()),
|
||||||
|
"SrcBMux.north"
|
||||||
|
)
|
||||||
|
draw.line(name: "wImmSrc",
|
||||||
|
"Ctrl-port-ImmSrc",
|
||||||
|
(rel: (1, 0), to: (horizontal: "RegFile.east", vertical: ())),
|
||||||
|
(horizontal: (), vertical: (rel: (0, -.5), to: "RegFile.south")),
|
||||||
|
(horizontal: "Ext.north", vertical: ()),
|
||||||
|
"Ext.north"
|
||||||
|
)
|
||||||
|
draw.line(name: "wRegWrite",
|
||||||
|
"Ctrl-port-RegWrite",
|
||||||
|
(rel: (.5, 0), to: (horizontal: "RegFile.east", vertical: ())),
|
||||||
|
(horizontal: (), vertical: ("Ctrl.south", 50%, "RegFile.north")),
|
||||||
|
(horizontal: "RegFile-port-WE3", vertical: ()),
|
||||||
|
"RegFile-port-WE3"
|
||||||
|
)
|
||||||
|
|
||||||
|
let names = (
|
||||||
|
"PCSrc": "PCSrc",
|
||||||
|
"ResSrc": "ResultSrc",
|
||||||
|
"MemWrite": "MemWrite",
|
||||||
|
"ALUCtrl": [ALUControl#sub("[2:0]")],
|
||||||
|
"ALUSrc": "ALUSrc",
|
||||||
|
"ImmSrc": [ImmSrc#sub("[1:0]")],
|
||||||
|
"RegWrite": "RegWrite"
|
||||||
|
)
|
||||||
|
for (port, name) in names {
|
||||||
|
draw.content("Ctrl-port-"+port, name, anchor: "south-west", padding: 3pt)
|
||||||
|
}
|
||||||
|
})
|
||||||
|
})
|
||||||
Reference in New Issue
Block a user