fixed minor issues + changed some default styles

gallery/test.typ

@@ -294,6 +294,6 @@
     bus: true
   )
 
-  wire.intersection("wResMP-RegFile.dodge-end")
+  wire.intersection("wResMP-RegFile.dodge-end", radius: .2)
-  wire.intersection("wResMP-AdrSrc.dodge-end")
+  wire.intersection("wResMP-AdrSrc.dodge-end", radius: .2)
 })

gallery/test2.typ

@@ -307,6 +307,6 @@
     bus: true
   )
   
-  wire.intersection("wResMP-RegFile.dodge-end")
+  wire.intersection("wResMP-RegFile.dodge-end", radius: .2)
-  wire.intersection("wResMP-AdrSrc.dodge-end")
+  wire.intersection("wResMP-AdrSrc.dodge-end", radius: .2)
 })

gallery/test5.typ

@@ -202,8 +202,8 @@
     style: "zigzag",
     zigzag-ratio: 1
   )
-  wire.intersection("wPC2.zig", radius: 2pt)
+  wire.intersection("wPC2.zig")
-  wire.intersection("wPC2.zag", radius: 2pt)
+  wire.intersection("wPC2.zag")
   wire.stub("PCAdd-port-in2", "west", name: "4", length: 1.5)
   wire.wire(
     "wPC+4", ("PCAdd-port-out", "PCMux-port-in0"),
@@ -278,11 +278,11 @@
     reverse: true,
     slice: (31, 7)
   )
-  wire.intersection("wF3.end", radius: 2pt)
+  wire.intersection("wF3.end")
-  wire.intersection("wF7.end", radius: 2pt)
+  wire.intersection("wF7.end")
-  wire.intersection("wA1.end", radius: 2pt)
+  wire.intersection("wA1.end")
-  wire.intersection("wA2.end", radius: 2pt)
+  wire.intersection("wA2.end")
-  wire.intersection("wA3.end", radius: 2pt)
+  wire.intersection("wA3.end")
 
   wire.stub("RegFile-port-clk", "north", name: "clk", length: 0.25)
   wire.wire("wRD2", ("RegFile-port-RD2", "SrcBMux-port-in0"))
@@ -293,7 +293,7 @@
     name: "WriteData",
     name-pos: "end"
   )
-  wire.intersection("wWD.zig", radius: 2pt)
+  wire.intersection("wWD.zig")
 
   wire.wire(
     "wImmALU", ("Ext-port-out", "SrcBMux-port-in1"),
@@ -305,7 +305,7 @@
   wire.wire(
     "wImmJump", ("Ext-port-out", "JumpAdd-port-in2")
   )
-  wire.intersection("wImmALU.zig", radius: 2pt)
+  wire.intersection("wImmALU.zig")
   wire.wire(
     "wJumpPC", ("JumpAdd-port-out", "PCMux-port-in1"),
     style: "dodge",
@@ -351,7 +351,7 @@
     dodge-y: 2,
     dodge-margins: (3, 2)
   )
-  wire.intersection("wALURes2.start2", radius: 2pt)
+  wire.intersection("wALURes2.start2")
 
   wire.stub("DMem-port-clk", "north", name: "clk", length: 0.25)
   wire.wire(

src/elements/alu.typ

@@ -86,6 +86,7 @@
     ports-y: (
       in1: (h) => {h * 0.225},
       in2: (h) => {h * 0.775},
+      out: (h) => {h * 0.5}
     ),
     debug: debug
   )

src/elements/extender.typ

@@ -71,7 +71,7 @@
   let out-pct = if align-out {h-ratio / 2} else {50%}
   let ports-y = (
     "in": (h) => {h - h * (h-ratio / 200%)},
-    "out": (h) => {h * (out-pct / 100%)}
+    "out": (h) => {h - h * (out-pct / 100%)}
   )
   
   element.elmt(

src/elements/logic/buf.typ

@@ -33,7 +33,7 @@
   y: none,
   w: none,
   h: none,
-  inputs: 2,
+  inputs: 1,
   fill: none,
   stroke: black + 1pt,
   id: "",
@@ -65,7 +65,7 @@
   y: none,
   w: none,
   h: none,
-  inputs: 2,
+  inputs: 1,
   fill: none,
   stroke: black + 1pt,
   id: "",

src/elements/logic/gate.typ

@@ -33,7 +33,7 @@
   stroke: black + 1pt,
   id: "",
   inverted: (),
-  inverted-radius: 0.2,
+  inverted-radius: 0.1,
   debug: (
     ports: false
   )

src/wire.typ

@@ -7,7 +7,7 @@
 #let signal-width = 1pt
 #let bus-width = 1.5pt
 
-#let intersection(pt, radius: .2, fill: black) = {
+#let intersection(pt, radius: .1, fill: black) = {
   draw.circle(pt, radius: radius, stroke: none, fill: fill)
 }