forked from HEL/circuiteria
137 lines
2.7 KiB
Typst
137 lines
2.7 KiB
Typst
#import "@preview/cetz:0.2.2": draw
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#import "../src/lib.typ": circuit, element, util, wire
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#set page(width: auto, height: auto, margin: .5cm)
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#circuit({
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element.block(
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x: 0, y: 0, w: 2, h: 3, id: "block",
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name: "Test",
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ports: (
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east: (
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(id: "out0"),
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(id: "out1"),
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(id: "out2"),
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)
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)
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)
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element.gate-and(
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x: 4, y: 0, w: 2, h: 2, id: "and1",
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inverted: ("in1")
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)
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element.gate-or(
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x: 7, y: 0, w: 2, h: 2, id: "or1",
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inverted: ("in0", "out")
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)
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wire.wire(
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"w1",
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("block-port-out0", "and1-port-in0"),
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style: "dodge",
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dodge-y: 3,
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dodge-margins: (20%, 20%)
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)
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wire.wire(
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"w2",
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("block-port-out1", "and1-port-in1"),
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style: "zigzag"
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)
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wire.wire(
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"w3",
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("and1-port-out", "or1-port-in0")
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)
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element.gate-and(
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x: 11, y: 0, w: 2, h: 2, id: "and2", inputs: 3,
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inverted: ("in0", "in2")
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)
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for i in range(3) {
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wire.stub("and2-port-in"+str(i), "west")
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}
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element.gate-xor(
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x: 14, y: 0, w: 2, h: 2, id: "xor",
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inverted: ("in1")
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)
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element.gate-buf(
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x: 0, y: -3, w: 2, h: 2, id: "buf"
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)
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element.gate-not(
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x: 0, y: -6, w: 2, h: 2, id: "not"
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)
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element.gate-and(
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x: 3, y: -3, w: 2, h: 2, id: "and"
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)
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element.gate-nand(
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x: 3, y: -6, w: 2, h: 2, id: "nand"
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)
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element.gate-or(
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x: 6, y: -3, w: 2, h: 2, id: "or"
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)
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element.gate-nor(
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x: 6, y: -6, w: 2, h: 2, id: "nor"
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)
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element.gate-xor(
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x: 9, y: -3, w: 2, h: 2, id: "xor"
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)
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element.gate-xnor(
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x: 9, y: -6, w: 2, h: 2, id: "xnor"
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)
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element.resistor(
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x: 0, y: -8, w: 2, h: 0.5, id: "res1"
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)
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element.capacitor(
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x: 3, y: (from: "res1-port-1", to: "0"),
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w: 2, h: 0.6,
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id: "cap1",
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scales: (100%, 80%),
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symbols: ([+], [-])
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)
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element.resistor(
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x: (rel: 1, to: "cap1-port-1"),
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y: (from: "cap1-port-1", to: "0"),
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w: 0.5, h: 2,
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id: "res2",
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vertical: true,
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zigzags: 8
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)
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element.capacitor(
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x: (rel: 1, to: "res2.east"),
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y: (from: "res2-port-1", to: "1"),
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w: 0.5, h: 2,
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id: "cap2",
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vertical: true,
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symbols: ([a], [b])
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)
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element.resistor(
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x: (rel: 1, to: "cap2-port-0"),
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y: (from: "cap2-port-0", to: "0"),
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w: 2, h: 0.5,
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id: "res3",
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zigzags: none
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)
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element.resistor(
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x: (rel: 1, to: "res3-port-1"),
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y: (from: "res3-port-1", to: "0"),
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w: 0.5, h: 2,
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id: "res4",
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zigzags: none,
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vertical: true
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)
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wire.wire("w4", ("res1-port-1", "cap1-port-0"))
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wire.wire("w5", ("cap1-port-1", "res2-port-0"))
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wire.wire("w6", ("res2-port-1", "cap2-port-1"))
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wire.wire("w7", ("cap2-port-0", "res3-port-0"))
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wire.wire("w8", ("res3-port-1", "res4-port-0"))
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}) |