1109 lines
33 KiB
C
1109 lines
33 KiB
C
/**
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******************************************************************************
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* @file stm32f7xx_hal_sram.c
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* @author MCD Application Team
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* @brief SRAM HAL module driver.
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* This file provides a generic firmware to drive SRAM memories
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* mounted as external device.
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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This driver is a generic layered driver which contains a set of APIs used to
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control SRAM memories. It uses the FMC layer functions to interface
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with SRAM devices.
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The following sequence should be followed to configure the FMC to interface
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with SRAM/PSRAM memories:
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(#) Declare a SRAM_HandleTypeDef handle structure, for example:
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SRAM_HandleTypeDef hsram; and:
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(++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
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values of the structure member.
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(++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
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base register instance for NOR or SRAM device
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(++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
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base register instance for NOR or SRAM extended mode
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(#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
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mode timings; for example:
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FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
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and fill its fields with the allowed values of the structure member.
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(#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
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performs the following sequence:
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(##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
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(##) Control register configuration using the FMC NORSRAM interface function
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FMC_NORSRAM_Init()
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(##) Timing register configuration using the FMC NORSRAM interface function
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FMC_NORSRAM_Timing_Init()
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(##) Extended mode Timing register configuration using the FMC NORSRAM interface function
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FMC_NORSRAM_Extended_Timing_Init()
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(##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
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(#) At this stage you can perform read/write accesses from/to the memory connected
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to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
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following APIs:
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(++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
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(++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
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(#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
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HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
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(#) You can continuously monitor the SRAM device HAL state by calling the function
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HAL_SRAM_GetState()
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*** Callback registration ***
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=============================================
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[..]
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The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
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allows the user to configure dynamically the driver callbacks.
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Use Functions HAL_SRAM_RegisterCallback() to register a user callback,
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it allows to register following callbacks:
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(+) MspInitCallback : SRAM MspInit.
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(+) MspDeInitCallback : SRAM MspDeInit.
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This function takes as parameters the HAL peripheral handle, the Callback ID
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and a pointer to the user callback function.
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Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
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weak (surcharged) function. It allows to reset following callbacks:
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(+) MspInitCallback : SRAM MspInit.
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(+) MspDeInitCallback : SRAM MspDeInit.
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This function) takes as parameters the HAL peripheral handle and the Callback ID.
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By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
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all callbacks are reset to the corresponding legacy weak (surcharged) functions.
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Exception done for MspInit and MspDeInit callbacks that are respectively
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reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init
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and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
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If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
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keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
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Callbacks can be registered/unregistered in READY state only.
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Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
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in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
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during the Init/DeInit.
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In that case first register the MspInit/MspDeInit user callbacks
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using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit
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or HAL_SRAM_Init function.
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When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
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not defined, the callback registering feature is not available
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and weak (surcharged) callbacks are used.
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@endverbatim
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f7xx_hal.h"
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/** @addtogroup STM32F7xx_HAL_Driver
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* @{
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*/
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#ifdef HAL_SRAM_MODULE_ENABLED
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/** @defgroup SRAM SRAM
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* @brief SRAM driver modules
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
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static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
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static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
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* @{
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*/
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/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and Configuration functions.
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*
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@verbatim
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==============================================================================
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##### SRAM Initialization and de_initialization functions #####
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==============================================================================
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[..] This section provides functions allowing to initialize/de-initialize
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the SRAM memory
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@endverbatim
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* @{
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*/
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/**
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* @brief Performs the SRAM device initialization sequence
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* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @param Timing Pointer to SRAM control timing structure
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* @param ExtTiming Pointer to SRAM extended mode timing structure
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
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FMC_NORSRAM_TimingTypeDef *ExtTiming)
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{
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/* Check the SRAM handle parameter */
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if (hsram == NULL)
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{
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return HAL_ERROR;
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}
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if (hsram->State == HAL_SRAM_STATE_RESET)
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{
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/* Allocate lock resource and initialize it */
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hsram->Lock = HAL_UNLOCKED;
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#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
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if (hsram->MspInitCallback == NULL)
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{
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hsram->MspInitCallback = HAL_SRAM_MspInit;
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}
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hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
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hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
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/* Init the low level hardware */
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hsram->MspInitCallback(hsram);
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#else
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/* Initialize the low level hardware (MSP) */
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HAL_SRAM_MspInit(hsram);
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#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
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}
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/* Initialize SRAM control Interface */
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(void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
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/* Initialize SRAM timing Interface */
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(void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
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/* Initialize SRAM extended mode timing Interface */
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(void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
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hsram->Init.ExtendedMode);
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/* Enable the NORSRAM device */
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__FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
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/* Initialize the SRAM controller state */
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hsram->State = HAL_SRAM_STATE_READY;
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return HAL_OK;
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}
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/**
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* @brief Performs the SRAM device De-initialization sequence.
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* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
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{
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#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
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if (hsram->MspDeInitCallback == NULL)
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{
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hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
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}
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/* DeInit the low level hardware */
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hsram->MspDeInitCallback(hsram);
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#else
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/* De-Initialize the low level hardware (MSP) */
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HAL_SRAM_MspDeInit(hsram);
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#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
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/* Configure the SRAM registers with their reset values */
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(void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
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/* Reset the SRAM controller state */
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hsram->State = HAL_SRAM_STATE_RESET;
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/* Release Lock */
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__HAL_UNLOCK(hsram);
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return HAL_OK;
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}
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/**
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* @brief SRAM MSP Init.
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* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @retval None
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*/
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__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
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{
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/* Prevent unused argument(s) compilation warning */
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UNUSED(hsram);
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_SRAM_MspInit could be implemented in the user file
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*/
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}
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/**
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* @brief SRAM MSP DeInit.
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* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @retval None
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*/
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__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
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{
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/* Prevent unused argument(s) compilation warning */
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UNUSED(hsram);
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_SRAM_MspDeInit could be implemented in the user file
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*/
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}
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/**
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* @brief DMA transfer complete callback.
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* @param hdma pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @retval None
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*/
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__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
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{
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/* Prevent unused argument(s) compilation warning */
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UNUSED(hdma);
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
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*/
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}
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/**
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* @brief DMA transfer complete error callback.
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* @param hdma pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @retval None
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*/
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__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
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{
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/* Prevent unused argument(s) compilation warning */
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UNUSED(hdma);
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
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*/
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}
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/**
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* @}
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*/
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/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
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* @brief Input Output and memory control functions
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*
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@verbatim
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==============================================================================
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##### SRAM Input and Output functions #####
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==============================================================================
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[..]
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This section provides functions allowing to use and control the SRAM memory
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@endverbatim
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* @{
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*/
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/**
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* @brief Reads 8-bit buffer from SRAM memory.
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* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @param pAddress Pointer to read start address
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* @param pDstBuffer Pointer to destination buffer
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* @param BufferSize Size of the buffer to read from memory
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
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uint32_t BufferSize)
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{
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uint32_t size;
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__IO uint8_t *psramaddress = (uint8_t *)pAddress;
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uint8_t *pdestbuff = pDstBuffer;
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HAL_SRAM_StateTypeDef state = hsram->State;
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/* Check the SRAM controller state */
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if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
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{
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/* Process Locked */
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__HAL_LOCK(hsram);
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/* Update the SRAM controller state */
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hsram->State = HAL_SRAM_STATE_BUSY;
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/* Read data from memory */
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for (size = BufferSize; size != 0U; size--)
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{
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*pdestbuff = *psramaddress;
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pdestbuff++;
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psramaddress++;
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}
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/* Update the SRAM controller state */
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hsram->State = state;
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/* Process unlocked */
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__HAL_UNLOCK(hsram);
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}
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else
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{
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return HAL_ERROR;
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}
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return HAL_OK;
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}
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/**
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* @brief Writes 8-bit buffer to SRAM memory.
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* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @param pAddress Pointer to write start address
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* @param pSrcBuffer Pointer to source buffer to write
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* @param BufferSize Size of the buffer to write to memory
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
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uint32_t BufferSize)
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{
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uint32_t size;
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__IO uint8_t *psramaddress = (uint8_t *)pAddress;
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uint8_t *psrcbuff = pSrcBuffer;
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/* Check the SRAM controller state */
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if (hsram->State == HAL_SRAM_STATE_READY)
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{
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/* Process Locked */
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__HAL_LOCK(hsram);
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/* Update the SRAM controller state */
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hsram->State = HAL_SRAM_STATE_BUSY;
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/* Write data to memory */
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for (size = BufferSize; size != 0U; size--)
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{
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*psramaddress = *psrcbuff;
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psrcbuff++;
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psramaddress++;
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}
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/* Update the SRAM controller state */
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hsram->State = HAL_SRAM_STATE_READY;
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/* Process unlocked */
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__HAL_UNLOCK(hsram);
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}
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else
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{
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return HAL_ERROR;
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}
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return HAL_OK;
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}
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/**
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* @brief Reads 16-bit buffer from SRAM memory.
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* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @param pAddress Pointer to read start address
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* @param pDstBuffer Pointer to destination buffer
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* @param BufferSize Size of the buffer to read from memory
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
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uint32_t BufferSize)
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{
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uint32_t size;
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__IO uint32_t *psramaddress = pAddress;
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uint16_t *pdestbuff = pDstBuffer;
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uint8_t limit;
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HAL_SRAM_StateTypeDef state = hsram->State;
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/* Check the SRAM controller state */
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if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
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{
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/* Process Locked */
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__HAL_LOCK(hsram);
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/* Update the SRAM controller state */
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hsram->State = HAL_SRAM_STATE_BUSY;
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/* Check if the size is a 32-bits multiple */
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limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
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/* Read data from memory */
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for (size = BufferSize; size != limit; size -= 2U)
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{
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*pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
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pdestbuff++;
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*pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
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pdestbuff++;
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psramaddress++;
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}
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/* Read last 16-bits if size is not 32-bits multiple */
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if (limit != 0U)
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{
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*pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
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}
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/* Update the SRAM controller state */
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hsram->State = state;
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/* Process unlocked */
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__HAL_UNLOCK(hsram);
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}
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else
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{
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return HAL_ERROR;
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}
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return HAL_OK;
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}
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/**
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* @brief Writes 16-bit buffer to SRAM memory.
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* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
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* the configuration information for SRAM module.
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* @param pAddress Pointer to write start address
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* @param pSrcBuffer Pointer to source buffer to write
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* @param BufferSize Size of the buffer to write to memory
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
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uint32_t BufferSize)
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{
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uint32_t size;
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__IO uint32_t *psramaddress = pAddress;
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uint16_t *psrcbuff = pSrcBuffer;
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uint8_t limit;
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/* Check the SRAM controller state */
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if (hsram->State == HAL_SRAM_STATE_READY)
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{
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/* Process Locked */
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__HAL_LOCK(hsram);
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/* Update the SRAM controller state */
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hsram->State = HAL_SRAM_STATE_BUSY;
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/* Check if the size is a 32-bits multiple */
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limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
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/* Write data to memory */
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for (size = BufferSize; size != limit; size -= 2U)
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{
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*psramaddress = (uint32_t)(*psrcbuff);
|
|
psrcbuff++;
|
|
*psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
|
|
psrcbuff++;
|
|
psramaddress++;
|
|
}
|
|
|
|
/* Write last 16-bits if size is not 32-bits multiple */
|
|
if (limit != 0U)
|
|
{
|
|
*psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
|
|
}
|
|
|
|
/* Update the SRAM controller state */
|
|
hsram->State = HAL_SRAM_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hsram);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Reads 32-bit buffer from SRAM memory.
|
|
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
|
|
* the configuration information for SRAM module.
|
|
* @param pAddress Pointer to read start address
|
|
* @param pDstBuffer Pointer to destination buffer
|
|
* @param BufferSize Size of the buffer to read from memory
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
|
|
uint32_t BufferSize)
|
|
{
|
|
uint32_t size;
|
|
__IO uint32_t *psramaddress = pAddress;
|
|
uint32_t *pdestbuff = pDstBuffer;
|
|
HAL_SRAM_StateTypeDef state = hsram->State;
|
|
|
|
/* Check the SRAM controller state */
|
|
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hsram);
|
|
|
|
/* Update the SRAM controller state */
|
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
|
|
|
/* Read data from memory */
|
|
for (size = BufferSize; size != 0U; size--)
|
|
{
|
|
*pdestbuff = *psramaddress;
|
|
pdestbuff++;
|
|
psramaddress++;
|
|
}
|
|
|
|
/* Update the SRAM controller state */
|
|
hsram->State = state;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hsram);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Writes 32-bit buffer to SRAM memory.
|
|
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
|
|
* the configuration information for SRAM module.
|
|
* @param pAddress Pointer to write start address
|
|
* @param pSrcBuffer Pointer to source buffer to write
|
|
* @param BufferSize Size of the buffer to write to memory
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
|
|
uint32_t BufferSize)
|
|
{
|
|
uint32_t size;
|
|
__IO uint32_t *psramaddress = pAddress;
|
|
uint32_t *psrcbuff = pSrcBuffer;
|
|
|
|
/* Check the SRAM controller state */
|
|
if (hsram->State == HAL_SRAM_STATE_READY)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hsram);
|
|
|
|
/* Update the SRAM controller state */
|
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
|
|
|
/* Write data to memory */
|
|
for (size = BufferSize; size != 0U; size--)
|
|
{
|
|
*psramaddress = *psrcbuff;
|
|
psrcbuff++;
|
|
psramaddress++;
|
|
}
|
|
|
|
/* Update the SRAM controller state */
|
|
hsram->State = HAL_SRAM_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hsram);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Reads a Words data from the SRAM memory using DMA transfer.
|
|
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
|
|
* the configuration information for SRAM module.
|
|
* @param pAddress Pointer to read start address
|
|
* @param pDstBuffer Pointer to destination buffer
|
|
* @param BufferSize Size of the buffer to read from memory
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
|
|
uint32_t BufferSize)
|
|
{
|
|
HAL_StatusTypeDef status;
|
|
HAL_SRAM_StateTypeDef state = hsram->State;
|
|
|
|
/* Check the SRAM controller state */
|
|
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hsram);
|
|
|
|
/* Update the SRAM controller state */
|
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
|
|
|
/* Configure DMA user callbacks */
|
|
if (state == HAL_SRAM_STATE_READY)
|
|
{
|
|
hsram->hdma->XferCpltCallback = SRAM_DMACplt;
|
|
}
|
|
else
|
|
{
|
|
hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
|
|
}
|
|
hsram->hdma->XferErrorCallback = SRAM_DMAError;
|
|
|
|
/* Enable the DMA Stream */
|
|
status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hsram);
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief Writes a Words data buffer to SRAM memory using DMA transfer.
|
|
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
|
|
* the configuration information for SRAM module.
|
|
* @param pAddress Pointer to write start address
|
|
* @param pSrcBuffer Pointer to source buffer to write
|
|
* @param BufferSize Size of the buffer to write to memory
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
|
|
uint32_t BufferSize)
|
|
{
|
|
HAL_StatusTypeDef status;
|
|
|
|
/* Check the SRAM controller state */
|
|
if (hsram->State == HAL_SRAM_STATE_READY)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hsram);
|
|
|
|
/* Update the SRAM controller state */
|
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
|
|
|
/* Configure DMA user callbacks */
|
|
hsram->hdma->XferCpltCallback = SRAM_DMACplt;
|
|
hsram->hdma->XferErrorCallback = SRAM_DMAError;
|
|
|
|
/* Enable the DMA Stream */
|
|
status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hsram);
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
|
/**
|
|
* @brief Register a User SRAM Callback
|
|
* To be used instead of the weak (surcharged) predefined callback
|
|
* @param hsram : SRAM handle
|
|
* @param CallbackId : ID of the callback to be registered
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
|
|
* @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
|
|
* @param pCallback : pointer to the Callback function
|
|
* @retval status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
|
|
pSRAM_CallbackTypeDef pCallback)
|
|
{
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
HAL_SRAM_StateTypeDef state;
|
|
|
|
if (pCallback == NULL)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hsram);
|
|
|
|
state = hsram->State;
|
|
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
|
|
{
|
|
switch (CallbackId)
|
|
{
|
|
case HAL_SRAM_MSP_INIT_CB_ID :
|
|
hsram->MspInitCallback = pCallback;
|
|
break;
|
|
case HAL_SRAM_MSP_DEINIT_CB_ID :
|
|
hsram->MspDeInitCallback = pCallback;
|
|
break;
|
|
default :
|
|
/* update return status */
|
|
status = HAL_ERROR;
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* update return status */
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hsram);
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief Unregister a User SRAM Callback
|
|
* SRAM Callback is redirected to the weak (surcharged) predefined callback
|
|
* @param hsram : SRAM handle
|
|
* @param CallbackId : ID of the callback to be unregistered
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
|
|
* @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
|
|
* @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
|
|
* @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
|
|
* @retval status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
|
|
{
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
HAL_SRAM_StateTypeDef state;
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hsram);
|
|
|
|
state = hsram->State;
|
|
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
|
|
{
|
|
switch (CallbackId)
|
|
{
|
|
case HAL_SRAM_MSP_INIT_CB_ID :
|
|
hsram->MspInitCallback = HAL_SRAM_MspInit;
|
|
break;
|
|
case HAL_SRAM_MSP_DEINIT_CB_ID :
|
|
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
|
|
break;
|
|
case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
|
|
hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
|
|
break;
|
|
case HAL_SRAM_DMA_XFER_ERR_CB_ID :
|
|
hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
|
|
break;
|
|
default :
|
|
/* update return status */
|
|
status = HAL_ERROR;
|
|
break;
|
|
}
|
|
}
|
|
else if (state == HAL_SRAM_STATE_RESET)
|
|
{
|
|
switch (CallbackId)
|
|
{
|
|
case HAL_SRAM_MSP_INIT_CB_ID :
|
|
hsram->MspInitCallback = HAL_SRAM_MspInit;
|
|
break;
|
|
case HAL_SRAM_MSP_DEINIT_CB_ID :
|
|
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
|
|
break;
|
|
default :
|
|
/* update return status */
|
|
status = HAL_ERROR;
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* update return status */
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hsram);
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief Register a User SRAM Callback for DMA transfers
|
|
* To be used instead of the weak (surcharged) predefined callback
|
|
* @param hsram : SRAM handle
|
|
* @param CallbackId : ID of the callback to be registered
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
|
|
* @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
|
|
* @param pCallback : pointer to the Callback function
|
|
* @retval status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
|
|
pSRAM_DmaCallbackTypeDef pCallback)
|
|
{
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
HAL_SRAM_StateTypeDef state;
|
|
|
|
if (pCallback == NULL)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hsram);
|
|
|
|
state = hsram->State;
|
|
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
|
|
{
|
|
switch (CallbackId)
|
|
{
|
|
case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
|
|
hsram->DmaXferCpltCallback = pCallback;
|
|
break;
|
|
case HAL_SRAM_DMA_XFER_ERR_CB_ID :
|
|
hsram->DmaXferErrorCallback = pCallback;
|
|
break;
|
|
default :
|
|
/* update return status */
|
|
status = HAL_ERROR;
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* update return status */
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hsram);
|
|
return status;
|
|
}
|
|
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup SRAM_Exported_Functions_Group3 Control functions
|
|
* @brief Control functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### SRAM Control functions #####
|
|
==============================================================================
|
|
[..]
|
|
This subsection provides a set of functions allowing to control dynamically
|
|
the SRAM interface.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enables dynamically SRAM write operation.
|
|
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
|
|
* the configuration information for SRAM module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
|
|
{
|
|
/* Check the SRAM controller state */
|
|
if (hsram->State == HAL_SRAM_STATE_PROTECTED)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hsram);
|
|
|
|
/* Update the SRAM controller state */
|
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
|
|
|
/* Enable write operation */
|
|
(void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
|
|
|
|
/* Update the SRAM controller state */
|
|
hsram->State = HAL_SRAM_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hsram);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Disables dynamically SRAM write operation.
|
|
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
|
|
* the configuration information for SRAM module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
|
|
{
|
|
/* Check the SRAM controller state */
|
|
if (hsram->State == HAL_SRAM_STATE_READY)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hsram);
|
|
|
|
/* Update the SRAM controller state */
|
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
|
|
|
/* Disable write operation */
|
|
(void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
|
|
|
|
/* Update the SRAM controller state */
|
|
hsram->State = HAL_SRAM_STATE_PROTECTED;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hsram);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
|
|
* @brief Peripheral State functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### SRAM State functions #####
|
|
==============================================================================
|
|
[..]
|
|
This subsection permits to get in run-time the status of the SRAM controller
|
|
and the data flow.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Returns the SRAM controller state
|
|
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
|
|
* the configuration information for SRAM module.
|
|
* @retval HAL state
|
|
*/
|
|
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
|
|
{
|
|
return hsram->State;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @brief DMA SRAM process complete callback.
|
|
* @param hdma : DMA handle
|
|
* @retval None
|
|
*/
|
|
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
|
|
|
|
/* Disable the DMA channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
|
|
/* Update the SRAM controller state */
|
|
hsram->State = HAL_SRAM_STATE_READY;
|
|
|
|
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
|
hsram->DmaXferCpltCallback(hdma);
|
|
#else
|
|
HAL_SRAM_DMA_XferCpltCallback(hdma);
|
|
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/**
|
|
* @brief DMA SRAM process complete callback.
|
|
* @param hdma : DMA handle
|
|
* @retval None
|
|
*/
|
|
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
|
|
|
|
/* Disable the DMA channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
|
|
/* Update the SRAM controller state */
|
|
hsram->State = HAL_SRAM_STATE_PROTECTED;
|
|
|
|
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
|
hsram->DmaXferCpltCallback(hdma);
|
|
#else
|
|
HAL_SRAM_DMA_XferCpltCallback(hdma);
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|
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
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|
}
|
|
|
|
/**
|
|
* @brief DMA SRAM error callback.
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|
* @param hdma : DMA handle
|
|
* @retval None
|
|
*/
|
|
static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
|
|
|
|
/* Disable the DMA channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
|
|
/* Update the SRAM controller state */
|
|
hsram->State = HAL_SRAM_STATE_ERROR;
|
|
|
|
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
|
|
hsram->DmaXferErrorCallback(hdma);
|
|
#else
|
|
HAL_SRAM_DMA_XferErrorCallback(hdma);
|
|
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* HAL_SRAM_MODULE_ENABLED */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|