1509 lines
45 KiB
C
1509 lines
45 KiB
C
/**
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******************************************************************************
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* @file stm32f7xx_hal_nor.c
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* @author MCD Application Team
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* @brief NOR HAL module driver.
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* This file provides a generic firmware to drive NOR memories mounted
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* as external device.
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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This driver is a generic layered driver which contains a set of APIs used to
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control NOR flash memories. It uses the FMC layer functions to interface
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with NOR devices. This driver is used as follows:
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(+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
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with control and timing parameters for both normal and extended mode.
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(+) Read NOR flash memory manufacturer code and device IDs using the function
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HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
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structure declared by the function caller.
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(+) Access NOR flash memory by read/write data unit operations using the functions
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HAL_NOR_Read(), HAL_NOR_Program().
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(+) Perform NOR flash erase block/chip operations using the functions
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HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
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(+) Read the NOR flash CFI (common flash interface) IDs using the function
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HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
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structure declared by the function caller.
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(+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
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HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
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(+) You can monitor the NOR device HAL state by calling the function
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HAL_NOR_GetState()
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[..]
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(@) This driver is a set of generic APIs which handle standard NOR flash operations.
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If a NOR flash device contains different operations and/or implementations,
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it should be implemented separately.
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*** NOR HAL driver macros list ***
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=============================================
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[..]
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Below the list of most used macros in NOR HAL driver.
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(+) NOR_WRITE : NOR memory write data to specified address
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*** Callback registration ***
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=============================================
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[..]
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The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
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allows the user to configure dynamically the driver callbacks.
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Use Functions HAL_NOR_RegisterCallback() to register a user callback,
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it allows to register following callbacks:
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(+) MspInitCallback : NOR MspInit.
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(+) MspDeInitCallback : NOR MspDeInit.
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This function takes as parameters the HAL peripheral handle, the Callback ID
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and a pointer to the user callback function.
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Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default
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weak (surcharged) function. It allows to reset following callbacks:
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(+) MspInitCallback : NOR MspInit.
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(+) MspDeInitCallback : NOR MspDeInit.
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This function) takes as parameters the HAL peripheral handle and the Callback ID.
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By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
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all callbacks are reset to the corresponding legacy weak (surcharged) functions.
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Exception done for MspInit and MspDeInit callbacks that are respectively
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reset to the legacy weak (surcharged) functions in the HAL_NOR_Init
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and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
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If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit
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keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
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Callbacks can be registered/unregistered in READY state only.
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Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
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in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
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during the Init/DeInit.
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In that case first register the MspInit/MspDeInit user callbacks
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using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit
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or HAL_NOR_Init function.
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When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
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not defined, the callback registering feature is not available
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and weak (surcharged) callbacks are used.
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@endverbatim
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f7xx_hal.h"
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/** @addtogroup STM32F7xx_HAL_Driver
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* @{
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*/
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#ifdef HAL_NOR_MODULE_ENABLED
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/** @defgroup NOR NOR
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* @brief NOR driver modules
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @defgroup NOR_Private_Defines NOR Private Defines
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* @{
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*/
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/* Constants to define address to set to write a command */
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#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
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#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
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#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
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#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
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#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
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#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
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#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
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/* Constants to define data to program a command */
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#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
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#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
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#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
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#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
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#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
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#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
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#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
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#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
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#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
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#define NOR_CMD_DATA_CFI (uint16_t)0x0098
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#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
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#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
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#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
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#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF
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#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040
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#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8
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#define NOR_CMD_CONFIRM (uint16_t)0x00D0
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#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020
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#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060
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#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070
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#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050
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/* Mask on NOR STATUS REGISTER */
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#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010
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#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
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#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
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#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080
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/* Address of the primary command set */
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#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013
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/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */
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#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */
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#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */
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#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */
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#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */
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#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */
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#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */
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#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */
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#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */
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#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */
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#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/** @defgroup NOR_Private_Variables NOR Private Variables
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* @{
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*/
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static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
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/**
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* @}
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*/
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/* Private functions ---------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup NOR_Exported_Functions NOR Exported Functions
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* @{
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*/
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/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and Configuration functions
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*
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@verbatim
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==============================================================================
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##### NOR Initialization and de_initialization functions #####
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==============================================================================
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[..]
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This section provides functions allowing to initialize/de-initialize
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the NOR memory
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@endverbatim
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* @{
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*/
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/**
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* @brief Perform the NOR memory Initialization sequence
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* @param hnor pointer to a NOR_HandleTypeDef structure that contains
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* the configuration information for NOR module.
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* @param Timing pointer to NOR control timing structure
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* @param ExtTiming pointer to NOR extended mode timing structure
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
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FMC_NORSRAM_TimingTypeDef *ExtTiming)
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{
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uint32_t deviceaddress;
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/* Check the NOR handle parameter */
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if (hnor == NULL)
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{
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return HAL_ERROR;
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}
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if (hnor->State == HAL_NOR_STATE_RESET)
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{
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/* Allocate lock resource and initialize it */
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hnor->Lock = HAL_UNLOCKED;
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#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
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if (hnor->MspInitCallback == NULL)
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{
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hnor->MspInitCallback = HAL_NOR_MspInit;
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}
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/* Init the low level hardware */
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hnor->MspInitCallback(hnor);
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#else
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/* Initialize the low level hardware (MSP) */
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HAL_NOR_MspInit(hnor);
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#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
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}
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/* Initialize NOR control Interface */
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(void)FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
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/* Initialize NOR timing Interface */
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(void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
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/* Initialize NOR extended mode timing Interface */
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(void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
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/* Enable the NORSRAM device */
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__FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
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/* Initialize NOR Memory Data Width*/
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if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
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{
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uwNORMemoryDataWidth = NOR_MEMORY_8B;
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}
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else
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{
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uwNORMemoryDataWidth = NOR_MEMORY_16B;
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}
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/* Initialize the NOR controller state */
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hnor->State = HAL_NOR_STATE_READY;
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/* Select the NOR device address */
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if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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{
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deviceaddress = NOR_MEMORY_ADRESS1;
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}
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else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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{
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deviceaddress = NOR_MEMORY_ADRESS2;
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}
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else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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{
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deviceaddress = NOR_MEMORY_ADRESS3;
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}
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else /* FMC_NORSRAM_BANK4 */
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{
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deviceaddress = NOR_MEMORY_ADRESS4;
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}
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/* Get the value of the command set */
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NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
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hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
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return HAL_NOR_ReturnToReadMode(hnor);
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}
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/**
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* @brief Perform NOR memory De-Initialization sequence
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* @param hnor pointer to a NOR_HandleTypeDef structure that contains
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* the configuration information for NOR module.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
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{
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#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
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if (hnor->MspDeInitCallback == NULL)
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{
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hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
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}
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/* DeInit the low level hardware */
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hnor->MspDeInitCallback(hnor);
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#else
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/* De-Initialize the low level hardware (MSP) */
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HAL_NOR_MspDeInit(hnor);
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#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
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/* Configure the NOR registers with their reset values */
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(void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
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/* Reset the NOR controller state */
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hnor->State = HAL_NOR_STATE_RESET;
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/* Release Lock */
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__HAL_UNLOCK(hnor);
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return HAL_OK;
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}
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/**
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* @brief NOR MSP Init
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* @param hnor pointer to a NOR_HandleTypeDef structure that contains
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* the configuration information for NOR module.
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* @retval None
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*/
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__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
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{
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/* Prevent unused argument(s) compilation warning */
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UNUSED(hnor);
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_NOR_MspInit could be implemented in the user file
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*/
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}
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/**
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* @brief NOR MSP DeInit
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* @param hnor pointer to a NOR_HandleTypeDef structure that contains
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* the configuration information for NOR module.
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* @retval None
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*/
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__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
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{
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/* Prevent unused argument(s) compilation warning */
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UNUSED(hnor);
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_NOR_MspDeInit could be implemented in the user file
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*/
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}
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/**
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* @brief NOR MSP Wait for Ready/Busy signal
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* @param hnor pointer to a NOR_HandleTypeDef structure that contains
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* the configuration information for NOR module.
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* @param Timeout Maximum timeout value
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* @retval None
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*/
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__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
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{
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/* Prevent unused argument(s) compilation warning */
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UNUSED(hnor);
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UNUSED(Timeout);
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_NOR_MspWait could be implemented in the user file
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*/
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}
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/**
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* @}
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*/
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/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
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* @brief Input Output and memory control functions
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*
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@verbatim
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==============================================================================
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##### NOR Input and Output functions #####
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==============================================================================
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[..]
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This section provides functions allowing to use and control the NOR memory
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@endverbatim
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* @{
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*/
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/**
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* @brief Read NOR flash IDs
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* @param hnor pointer to a NOR_HandleTypeDef structure that contains
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* the configuration information for NOR module.
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* @param pNOR_ID pointer to NOR ID structure
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
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{
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uint32_t deviceaddress;
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HAL_NOR_StateTypeDef state;
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HAL_StatusTypeDef status = HAL_OK;
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/* Check the NOR controller state */
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state = hnor->State;
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if (state == HAL_NOR_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
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{
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/* Process Locked */
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__HAL_LOCK(hnor);
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/* Update the NOR controller state */
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hnor->State = HAL_NOR_STATE_BUSY;
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/* Select the NOR device address */
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if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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{
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deviceaddress = NOR_MEMORY_ADRESS1;
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}
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else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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{
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deviceaddress = NOR_MEMORY_ADRESS2;
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}
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else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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{
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deviceaddress = NOR_MEMORY_ADRESS3;
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}
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else /* FMC_NORSRAM_BANK4 */
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{
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deviceaddress = NOR_MEMORY_ADRESS4;
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}
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/* Send read ID command */
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if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
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{
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NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
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NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
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NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
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}
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else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
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{
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NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT);
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}
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else
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{
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/* Primary command set not supported by the driver */
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status = HAL_ERROR;
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}
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if (status != HAL_ERROR)
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{
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/* Read the NOR IDs */
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pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
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pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
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DEVICE_CODE1_ADDR);
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pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
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DEVICE_CODE2_ADDR);
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pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
|
|
DEVICE_CODE3_ADDR);
|
|
}
|
|
|
|
/* Check the NOR controller state */
|
|
hnor->State = state;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the NOR memory to Read mode.
|
|
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
|
|
* the configuration information for NOR module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
|
|
{
|
|
uint32_t deviceaddress;
|
|
HAL_NOR_StateTypeDef state;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
|
/* Check the NOR controller state */
|
|
state = hnor->State;
|
|
if (state == HAL_NOR_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
|
/* Select the NOR device address */
|
|
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS1;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS2;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS3;
|
|
}
|
|
else /* FMC_NORSRAM_BANK4 */
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS4;
|
|
}
|
|
|
|
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
|
{
|
|
NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
|
|
}
|
|
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
|
|
{
|
|
NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
|
|
}
|
|
else
|
|
{
|
|
/* Primary command set not supported by the driver */
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
/* Check the NOR controller state */
|
|
hnor->State = state;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief Read data from NOR memory
|
|
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
|
|
* the configuration information for NOR module.
|
|
* @param pAddress pointer to Device address
|
|
* @param pData pointer to read data
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
|
|
{
|
|
uint32_t deviceaddress;
|
|
HAL_NOR_StateTypeDef state;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
|
/* Check the NOR controller state */
|
|
state = hnor->State;
|
|
if (state == HAL_NOR_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
|
/* Select the NOR device address */
|
|
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS1;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS2;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS3;
|
|
}
|
|
else /* FMC_NORSRAM_BANK4 */
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS4;
|
|
}
|
|
|
|
/* Send read data command */
|
|
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
|
{
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
|
|
}
|
|
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
|
|
{
|
|
NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY);
|
|
}
|
|
else
|
|
{
|
|
/* Primary command set not supported by the driver */
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
if (status != HAL_ERROR)
|
|
{
|
|
/* Read the data */
|
|
*pData = (uint16_t)(*(__IO uint32_t *)pAddress);
|
|
}
|
|
|
|
/* Check the NOR controller state */
|
|
hnor->State = state;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief Program data to NOR memory
|
|
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
|
|
* the configuration information for NOR module.
|
|
* @param pAddress Device address
|
|
* @param pData pointer to the data to write
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
|
|
{
|
|
uint32_t deviceaddress;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
|
/* Check the NOR controller state */
|
|
if (hnor->State == HAL_NOR_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if (hnor->State == HAL_NOR_STATE_READY)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
|
/* Select the NOR device address */
|
|
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS1;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS2;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS3;
|
|
}
|
|
else /* FMC_NORSRAM_BANK4 */
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS4;
|
|
}
|
|
|
|
/* Send program data command */
|
|
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
|
{
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
|
|
}
|
|
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
|
|
{
|
|
NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM);
|
|
}
|
|
else
|
|
{
|
|
/* Primary command set not supported by the driver */
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
if (status != HAL_ERROR)
|
|
{
|
|
/* Write the data */
|
|
NOR_WRITE(pAddress, *pData);
|
|
}
|
|
|
|
/* Check the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief Reads a half-word buffer from the NOR memory.
|
|
* @param hnor pointer to the NOR handle
|
|
* @param uwAddress NOR memory internal address to read from.
|
|
* @param pData pointer to the buffer that receives the data read from the
|
|
* NOR memory.
|
|
* @param uwBufferSize number of Half word to read.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
|
|
uint32_t uwBufferSize)
|
|
{
|
|
uint32_t deviceaddress;
|
|
uint32_t size = uwBufferSize;
|
|
uint32_t address = uwAddress;
|
|
uint16_t *data = pData;
|
|
HAL_NOR_StateTypeDef state;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
|
/* Check the NOR controller state */
|
|
state = hnor->State;
|
|
if (state == HAL_NOR_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
|
/* Select the NOR device address */
|
|
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS1;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS2;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS3;
|
|
}
|
|
else /* FMC_NORSRAM_BANK4 */
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS4;
|
|
}
|
|
|
|
/* Send read data command */
|
|
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
|
{
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
|
|
}
|
|
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
|
|
{
|
|
NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
|
|
}
|
|
else
|
|
{
|
|
/* Primary command set not supported by the driver */
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
if (status != HAL_ERROR)
|
|
{
|
|
/* Read buffer */
|
|
while (size > 0U)
|
|
{
|
|
*data = *(__IO uint16_t *)address;
|
|
data++;
|
|
address += 2U;
|
|
size--;
|
|
}
|
|
}
|
|
|
|
/* Check the NOR controller state */
|
|
hnor->State = state;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief Writes a half-word buffer to the NOR memory. This function must be used
|
|
only with S29GL128P NOR memory.
|
|
* @param hnor pointer to the NOR handle
|
|
* @param uwAddress NOR memory internal start write address
|
|
* @param pData pointer to source data buffer.
|
|
* @param uwBufferSize Size of the buffer to write
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
|
|
uint32_t uwBufferSize)
|
|
{
|
|
uint16_t *p_currentaddress;
|
|
const uint16_t *p_endaddress;
|
|
uint16_t *data = pData;
|
|
uint32_t deviceaddress;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
|
/* Check the NOR controller state */
|
|
if (hnor->State == HAL_NOR_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if (hnor->State == HAL_NOR_STATE_READY)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
|
/* Select the NOR device address */
|
|
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS1;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS2;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS3;
|
|
}
|
|
else /* FMC_NORSRAM_BANK4 */
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS4;
|
|
}
|
|
|
|
/* Initialize variables */
|
|
p_currentaddress = (uint16_t *)(deviceaddress + uwAddress);
|
|
p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U)));
|
|
|
|
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
|
{
|
|
/* Issue unlock command sequence */
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
|
|
|
/* Write Buffer Load Command */
|
|
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
|
|
NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
|
|
}
|
|
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
|
|
{
|
|
/* Write Buffer Load Command */
|
|
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM);
|
|
NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
|
|
}
|
|
else
|
|
{
|
|
/* Primary command set not supported by the driver */
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
if (status != HAL_ERROR)
|
|
{
|
|
/* Load Data into NOR Buffer */
|
|
while (p_currentaddress <= p_endaddress)
|
|
{
|
|
NOR_WRITE(p_currentaddress, *data);
|
|
|
|
data++;
|
|
p_currentaddress ++;
|
|
}
|
|
|
|
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
|
{
|
|
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
|
|
}
|
|
else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */
|
|
{
|
|
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM);
|
|
}
|
|
}
|
|
|
|
/* Check the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
/**
|
|
* @brief Erase the specified block of the NOR memory
|
|
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
|
|
* the configuration information for NOR module.
|
|
* @param BlockAddress Block to erase address
|
|
* @param Address Device address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
|
|
{
|
|
uint32_t deviceaddress;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
|
/* Check the NOR controller state */
|
|
if (hnor->State == HAL_NOR_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if (hnor->State == HAL_NOR_STATE_READY)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
|
/* Select the NOR device address */
|
|
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS1;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS2;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS3;
|
|
}
|
|
else /* FMC_NORSRAM_BANK4 */
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS4;
|
|
}
|
|
|
|
/* Send block erase command sequence */
|
|
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
|
{
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
|
|
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
|
|
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
|
|
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
|
|
NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
|
|
}
|
|
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
|
|
{
|
|
NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK);
|
|
NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
|
|
NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE);
|
|
NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
|
|
}
|
|
else
|
|
{
|
|
/* Primary command set not supported by the driver */
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
/* Check the NOR memory status and update the controller state */
|
|
hnor->State = HAL_NOR_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
/**
|
|
* @brief Erase the entire NOR chip.
|
|
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
|
|
* the configuration information for NOR module.
|
|
* @param Address Device address
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
|
|
{
|
|
uint32_t deviceaddress;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
UNUSED(Address);
|
|
|
|
/* Check the NOR controller state */
|
|
if (hnor->State == HAL_NOR_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if (hnor->State == HAL_NOR_STATE_READY)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
|
/* Select the NOR device address */
|
|
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS1;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS2;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS3;
|
|
}
|
|
else /* FMC_NORSRAM_BANK4 */
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS4;
|
|
}
|
|
|
|
/* Send NOR chip erase command sequence */
|
|
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
|
{
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
|
|
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
|
|
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
|
|
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
|
|
}
|
|
else
|
|
{
|
|
/* Primary command set not supported by the driver */
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
/* Check the NOR memory status and update the controller state */
|
|
hnor->State = HAL_NOR_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief Read NOR flash CFI IDs
|
|
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
|
|
* the configuration information for NOR module.
|
|
* @param pNOR_CFI pointer to NOR CFI IDs structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
|
|
{
|
|
uint32_t deviceaddress;
|
|
HAL_NOR_StateTypeDef state;
|
|
|
|
/* Check the NOR controller state */
|
|
state = hnor->State;
|
|
if (state == HAL_NOR_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
|
/* Select the NOR device address */
|
|
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS1;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS2;
|
|
}
|
|
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS3;
|
|
}
|
|
else /* FMC_NORSRAM_BANK4 */
|
|
{
|
|
deviceaddress = NOR_MEMORY_ADRESS4;
|
|
}
|
|
|
|
/* Send read CFI query command */
|
|
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
|
|
|
|
/* read the NOR CFI information */
|
|
pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
|
|
pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
|
|
pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
|
|
pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
|
|
|
|
/* Check the NOR controller state */
|
|
hnor->State = state;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
|
|
/**
|
|
* @brief Register a User NOR Callback
|
|
* To be used instead of the weak (surcharged) predefined callback
|
|
* @param hnor : NOR handle
|
|
* @param CallbackId : ID of the callback to be registered
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
|
|
* @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
|
|
* @param pCallback : pointer to the Callback function
|
|
* @retval status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
|
|
pNOR_CallbackTypeDef pCallback)
|
|
{
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
HAL_NOR_StateTypeDef state;
|
|
|
|
if (pCallback == NULL)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
state = hnor->State;
|
|
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
|
|
{
|
|
switch (CallbackId)
|
|
{
|
|
case HAL_NOR_MSP_INIT_CB_ID :
|
|
hnor->MspInitCallback = pCallback;
|
|
break;
|
|
case HAL_NOR_MSP_DEINIT_CB_ID :
|
|
hnor->MspDeInitCallback = pCallback;
|
|
break;
|
|
default :
|
|
/* update return status */
|
|
status = HAL_ERROR;
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* update return status */
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hnor);
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief Unregister a User NOR Callback
|
|
* NOR Callback is redirected to the weak (surcharged) predefined callback
|
|
* @param hnor : NOR handle
|
|
* @param CallbackId : ID of the callback to be unregistered
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
|
|
* @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
|
|
* @retval status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
|
|
{
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
HAL_NOR_StateTypeDef state;
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
state = hnor->State;
|
|
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
|
|
{
|
|
switch (CallbackId)
|
|
{
|
|
case HAL_NOR_MSP_INIT_CB_ID :
|
|
hnor->MspInitCallback = HAL_NOR_MspInit;
|
|
break;
|
|
case HAL_NOR_MSP_DEINIT_CB_ID :
|
|
hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
|
|
break;
|
|
default :
|
|
/* update return status */
|
|
status = HAL_ERROR;
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* update return status */
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hnor);
|
|
return status;
|
|
}
|
|
#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
|
|
* @brief management functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### NOR Control functions #####
|
|
==============================================================================
|
|
[..]
|
|
This subsection provides a set of functions allowing to control dynamically
|
|
the NOR interface.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enables dynamically NOR write operation.
|
|
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
|
|
* the configuration information for NOR module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
|
|
{
|
|
/* Check the NOR controller state */
|
|
if (hnor->State == HAL_NOR_STATE_PROTECTED)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
|
/* Enable write operation */
|
|
(void)FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Disables dynamically NOR write operation.
|
|
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
|
|
* the configuration information for NOR module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
|
|
{
|
|
/* Check the NOR controller state */
|
|
if (hnor->State == HAL_NOR_STATE_READY)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnor);
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
|
/* Disable write operation */
|
|
(void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
|
|
|
|
/* Update the NOR controller state */
|
|
hnor->State = HAL_NOR_STATE_PROTECTED;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnor);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
|
|
* @brief Peripheral State functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### NOR State functions #####
|
|
==============================================================================
|
|
[..]
|
|
This subsection permits to get in run-time the status of the NOR controller
|
|
and the data flow.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief return the NOR controller state
|
|
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
|
|
* the configuration information for NOR module.
|
|
* @retval NOR controller state
|
|
*/
|
|
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
|
|
{
|
|
return hnor->State;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the NOR operation status.
|
|
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
|
|
* the configuration information for NOR module.
|
|
* @param Address Device address
|
|
* @param Timeout NOR programming Timeout
|
|
* @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
|
|
* or HAL_NOR_STATUS_TIMEOUT
|
|
*/
|
|
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
|
|
{
|
|
HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
|
|
uint16_t tmpsr1;
|
|
uint16_t tmpsr2;
|
|
uint32_t tickstart;
|
|
|
|
/* Poll on NOR memory Ready/Busy signal ------------------------------------*/
|
|
HAL_NOR_MspWait(hnor, Timeout);
|
|
|
|
/* Get the NOR memory operation status -------------------------------------*/
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
|
|
{
|
|
while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
{
|
|
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
|
{
|
|
status = HAL_NOR_STATUS_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Read NOR status register (DQ6 and DQ5) */
|
|
tmpsr1 = *(__IO uint16_t *)Address;
|
|
tmpsr2 = *(__IO uint16_t *)Address;
|
|
|
|
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
|
|
if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
|
|
{
|
|
return HAL_NOR_STATUS_SUCCESS ;
|
|
}
|
|
|
|
if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
|
|
{
|
|
status = HAL_NOR_STATUS_ONGOING;
|
|
}
|
|
|
|
tmpsr1 = *(__IO uint16_t *)Address;
|
|
tmpsr2 = *(__IO uint16_t *)Address;
|
|
|
|
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
|
|
if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
|
|
{
|
|
return HAL_NOR_STATUS_SUCCESS;
|
|
}
|
|
if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
|
|
{
|
|
return HAL_NOR_STATUS_ERROR;
|
|
}
|
|
}
|
|
}
|
|
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
|
|
{
|
|
do
|
|
{
|
|
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
|
|
tmpsr2 = *(__IO uint16_t *)(Address);
|
|
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
{
|
|
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
|
{
|
|
return HAL_NOR_STATUS_TIMEOUT;
|
|
}
|
|
}
|
|
} while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U);
|
|
|
|
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
|
|
tmpsr1 = *(__IO uint16_t *)(Address);
|
|
if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U)
|
|
{
|
|
/* Clear the Status Register */
|
|
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
|
|
status = HAL_NOR_STATUS_ERROR;
|
|
}
|
|
else
|
|
{
|
|
status = HAL_NOR_STATUS_SUCCESS;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Primary command set not supported by the driver */
|
|
status = HAL_NOR_STATUS_ERROR;
|
|
}
|
|
|
|
/* Return the operation status */
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* HAL_NOR_MODULE_ENABLED */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|