1388 lines
53 KiB
C
1388 lines
53 KiB
C
/**
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******************************************************************************
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* @file stm32f7xx_ll_tim.c
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* @author MCD Application Team
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* @brief TIM LL module driver.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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#if defined(USE_FULL_LL_DRIVER)
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f7xx_ll_tim.h"
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#include "stm32f7xx_ll_bus.h"
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#ifdef USE_FULL_ASSERT
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#include "stm32_assert.h"
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#else
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#define assert_param(expr) ((void)0U)
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#endif /* USE_FULL_ASSERT */
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/** @addtogroup STM32F7xx_LL_Driver
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* @{
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*/
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#if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM6) || defined (TIM7)
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/** @addtogroup TIM_LL
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/** @addtogroup TIM_LL_Private_Macros
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* @{
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*/
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#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
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|| ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
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|| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
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|| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
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|| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
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#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
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|| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
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|| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
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#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
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|| ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
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|| ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
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|| ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
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|| ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
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|| ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
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|| ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
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|| ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
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|| ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
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|| ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
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|| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
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|| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
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|| ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
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|| ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
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#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
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|| ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
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#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
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|| ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
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#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
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|| ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
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#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
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|| ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
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|| ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
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#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
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|| ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
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|| ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
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|| ((__VALUE__) == LL_TIM_ICPSC_DIV8))
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#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
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|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
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|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
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|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
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|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
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|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
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|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
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|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
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|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
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|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
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|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
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|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
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|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
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|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
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|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
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|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
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#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
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|| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
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|| ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
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#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
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|| ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
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|| ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
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#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
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|| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
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#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
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|| ((__VALUE__) == LL_TIM_OSSR_ENABLE))
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#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
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|| ((__VALUE__) == LL_TIM_OSSI_ENABLE))
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#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
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|| ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
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|| ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
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|| ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
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#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
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|| ((__VALUE__) == LL_TIM_BREAK_ENABLE))
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#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
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|| ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
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#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
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|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
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|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
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|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
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|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
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|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
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|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
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|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
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|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
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|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
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|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
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|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
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|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
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|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
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|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
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|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
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#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
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|| ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
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#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
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|| ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
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#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
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|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
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|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
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|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
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|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
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|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
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|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
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|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
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|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
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|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
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|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
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|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
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|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
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|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
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|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
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|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
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#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
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|| ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
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/**
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* @}
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*/
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/* Private function prototypes -----------------------------------------------*/
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/** @defgroup TIM_LL_Private_Functions TIM Private Functions
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* @{
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*/
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static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
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static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
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static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
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static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
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static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
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static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
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static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
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static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
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static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
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static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup TIM_LL_Exported_Functions
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* @{
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*/
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/** @addtogroup TIM_LL_EF_Init
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* @{
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*/
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/**
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* @brief Set TIMx registers to their reset values.
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* @param TIMx Timer instance
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: TIMx registers are de-initialized
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* - ERROR: invalid TIMx instance
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*/
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ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
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{
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ErrorStatus result = SUCCESS;
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/* Check the parameters */
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assert_param(IS_TIM_INSTANCE(TIMx));
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if (TIMx == TIM1)
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{
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LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
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LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
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}
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else if (TIMx == TIM2)
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{
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LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
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LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
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}
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#if defined(TIM3)
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else if (TIMx == TIM3)
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{
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LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
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LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
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}
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#endif /* TIM3 */
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#if defined(TIM4)
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else if (TIMx == TIM4)
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{
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LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
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LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
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}
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#endif /* TIM4 */
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#if defined(TIM5)
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else if (TIMx == TIM5)
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{
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LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
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LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
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}
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#endif /* TIM5 */
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#if defined(TIM6)
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else if (TIMx == TIM6)
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{
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LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
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LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
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}
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#endif /* TIM6 */
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#if defined (TIM7)
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else if (TIMx == TIM7)
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{
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LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
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LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
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}
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#endif /* TIM7 */
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#if defined(TIM8)
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else if (TIMx == TIM8)
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{
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LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
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LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
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}
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#endif /* TIM8 */
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#if defined(TIM9)
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else if (TIMx == TIM9)
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{
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LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
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LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
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}
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#endif /* TIM9 */
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#if defined(TIM10)
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else if (TIMx == TIM10)
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{
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LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
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LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
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}
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#endif /* TIM10 */
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#if defined(TIM11)
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else if (TIMx == TIM11)
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{
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LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
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LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
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}
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#endif /* TIM11 */
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#if defined(TIM12)
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else if (TIMx == TIM12)
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{
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LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
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LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
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}
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#endif /* TIM12 */
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#if defined(TIM13)
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else if (TIMx == TIM13)
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{
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LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
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LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
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}
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#endif /* TIM13 */
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#if defined(TIM14)
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else if (TIMx == TIM14)
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{
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LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
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LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
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}
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#endif /* TIM14 */
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else
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{
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result = ERROR;
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}
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return result;
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}
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/**
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* @brief Set the fields of the time base unit configuration data structure
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* to their default values.
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* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
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* @retval None
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*/
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void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
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{
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/* Set the default configuration */
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TIM_InitStruct->Prescaler = (uint16_t)0x0000;
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TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
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TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
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TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
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TIM_InitStruct->RepetitionCounter = 0x00000000U;
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}
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/**
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* @brief Configure the TIMx time base unit.
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* @param TIMx Timer Instance
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* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
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* (TIMx time base unit configuration data structure)
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: TIMx registers are de-initialized
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* - ERROR: not applicable
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*/
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ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
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{
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uint32_t tmpcr1;
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/* Check the parameters */
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assert_param(IS_TIM_INSTANCE(TIMx));
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assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
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assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
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tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
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if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
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{
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/* Select the Counter Mode */
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MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
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}
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if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
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{
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/* Set the clock division */
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MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
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}
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/* Write to TIMx CR1 */
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LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
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/* Set the Autoreload value */
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LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
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/* Set the Prescaler value */
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LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
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if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
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{
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/* Set the Repetition Counter value */
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LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
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}
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/* Generate an update event to reload the Prescaler
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and the repetition counter value (if applicable) immediately */
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LL_TIM_GenerateEvent_UPDATE(TIMx);
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return SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* @brief Set the fields of the TIMx output channel configuration data
|
|
* structure to their default values.
|
|
* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
|
|
* (the output channel configuration data structure)
|
|
* @retval None
|
|
*/
|
|
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
|
|
{
|
|
/* Set the default configuration */
|
|
TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
|
|
TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
|
|
TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
|
|
TIM_OC_InitStruct->CompareValue = 0x00000000U;
|
|
TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
|
|
TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
|
|
TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
|
|
TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the TIMx output channel.
|
|
* @param TIMx Timer Instance
|
|
* @param Channel This parameter can be one of the following values:
|
|
* @arg @ref LL_TIM_CHANNEL_CH1
|
|
* @arg @ref LL_TIM_CHANNEL_CH2
|
|
* @arg @ref LL_TIM_CHANNEL_CH3
|
|
* @arg @ref LL_TIM_CHANNEL_CH4
|
|
* @arg @ref LL_TIM_CHANNEL_CH5
|
|
* @arg @ref LL_TIM_CHANNEL_CH6
|
|
* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
|
|
* data structure)
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: TIMx output channel is initialized
|
|
* - ERROR: TIMx output channel is not initialized
|
|
*/
|
|
ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
|
|
{
|
|
ErrorStatus result = ERROR;
|
|
|
|
switch (Channel)
|
|
{
|
|
case LL_TIM_CHANNEL_CH1:
|
|
result = OC1Config(TIMx, TIM_OC_InitStruct);
|
|
break;
|
|
case LL_TIM_CHANNEL_CH2:
|
|
result = OC2Config(TIMx, TIM_OC_InitStruct);
|
|
break;
|
|
case LL_TIM_CHANNEL_CH3:
|
|
result = OC3Config(TIMx, TIM_OC_InitStruct);
|
|
break;
|
|
case LL_TIM_CHANNEL_CH4:
|
|
result = OC4Config(TIMx, TIM_OC_InitStruct);
|
|
break;
|
|
case LL_TIM_CHANNEL_CH5:
|
|
result = OC5Config(TIMx, TIM_OC_InitStruct);
|
|
break;
|
|
case LL_TIM_CHANNEL_CH6:
|
|
result = OC6Config(TIMx, TIM_OC_InitStruct);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
/**
|
|
* @brief Set the fields of the TIMx input channel configuration data
|
|
* structure to their default values.
|
|
* @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
|
|
* data structure)
|
|
* @retval None
|
|
*/
|
|
void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
|
|
{
|
|
/* Set the default configuration */
|
|
TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
|
|
TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
|
|
TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
|
|
TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the TIMx input channel.
|
|
* @param TIMx Timer Instance
|
|
* @param Channel This parameter can be one of the following values:
|
|
* @arg @ref LL_TIM_CHANNEL_CH1
|
|
* @arg @ref LL_TIM_CHANNEL_CH2
|
|
* @arg @ref LL_TIM_CHANNEL_CH3
|
|
* @arg @ref LL_TIM_CHANNEL_CH4
|
|
* @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
|
|
* structure)
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: TIMx output channel is initialized
|
|
* - ERROR: TIMx output channel is not initialized
|
|
*/
|
|
ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
|
|
{
|
|
ErrorStatus result = ERROR;
|
|
|
|
switch (Channel)
|
|
{
|
|
case LL_TIM_CHANNEL_CH1:
|
|
result = IC1Config(TIMx, TIM_IC_InitStruct);
|
|
break;
|
|
case LL_TIM_CHANNEL_CH2:
|
|
result = IC2Config(TIMx, TIM_IC_InitStruct);
|
|
break;
|
|
case LL_TIM_CHANNEL_CH3:
|
|
result = IC3Config(TIMx, TIM_IC_InitStruct);
|
|
break;
|
|
case LL_TIM_CHANNEL_CH4:
|
|
result = IC4Config(TIMx, TIM_IC_InitStruct);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
/**
|
|
* @brief Fills each TIM_EncoderInitStruct field with its default value
|
|
* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
|
|
* configuration data structure)
|
|
* @retval None
|
|
*/
|
|
void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
|
|
{
|
|
/* Set the default configuration */
|
|
TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
|
|
TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
|
|
TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
|
|
TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
|
|
TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
|
|
TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
|
|
TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
|
|
TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
|
|
TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the encoder interface of the timer instance.
|
|
* @param TIMx Timer Instance
|
|
* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
|
|
* configuration data structure)
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: TIMx registers are de-initialized
|
|
* - ERROR: not applicable
|
|
*/
|
|
ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
|
|
{
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
|
|
assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
|
|
assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
|
|
assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
|
|
assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
|
|
assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
|
|
assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
|
|
assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
|
|
assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
|
|
assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
|
|
|
|
/* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
|
|
TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = LL_TIM_ReadReg(TIMx, CCER);
|
|
|
|
/* Configure TI1 */
|
|
tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
|
|
tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
|
|
tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
|
|
tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
|
|
|
|
/* Configure TI2 */
|
|
tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
|
|
tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
|
|
tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
|
|
tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
|
|
|
|
/* Set TI1 and TI2 polarity and enable TI1 and TI2 */
|
|
tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
|
tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
|
|
tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
|
|
tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
|
|
|
|
/* Set encoder mode */
|
|
LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
|
|
|
|
/* Write to TIMx CCER */
|
|
LL_TIM_WriteReg(TIMx, CCER, tmpccer);
|
|
|
|
return SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* @brief Set the fields of the TIMx Hall sensor interface configuration data
|
|
* structure to their default values.
|
|
* @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
|
|
* configuration data structure)
|
|
* @retval None
|
|
*/
|
|
void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
|
|
{
|
|
/* Set the default configuration */
|
|
TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
|
|
TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
|
|
TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
|
|
TIM_HallSensorInitStruct->CommutationDelay = 0U;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the Hall sensor interface of the timer instance.
|
|
* @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
|
|
* to the TI1 input channel
|
|
* @note TIMx slave mode controller is configured in reset mode.
|
|
Selected internal trigger is TI1F_ED.
|
|
* @note Channel 1 is configured as input, IC1 is mapped on TRC.
|
|
* @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
|
|
* between 2 changes on the inputs. It gives information about motor speed.
|
|
* @note Channel 2 is configured in output PWM 2 mode.
|
|
* @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
|
|
* @note OC2REF is selected as trigger output on TRGO.
|
|
* @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
|
|
* when TIMx operates in Hall sensor interface mode.
|
|
* @param TIMx Timer Instance
|
|
* @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
|
|
* interface configuration data structure)
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: TIMx registers are de-initialized
|
|
* - ERROR: not applicable
|
|
*/
|
|
ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
|
|
{
|
|
uint32_t tmpcr2;
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
|
|
assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
|
|
assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
|
|
assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
|
|
|
|
/* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
|
|
TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = LL_TIM_ReadReg(TIMx, CCER);
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
|
|
|
|
/* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
|
|
tmpcr2 |= TIM_CR2_TI1S;
|
|
|
|
/* OC2REF signal is used as trigger output (TRGO) */
|
|
tmpcr2 |= LL_TIM_TRGO_OC2REF;
|
|
|
|
/* Configure the slave mode controller */
|
|
tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
|
|
tmpsmcr |= LL_TIM_TS_TI1F_ED;
|
|
tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
|
|
|
|
/* Configure input channel 1 */
|
|
tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
|
|
tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
|
|
tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
|
|
tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
|
|
|
|
/* Configure input channel 2 */
|
|
tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
|
|
tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
|
|
|
|
/* Set Channel 1 polarity and enable Channel 1 and Channel2 */
|
|
tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
|
tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
|
|
tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
|
|
|
|
/* Write to TIMx CR2 */
|
|
LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
|
|
|
|
/* Write to TIMx SMCR */
|
|
LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
|
|
|
|
/* Write to TIMx CCER */
|
|
LL_TIM_WriteReg(TIMx, CCER, tmpccer);
|
|
|
|
/* Write to TIMx CCR2 */
|
|
LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
|
|
|
|
return SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* @brief Set the fields of the Break and Dead Time configuration data structure
|
|
* to their default values.
|
|
* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
|
|
* data structure)
|
|
* @retval None
|
|
*/
|
|
void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
|
|
{
|
|
/* Set the default configuration */
|
|
TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
|
|
TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
|
|
TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
|
|
TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
|
|
TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
|
|
TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
|
|
TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
|
|
TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
|
|
TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
|
|
TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
|
|
TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the Break and Dead Time feature of the timer instance.
|
|
* @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
|
|
* and DTG[7:0] can be write-locked depending on the LOCK configuration, it
|
|
* can be necessary to configure all of them during the first write access to
|
|
* the TIMx_BDTR register.
|
|
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
|
|
* a timer instance provides a break input.
|
|
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
|
|
* a timer instance provides a second break input.
|
|
* @param TIMx Timer Instance
|
|
* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
|
|
* data structure)
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: Break and Dead Time is initialized
|
|
* - ERROR: not applicable
|
|
*/
|
|
ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
|
|
{
|
|
uint32_t tmpbdtr = 0;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
|
|
assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
|
|
assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
|
|
assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
|
|
assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
|
|
assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
|
|
assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
|
|
|
|
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
|
|
the OSSI State, the dead time value and the Automatic Output Enable Bit */
|
|
|
|
/* Set the BDTR bits */
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
|
|
if (IS_TIM_ADVANCED_INSTANCE(TIMx))
|
|
{
|
|
assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
|
|
}
|
|
|
|
if (IS_TIM_BKIN2_INSTANCE(TIMx))
|
|
{
|
|
assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
|
|
assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
|
|
assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
|
|
|
|
/* Set the BREAK2 input related BDTR bit-fields */
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
|
|
}
|
|
|
|
/* Set TIMx_BDTR */
|
|
LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
|
|
|
|
return SUCCESS;
|
|
}
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
|
|
* @brief Private functions
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Configure the TIMx output channel 1.
|
|
* @param TIMx Timer Instance
|
|
* @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: TIMx registers are de-initialized
|
|
* - ERROR: not applicable
|
|
*/
|
|
static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
|
|
{
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
|
|
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
|
|
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
|
|
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
|
|
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
|
|
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = LL_TIM_ReadReg(TIMx, CCER);
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
|
|
|
|
/* Reset Capture/Compare selection Bits */
|
|
CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
|
|
|
|
/* Set the Output Compare Mode */
|
|
MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
|
|
|
|
/* Set the Output Compare Polarity */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
|
|
|
|
/* Set the Output State */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
{
|
|
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
|
|
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
|
|
|
|
/* Set the complementary output Polarity */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
|
|
|
|
/* Set the complementary output State */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
|
|
|
|
/* Set the Output Idle state */
|
|
MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
|
|
|
|
/* Set the complementary output Idle state */
|
|
MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
|
|
|
|
/* Set the Capture Compare Register value */
|
|
LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
|
|
|
|
/* Write to TIMx CCER */
|
|
LL_TIM_WriteReg(TIMx, CCER, tmpccer);
|
|
|
|
return SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the TIMx output channel 2.
|
|
* @param TIMx Timer Instance
|
|
* @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: TIMx registers are de-initialized
|
|
* - ERROR: not applicable
|
|
*/
|
|
static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
|
|
{
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC2_INSTANCE(TIMx));
|
|
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
|
|
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
|
|
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
|
|
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
|
|
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = LL_TIM_ReadReg(TIMx, CCER);
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
|
|
|
|
/* Reset Capture/Compare selection Bits */
|
|
CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
|
|
|
|
/* Select the Output Compare Mode */
|
|
MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
|
|
|
|
/* Set the Output Compare Polarity */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
|
|
|
|
/* Set the Output State */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
{
|
|
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
|
|
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
|
|
|
|
/* Set the complementary output Polarity */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
|
|
|
|
/* Set the complementary output State */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
|
|
|
|
/* Set the Output Idle state */
|
|
MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
|
|
|
|
/* Set the complementary output Idle state */
|
|
MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
|
|
|
|
/* Set the Capture Compare Register value */
|
|
LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
|
|
|
|
/* Write to TIMx CCER */
|
|
LL_TIM_WriteReg(TIMx, CCER, tmpccer);
|
|
|
|
return SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the TIMx output channel 3.
|
|
* @param TIMx Timer Instance
|
|
* @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: TIMx registers are de-initialized
|
|
* - ERROR: not applicable
|
|
*/
|
|
static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
|
|
{
|
|
uint32_t tmpccmr2;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC3_INSTANCE(TIMx));
|
|
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
|
|
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
|
|
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
|
|
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
|
|
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
|
|
|
|
/* Disable the Channel 3: Reset the CC3E Bit */
|
|
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = LL_TIM_ReadReg(TIMx, CCER);
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
|
|
|
|
/* Reset Capture/Compare selection Bits */
|
|
CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
|
|
|
|
/* Select the Output Compare Mode */
|
|
MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
|
|
|
|
/* Set the Output Compare Polarity */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
|
|
|
|
/* Set the Output State */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
{
|
|
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
|
|
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
|
|
|
|
/* Set the complementary output Polarity */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
|
|
|
|
/* Set the complementary output State */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
|
|
|
|
/* Set the Output Idle state */
|
|
MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
|
|
|
|
/* Set the complementary output Idle state */
|
|
MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
|
|
|
|
/* Set the Capture Compare Register value */
|
|
LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
|
|
|
|
/* Write to TIMx CCER */
|
|
LL_TIM_WriteReg(TIMx, CCER, tmpccer);
|
|
|
|
return SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the TIMx output channel 4.
|
|
* @param TIMx Timer Instance
|
|
* @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: TIMx registers are de-initialized
|
|
* - ERROR: not applicable
|
|
*/
|
|
static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
|
|
{
|
|
uint32_t tmpccmr2;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC4_INSTANCE(TIMx));
|
|
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
|
|
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
|
|
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
|
|
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
|
|
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
|
|
|
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
|
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = LL_TIM_ReadReg(TIMx, CCER);
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
|
|
|
|
/* Reset Capture/Compare selection Bits */
|
|
CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
|
|
|
|
/* Select the Output Compare Mode */
|
|
MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
|
|
|
|
/* Set the Output Compare Polarity */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
|
|
|
|
/* Set the Output State */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
{
|
|
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
|
|
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
|
|
|
|
/* Set the Output Idle state */
|
|
MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
|
|
|
|
/* Set the Capture Compare Register value */
|
|
LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
|
|
|
|
/* Write to TIMx CCER */
|
|
LL_TIM_WriteReg(TIMx, CCER, tmpccer);
|
|
|
|
return SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the TIMx output channel 5.
|
|
* @param TIMx Timer Instance
|
|
* @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: TIMx registers are de-initialized
|
|
* - ERROR: not applicable
|
|
*/
|
|
static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
|
|
{
|
|
uint32_t tmpccmr3;
|
|
uint32_t tmpccer;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC5_INSTANCE(TIMx));
|
|
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
|
|
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
|
|
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
|
|
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
|
|
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
|
|
|
|
/* Disable the Channel 5: Reset the CC5E Bit */
|
|
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = LL_TIM_ReadReg(TIMx, CCER);
|
|
|
|
/* Get the TIMx CCMR3 register value */
|
|
tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
|
|
|
|
/* Select the Output Compare Mode */
|
|
MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
|
|
|
|
/* Set the Output Compare Polarity */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
|
|
|
|
/* Set the Output State */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
{
|
|
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
|
|
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
|
|
|
|
/* Set the Output Idle state */
|
|
MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
|
|
|
|
}
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
|
|
|
|
/* Set the Capture Compare Register value */
|
|
LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
|
|
|
|
/* Write to TIMx CCER */
|
|
LL_TIM_WriteReg(TIMx, CCER, tmpccer);
|
|
|
|
return SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the TIMx output channel 6.
|
|
* @param TIMx Timer Instance
|
|
* @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: TIMx registers are de-initialized
|
|
* - ERROR: not applicable
|
|
*/
|
|
static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
|
|
{
|
|
uint32_t tmpccmr3;
|
|
uint32_t tmpccer;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC6_INSTANCE(TIMx));
|
|
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
|
|
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
|
|
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
|
|
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
|
|
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
|
|
|
|
/* Disable the Channel 5: Reset the CC6E Bit */
|
|
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = LL_TIM_ReadReg(TIMx, CCER);
|
|
|
|
/* Get the TIMx CCMR3 register value */
|
|
tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
|
|
|
|
/* Select the Output Compare Mode */
|
|
MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
|
|
|
|
/* Set the Output Compare Polarity */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
|
|
|
|
/* Set the Output State */
|
|
MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
{
|
|
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
|
|
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
|
|
|
|
/* Set the Output Idle state */
|
|
MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
|
|
}
|
|
|
|
/* Write to TIMx CCMR3 */
|
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LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
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|
|
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/* Set the Capture Compare Register value */
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LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
|
|
|
|
/* Write to TIMx CCER */
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LL_TIM_WriteReg(TIMx, CCER, tmpccer);
|
|
|
|
return SUCCESS;
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}
|
|
|
|
/**
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|
* @brief Configure the TIMx input channel 1.
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|
* @param TIMx Timer Instance
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|
* @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: TIMx registers are de-initialized
|
|
* - ERROR: not applicable
|
|
*/
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|
static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
|
|
assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
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|
assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
|
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assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
|
|
assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
|
|
|
|
/* Select the Input and set the filter and the prescaler value */
|
|
MODIFY_REG(TIMx->CCMR1,
|
|
(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
|
|
(TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
|
|
|
|
/* Select the Polarity and set the CC1E Bit */
|
|
MODIFY_REG(TIMx->CCER,
|
|
(TIM_CCER_CC1P | TIM_CCER_CC1NP),
|
|
(TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
|
|
|
|
return SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the TIMx input channel 2.
|
|
* @param TIMx Timer Instance
|
|
* @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: TIMx registers are de-initialized
|
|
* - ERROR: not applicable
|
|
*/
|
|
static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC2_INSTANCE(TIMx));
|
|
assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
|
|
assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
|
|
assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
|
|
assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
|
|
|
|
/* Select the Input and set the filter and the prescaler value */
|
|
MODIFY_REG(TIMx->CCMR1,
|
|
(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
|
|
(TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
|
|
|
|
/* Select the Polarity and set the CC2E Bit */
|
|
MODIFY_REG(TIMx->CCER,
|
|
(TIM_CCER_CC2P | TIM_CCER_CC2NP),
|
|
((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
|
|
|
|
return SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the TIMx input channel 3.
|
|
* @param TIMx Timer Instance
|
|
* @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: TIMx registers are de-initialized
|
|
* - ERROR: not applicable
|
|
*/
|
|
static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC3_INSTANCE(TIMx));
|
|
assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
|
|
assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
|
|
assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
|
|
assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
|
|
|
|
/* Disable the Channel 3: Reset the CC3E Bit */
|
|
TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
|
|
|
|
/* Select the Input and set the filter and the prescaler value */
|
|
MODIFY_REG(TIMx->CCMR2,
|
|
(TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
|
|
(TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
|
|
|
|
/* Select the Polarity and set the CC3E Bit */
|
|
MODIFY_REG(TIMx->CCER,
|
|
(TIM_CCER_CC3P | TIM_CCER_CC3NP),
|
|
((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
|
|
|
|
return SUCCESS;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the TIMx input channel 4.
|
|
* @param TIMx Timer Instance
|
|
* @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: TIMx registers are de-initialized
|
|
* - ERROR: not applicable
|
|
*/
|
|
static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC4_INSTANCE(TIMx));
|
|
assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
|
|
assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
|
|
assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
|
|
assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
|
|
|
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
|
TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
|
|
|
|
/* Select the Input and set the filter and the prescaler value */
|
|
MODIFY_REG(TIMx->CCMR2,
|
|
(TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
|
|
(TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
|
|
|
|
/* Select the Polarity and set the CC2E Bit */
|
|
MODIFY_REG(TIMx->CCER,
|
|
(TIM_CCER_CC4P | TIM_CCER_CC4NP),
|
|
((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
|
|
|
|
return SUCCESS;
|
|
}
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 ||TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM6 || TIM7 */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* USE_FULL_LL_DRIVER */
|
|
|