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Julien Chevalley
230
Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sram.h
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230
Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sram.h
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/**
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******************************************************************************
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* @file stm32f7xx_hal_sram.h
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* @author MCD Application Team
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* @brief Header file of SRAM HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32F7xx_HAL_SRAM_H
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#define STM32F7xx_HAL_SRAM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f7xx_ll_fmc.h"
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/** @addtogroup STM32F7xx_HAL_Driver
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* @{
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*/
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/** @addtogroup SRAM
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* @{
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*/
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/* Exported typedef ----------------------------------------------------------*/
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/** @defgroup SRAM_Exported_Types SRAM Exported Types
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* @{
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*/
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/**
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* @brief HAL SRAM State structures definition
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*/
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typedef enum
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{
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HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
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HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
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HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
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HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
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HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
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} HAL_SRAM_StateTypeDef;
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/**
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* @brief SRAM handle Structure definition
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*/
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#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
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typedef struct __SRAM_HandleTypeDef
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#else
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typedef struct
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#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
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{
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FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
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FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
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FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
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HAL_LockTypeDef Lock; /*!< SRAM locking object */
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__IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
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DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
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#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
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void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */
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void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */
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void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */
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void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */
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#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
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} SRAM_HandleTypeDef;
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#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
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/**
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* @brief HAL SRAM Callback ID enumeration definition
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*/
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typedef enum
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{
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HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */
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HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */
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HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */
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HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */
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} HAL_SRAM_CallbackIDTypeDef;
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/**
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* @brief HAL SRAM Callback pointer definition
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*/
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typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
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typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
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#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/* Exported macro ------------------------------------------------------------*/
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/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
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* @{
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*/
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/** @brief Reset SRAM handle state
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* @param __HANDLE__ SRAM handle
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* @retval None
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*/
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#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
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#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \
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(__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
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(__HANDLE__)->MspInitCallback = NULL; \
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(__HANDLE__)->MspDeInitCallback = NULL; \
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} while(0)
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#else
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#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
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#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
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* @{
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*/
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/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
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* @{
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*/
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/* Initialization/de-initialization functions ********************************/
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HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
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FMC_NORSRAM_TimingTypeDef *ExtTiming);
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HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
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void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
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void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
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/**
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* @}
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*/
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/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
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* @{
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*/
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/* I/O operation functions ***************************************************/
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HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
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uint32_t BufferSize);
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HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
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uint32_t BufferSize);
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HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
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uint32_t BufferSize);
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HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
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uint32_t BufferSize);
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HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
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uint32_t BufferSize);
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HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
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uint32_t BufferSize);
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HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
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uint32_t BufferSize);
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HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
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uint32_t BufferSize);
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void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
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void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
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#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
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/* SRAM callback registering/unregistering */
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HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
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pSRAM_CallbackTypeDef pCallback);
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HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
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HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
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pSRAM_DmaCallbackTypeDef pCallback);
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#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
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/**
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* @}
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*/
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/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
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* @{
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*/
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/* SRAM Control functions ****************************************************/
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HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
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HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
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/**
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* @}
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*/
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/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
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* @{
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*/
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/* SRAM State functions ******************************************************/
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HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* STM32F7xx_HAL_SRAM_H */
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