Initial commit
This commit is contained in:
Julien Chevalley
377
Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nand.h
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377
Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nand.h
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/**
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******************************************************************************
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* @file stm32f7xx_hal_nand.h
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* @author MCD Application Team
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* @brief Header file of NAND HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32F7xx_HAL_NAND_H
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#define STM32F7xx_HAL_NAND_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f7xx_ll_fmc.h"
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/** @addtogroup STM32F7xx_HAL_Driver
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* @{
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*/
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/** @addtogroup NAND
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* @{
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*/
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/* Exported typedef ----------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup NAND_Exported_Types NAND Exported Types
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* @{
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*/
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/**
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* @brief HAL NAND State structures definition
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*/
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typedef enum
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{
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HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
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HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
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HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
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HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
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} HAL_NAND_StateTypeDef;
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/**
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* @brief NAND Memory electronic signature Structure definition
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*/
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typedef struct
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{
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/*<! NAND memory electronic signature maker and device IDs */
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uint8_t Maker_Id;
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uint8_t Device_Id;
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uint8_t Third_Id;
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uint8_t Fourth_Id;
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} NAND_IDTypeDef;
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/**
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* @brief NAND Memory address Structure definition
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*/
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typedef struct
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{
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uint16_t Page; /*!< NAND memory Page address */
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uint16_t Plane; /*!< NAND memory Zone address */
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uint16_t Block; /*!< NAND memory Block address */
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} NAND_AddressTypeDef;
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/**
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* @brief NAND Memory info Structure definition
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*/
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typedef struct
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{
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uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
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for 8 bits addressing or words for 16 bits addressing */
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uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
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for 8 bits addressing or words for 16 bits addressing */
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uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
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uint32_t BlockNbr; /*!< NAND memory number of total blocks */
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uint32_t PlaneNbr; /*!< NAND memory number of planes */
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uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */
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FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
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parameter is mandatory for some NAND parts after the read
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command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
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Example: Toshiba THTH58BYG3S0HBAI6.
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This parameter could be ENABLE or DISABLE
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Please check the Read Mode sequnece in the NAND device datasheet */
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} NAND_DeviceConfigTypeDef;
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/**
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* @brief NAND handle Structure definition
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*/
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#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
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typedef struct __NAND_HandleTypeDef
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#else
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typedef struct
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#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
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{
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FMC_NAND_TypeDef *Instance; /*!< Register base address */
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FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
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HAL_LockTypeDef Lock; /*!< NAND locking object */
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__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
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NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
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#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
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void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
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void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */
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void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */
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#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
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} NAND_HandleTypeDef;
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#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
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/**
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* @brief HAL NAND Callback ID enumeration definition
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*/
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typedef enum
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{
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HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */
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HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */
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HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */
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} HAL_NAND_CallbackIDTypeDef;
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/**
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* @brief HAL NAND Callback pointer definition
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*/
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typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
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#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/* Exported macro ------------------------------------------------------------*/
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/** @defgroup NAND_Exported_Macros NAND Exported Macros
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* @{
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*/
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/** @brief Reset NAND handle state
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* @param __HANDLE__ specifies the NAND handle.
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* @retval None
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*/
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#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
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#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \
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(__HANDLE__)->State = HAL_NAND_STATE_RESET; \
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(__HANDLE__)->MspInitCallback = NULL; \
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(__HANDLE__)->MspDeInitCallback = NULL; \
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} while(0)
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#else
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#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
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#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup NAND_Exported_Functions NAND Exported Functions
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* @{
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*/
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/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
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* @{
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*/
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/* Initialization/de-initialization functions ********************************/
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HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
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FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
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HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
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HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
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HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
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void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
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void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
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void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
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void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
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/**
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* @}
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*/
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/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
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* @{
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*/
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/* IO operation functions ****************************************************/
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HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
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HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
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uint32_t NumPageToRead);
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HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
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uint32_t NumPageToWrite);
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HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
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uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
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HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
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uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
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HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
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uint32_t NumPageToRead);
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HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
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uint32_t NumPageToWrite);
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HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
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uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
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HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
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uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
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HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
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uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
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#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
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/* NAND callback registering/unregistering */
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HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
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pNAND_CallbackTypeDef pCallback);
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HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
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#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
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/**
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* @}
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*/
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/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
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* @{
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*/
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/* NAND Control functions ****************************************************/
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HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
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HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
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HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
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/**
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* @}
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*/
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/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
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* @{
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*/
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/* NAND State functions *******************************************************/
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HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
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uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/** @defgroup NAND_Private_Constants NAND Private Constants
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* @{
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*/
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#define NAND_DEVICE 0x80000000UL
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#define NAND_WRITE_TIMEOUT 0x01000000UL
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#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
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#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
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#define NAND_CMD_AREA_A ((uint8_t)0x00)
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#define NAND_CMD_AREA_B ((uint8_t)0x01)
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#define NAND_CMD_AREA_C ((uint8_t)0x50)
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#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
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#define NAND_CMD_WRITE0 ((uint8_t)0x80)
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#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
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#define NAND_CMD_ERASE0 ((uint8_t)0x60)
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#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
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#define NAND_CMD_READID ((uint8_t)0x90)
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#define NAND_CMD_STATUS ((uint8_t)0x70)
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#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
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#define NAND_CMD_RESET ((uint8_t)0xFF)
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/* NAND memory status */
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#define NAND_VALID_ADDRESS 0x00000100UL
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#define NAND_INVALID_ADDRESS 0x00000200UL
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#define NAND_TIMEOUT_ERROR 0x00000400UL
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#define NAND_BUSY 0x00000000UL
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#define NAND_ERROR 0x00000001UL
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#define NAND_READY 0x00000040UL
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/** @defgroup NAND_Private_Macros NAND Private Macros
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* @{
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*/
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/**
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* @brief NAND memory address computation.
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* @param __ADDRESS__ NAND memory address.
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* @param __HANDLE__ NAND handle.
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* @retval NAND Raw address value
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*/
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#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
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(((__ADDRESS__)->Block + \
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(((__ADDRESS__)->Plane) * \
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((__HANDLE__)->Config.PlaneSize))) * \
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((__HANDLE__)->Config.BlockSize)))
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/**
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* @brief NAND memory Column address computation.
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* @param __HANDLE__ NAND handle.
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* @retval NAND Raw address value
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*/
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#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
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/**
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* @brief NAND memory address cycling.
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* @param __ADDRESS__ NAND memory address.
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* @retval NAND address cycling value.
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*/
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#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
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#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
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#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
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#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
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/**
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* @brief NAND memory Columns cycling.
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* @param __ADDRESS__ NAND memory address.
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* @retval NAND Column address cycling value.
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*/
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#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */
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#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* STM32F7xx_HAL_NAND_H */
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