8 lines
		
	
	
		
			130 B
		
	
	
	
		
			VHDL
		
	
	
	
	
	
			
		
		
	
	
			8 lines
		
	
	
		
			130 B
		
	
	
	
		
			VHDL
		
	
	
	
	
	
| ARCHITECTURE studentVersion OF pipelineAdder IS
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| BEGIN
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| 
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|   sum <= (others => '0');
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|   cOut <= '0';
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| 
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| END ARCHITECTURE studentVersion;
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