2569 lines
32 KiB
Plaintext
2569 lines
32 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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instances [
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(Instance
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name "I_DUT"
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duLibraryName "PipelinedOperators"
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duName "pipelineCounter"
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elements [
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(GiElement
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name "bitNb"
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type "positive"
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value "counterBitNb"
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)
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(GiElement
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name "stageNb"
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type "positive"
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value "pipelineStageNb"
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mwi 0
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uid 2719,0
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(Instance
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name "I_tester"
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duLibraryName "PipelinedOperators_test"
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duName "PipelineCounter_tester"
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elements [
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(GiElement
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name "counterBitNb"
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type "integer"
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value "counterBitNb"
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(GiElement
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name "clockFrequency"
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type "real"
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value "clockFrequency"
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mwi 0
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uid 2970,0
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libraryRefs [
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"ieee"
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]
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)
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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model (BlockDiag
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VExpander (VariableExpander
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vvMap [
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(vvPair
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variable " "
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value " "
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)
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(vvPair
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variable "HDLDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hdl"
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)
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(vvPair
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variable "HDSDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds"
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)
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(vvPair
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variable "SideDataDesignDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@counter_tb\\struct.bd.info"
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)
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(vvPair
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variable "SideDataUserDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@counter_tb\\struct.bd.user"
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)
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(vvPair
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variable "SourceDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds"
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)
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(vvPair
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variable "appl"
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value "HDL Designer"
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)
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(vvPair
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variable "arch_name"
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value "struct"
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)
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(vvPair
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variable "asm_file"
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value "beamer.asm"
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)
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(vvPair
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variable "concat_file"
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value "concatenated"
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)
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(vvPair
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variable "config"
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value "%(unit)_%(view)_config"
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)
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(vvPair
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variable "d"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@counter_tb"
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)
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(vvPair
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variable "d_logical"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipelineCounter_tb"
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(vvPair
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variable "date"
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value "28.04.2023"
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(vvPair
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variable "day"
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value "ven."
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)
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(vvPair
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variable "day_long"
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value "vendredi"
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)
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(vvPair
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variable "dd"
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value "28"
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)
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(vvPair
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variable "designName"
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value "$DESIGN_NAME"
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)
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(vvPair
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variable "entity_name"
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value "pipelineCounter_tb"
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)
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(vvPair
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variable "ext"
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value "<TBD>"
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)
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(vvPair
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variable "f"
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value "struct.bd"
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)
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(vvPair
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variable "f_logical"
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value "struct.bd"
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)
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(vvPair
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variable "f_noext"
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value "struct"
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(vvPair
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variable "graphical_source_author"
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value "axel.amand"
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variable "graphical_source_date"
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value "28.04.2023"
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(vvPair
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variable "graphical_source_group"
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value "UNKNOWN"
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(vvPair
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variable "graphical_source_host"
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value "WE7860"
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(vvPair
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variable "graphical_source_time"
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value "15:21:02"
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(vvPair
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variable "group"
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value "UNKNOWN"
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(vvPair
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variable "host"
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value "WE7860"
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(vvPair
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variable "language"
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value "VHDL"
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(vvPair
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variable "library"
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value "PipelinedOperators_test"
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)
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(vvPair
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variable "library_downstream_ModelSim"
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value "D:\\Users\\ELN_labs\\VHDL_comp"
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)
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(vvPair
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variable "library_downstream_ModelSimCompiler"
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value "$SCRATCH_DIR/PipelinedOperators_test"
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)
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(vvPair
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variable "mm"
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value "04"
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)
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(vvPair
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variable "module_name"
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value "pipelineCounter_tb"
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)
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(vvPair
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variable "month"
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value "avr."
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)
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(vvPair
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variable "month_long"
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value "avril"
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(vvPair
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variable "p"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@counter_tb\\struct.bd"
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)
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(vvPair
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variable "p_logical"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipelineCounter_tb\\struct.bd"
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)
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(vvPair
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variable "package_name"
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value "<Undefined Variable>"
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)
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(vvPair
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variable "project_name"
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value "hds"
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)
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(vvPair
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variable "series"
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value "HDL Designer Series"
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)
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(vvPair
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variable "task_ADMS"
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value "<TBD>"
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)
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(vvPair
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variable "task_AsmPath"
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value "$HEI_LIBS_DIR/NanoBlaze/hdl"
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(vvPair
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variable "task_DesignCompilerPath"
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value "<TBD>"
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(vvPair
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variable "task_HDSPath"
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value "$HDS_HOME"
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(vvPair
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variable "task_ISEBinPath"
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(vvPair
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variable "task_ISEPath"
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value "$ISE_WORK_DIR"
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(vvPair
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variable "task_LeonardoPath"
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value "<TBD>"
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(vvPair
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variable "task_ModelSimPath"
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value "$MODELSIM_HOME/modeltech/bin"
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(vvPair
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variable "task_NC"
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value "<TBD>"
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(vvPair
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variable "task_PrecisionRTLPath"
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value "<TBD>"
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)
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(vvPair
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variable "task_QuestaSimPath"
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value "<TBD>"
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)
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(vvPair
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variable "task_VCSPath"
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value "<TBD>"
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(vvPair
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variable "this_ext"
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value "bd"
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(vvPair
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variable "this_file"
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value "struct"
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(vvPair
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variable "this_file_logical"
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value "struct"
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(vvPair
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variable "time"
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value "15:21:02"
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(vvPair
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variable "unit"
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value "pipelineCounter_tb"
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variable "user"
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value "axel.amand"
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variable "version"
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value "2019.2 (Build 5)"
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(vvPair
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variable "view"
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value "struct"
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(vvPair
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variable "year"
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value "2023"
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(vvPair
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variable "yy"
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value "23"
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elements [
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shape (Rectangle
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stg "VerticalLayoutStrategy"
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tm "HdlTextNameMgr"
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tm "HdlTextNumberMgr"
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defaultEmbeddedText (EmbeddedText
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commentText (CommentText
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shape (Rectangle
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text (MLText
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tm "HdlTextMgr"
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defaultBdJunction (BdJunction
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ps "OnConnectorStrategy"
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shape (Circle
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defaultPortIoIn (PortIoIn
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shape (CompositeShape
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vasetType 1
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fg "0,0,32768"
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tg (WTG
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ps "PortIoTextPlaceStrategy"
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stg "STSignalDisplayStrategy"
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ju 2
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blo "-1375,-1000"
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tm "WireNameMgr"
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)
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defaultPortIoOut (PortIoOut
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shape (CompositeShape
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va (VaSet
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optionalChildren [
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pts [
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tg (WTG
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ps "PortIoTextPlaceStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
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va (VaSet
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font "Verdana,12,0"
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blo "625,-1000"
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tm "WireNameMgr"
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)
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defaultPortIoInOut (PortIoInOut
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shape (CompositeShape
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fg "0,0,32768"
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optionalChildren [
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)
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tg (WTG
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ps "PortIoTextPlaceStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
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va (VaSet
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font "Verdana,12,0"
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)
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|
blo "0,-375"
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|
tm "WireNameMgr"
|
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)
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)
|
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)
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defaultPortIoBuffer (PortIoBuffer
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shape (CompositeShape
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va (VaSet
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|
fg "65535,65535,65535"
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lineColor "0,0,32768"
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optionalChildren [
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pts [
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tg (WTG
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stg "STSignalDisplayStrategy"
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f (Text
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va (VaSet
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font "Verdana,12,0"
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|
blo "0,-375"
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tm "WireNameMgr"
|
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|
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)
|
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)
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defaultSignal (Wire
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shape (OrthoPolyLine
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va (VaSet
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vasetType 3
|
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pts [
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)
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|
|
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sat 32
|
|
eat 32
|
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stc 0
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sf 1
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si 0
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tg (WTG
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ps "ConnStartEndStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
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va (VaSet
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font "Verdana,12,0"
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)
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st "sig0"
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|
blo "0,1200"
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tm "WireNameMgr"
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)
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)
|
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)
|
|
defaultBus (Wire
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shape (OrthoPolyLine
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va (VaSet
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pts [
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)
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|
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sat 32
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eat 32
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sty 1
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stc 0
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|
sf 1
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si 0
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tg (WTG
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ps "ConnStartEndStrategy"
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stg "STSignalDisplayStrategy"
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va (VaSet
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)
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|
st "dbus0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
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|
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)
|
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)
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defaultBundle (Bundle
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shape (OrthoPolyLine
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va (VaSet
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vasetType 3
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lineWidth 1
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)
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pts [
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"0,0"
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]
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)
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sat 32
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eat 32
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textGroup (BiTextGroup
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ps "ConnStartEndStrategy"
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stg "VerticalLayoutStrategy"
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first (Text
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va (VaSet
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xt "0,0,2600,1000"
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st "bundle0"
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blo "0,800"
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tm "BundleNameMgr"
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)
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second (MLText
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va (VaSet
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xt "0,1000,1500,2200"
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st "()"
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tm "BundleContentsMgr"
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bundleNet &0
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defaultPortMapFrame (PortMapFrame
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ps "PortMapFrameStrategy"
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shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,50000"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,0,5000,1200"
|
|
st "Auto list"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,9600,2200"
|
|
st "User defined list"
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,18500,100"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*56 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*57 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,11000,100"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*58 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*59 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,5600,6500,6500"
|
|
st "Declarations"
|
|
blo "0,6300"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,6500,3000,7400"
|
|
st "Ports:"
|
|
blo "0,7200"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,7400,4500,8300"
|
|
st "Pre User:"
|
|
blo "0,8100"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,8300,22100,12300"
|
|
st "constant counterBitNb: positive := 20;
|
|
constant pipelineStageNb: positive := 5;
|
|
constant clockFrequency : real := 60.0E6;
|
|
--constant clockFrequency : real := 66.0E6;"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,12300,8500,13200"
|
|
st "Diagram Signals:"
|
|
blo "0,13000"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,5600,5500,6500"
|
|
st "Post User:"
|
|
blo "0,6300"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,5600,0,5600"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 28,0
|
|
usingSuid 1
|
|
emptyRow *60 (LEmptyRow
|
|
)
|
|
uid 1321,0
|
|
optionalChildren [
|
|
*61 (RefLabelRowHdr
|
|
)
|
|
*62 (TitleRowHdr
|
|
)
|
|
*63 (FilterRowHdr
|
|
)
|
|
*64 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*65 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*66 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*67 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*68 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*69 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*70 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*71 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*72 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*73 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 25,0
|
|
)
|
|
)
|
|
uid 2672,0
|
|
)
|
|
*74 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 26,0
|
|
)
|
|
)
|
|
uid 2674,0
|
|
)
|
|
*75 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "countOut"
|
|
t "unsigned"
|
|
b "(counterBitNb-1 downto 0)"
|
|
o 2
|
|
suid 28,0
|
|
)
|
|
)
|
|
uid 2736,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 1334,0
|
|
optionalChildren [
|
|
*76 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *77 (MRCItem
|
|
litem &60
|
|
pos 3
|
|
dimension 20
|
|
)
|
|
uid 1336,0
|
|
optionalChildren [
|
|
*78 (MRCItem
|
|
litem &61
|
|
pos 0
|
|
dimension 20
|
|
uid 1337,0
|
|
)
|
|
*79 (MRCItem
|
|
litem &62
|
|
pos 1
|
|
dimension 23
|
|
uid 1338,0
|
|
)
|
|
*80 (MRCItem
|
|
litem &63
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 1339,0
|
|
)
|
|
*81 (MRCItem
|
|
litem &73
|
|
pos 0
|
|
dimension 20
|
|
uid 2673,0
|
|
)
|
|
*82 (MRCItem
|
|
litem &74
|
|
pos 1
|
|
dimension 20
|
|
uid 2675,0
|
|
)
|
|
*83 (MRCItem
|
|
litem &75
|
|
pos 2
|
|
dimension 20
|
|
uid 2737,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 1340,0
|
|
optionalChildren [
|
|
*84 (MRCItem
|
|
litem &64
|
|
pos 0
|
|
dimension 20
|
|
uid 1341,0
|
|
)
|
|
*85 (MRCItem
|
|
litem &66
|
|
pos 1
|
|
dimension 50
|
|
uid 1342,0
|
|
)
|
|
*86 (MRCItem
|
|
litem &67
|
|
pos 2
|
|
dimension 100
|
|
uid 1343,0
|
|
)
|
|
*87 (MRCItem
|
|
litem &68
|
|
pos 3
|
|
dimension 50
|
|
uid 1344,0
|
|
)
|
|
*88 (MRCItem
|
|
litem &69
|
|
pos 4
|
|
dimension 100
|
|
uid 1345,0
|
|
)
|
|
*89 (MRCItem
|
|
litem &70
|
|
pos 5
|
|
dimension 100
|
|
uid 1346,0
|
|
)
|
|
*90 (MRCItem
|
|
litem &71
|
|
pos 6
|
|
dimension 50
|
|
uid 1347,0
|
|
)
|
|
*91 (MRCItem
|
|
litem &72
|
|
pos 7
|
|
dimension 80
|
|
uid 1348,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 1335,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 1320,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *92 (LEmptyRow
|
|
)
|
|
uid 1350,0
|
|
optionalChildren [
|
|
*93 (RefLabelRowHdr
|
|
)
|
|
*94 (TitleRowHdr
|
|
)
|
|
*95 (FilterRowHdr
|
|
)
|
|
*96 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*97 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*98 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*99 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*100 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*101 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*102 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*103 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 1362,0
|
|
optionalChildren [
|
|
*104 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *105 (MRCItem
|
|
litem &92
|
|
pos 0
|
|
dimension 20
|
|
)
|
|
uid 1364,0
|
|
optionalChildren [
|
|
*106 (MRCItem
|
|
litem &93
|
|
pos 0
|
|
dimension 20
|
|
uid 1365,0
|
|
)
|
|
*107 (MRCItem
|
|
litem &94
|
|
pos 1
|
|
dimension 23
|
|
uid 1366,0
|
|
)
|
|
*108 (MRCItem
|
|
litem &95
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 1367,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 1368,0
|
|
optionalChildren [
|
|
*109 (MRCItem
|
|
litem &96
|
|
pos 0
|
|
dimension 20
|
|
uid 1369,0
|
|
)
|
|
*110 (MRCItem
|
|
litem &98
|
|
pos 1
|
|
dimension 50
|
|
uid 1370,0
|
|
)
|
|
*111 (MRCItem
|
|
litem &99
|
|
pos 2
|
|
dimension 100
|
|
uid 1371,0
|
|
)
|
|
*112 (MRCItem
|
|
litem &100
|
|
pos 3
|
|
dimension 100
|
|
uid 1372,0
|
|
)
|
|
*113 (MRCItem
|
|
litem &101
|
|
pos 4
|
|
dimension 50
|
|
uid 1373,0
|
|
)
|
|
*114 (MRCItem
|
|
litem &102
|
|
pos 5
|
|
dimension 50
|
|
uid 1374,0
|
|
)
|
|
*115 (MRCItem
|
|
litem &103
|
|
pos 6
|
|
dimension 80
|
|
uid 1375,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 1363,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 1349,0
|
|
type 1
|
|
)
|
|
activeModelName "BlockDiag"
|
|
)
|