28 lines
946 B
VHDL
28 lines
946 B
VHDL
ARCHITECTURE studentVersion OF interpolatorCoefficients IS
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subtype sample is signed(bitNb-1 DOWNTO 0);
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subtype coeff is signed(coeffBitNb-1 DOWNTO 0);
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type samples_type is array (1 to 4) of coeff;
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signal samples: samples_type;
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BEGIN
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-- a = - sample1 +3·sample2 -3·sample3 + sample4
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-- b = 2·sample1 -5·sample2 +4·sample3 - sample4
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-- c = - sample1 + sample3
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-- d = sample2
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process(sample1, sample2, sample3, sample4) begin
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samples(1) <= resize(sample1, coeff'high+1);
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samples(2) <= resize(sample2, coeff'high+1);
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samples(3) <= resize(sample3, coeff'high+1);
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samples(4) <= resize(sample4, coeff'high+1);
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end process;
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a <= samples(4) - samples(1) + resize( 3*(samples(2) - samples(3)), coeff'high+1);
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b <= resize(2*samples(1), coeff'high+1) - resize(5*samples(2), coeff'high+1) + resize(4*samples(3), coeff'high+1) - samples(4);
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c <= samples(3) - samples(1);
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d <= samples(2);
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END ARCHITECTURE studentVersion;
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