120 lines
3.6 KiB
VHDL
120 lines
3.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use std.textio.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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context vunit_lib.com_context;
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context vunit_lib.vc_context;
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use work.uart_rx_pkg.all;
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entity uart_rx is
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generic (handle : uart_rx_t);
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port (
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clk : in std_ulogic;
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uart_txd : in std_ulogic
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);
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end entity;
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architecture a of uart_rx is
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signal uart_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
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signal uart_rx_busy : std_ulogic := '0';
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signal uart_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
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signal uart_rx_baud_cnt : real;
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signal uart_rx_bitcnt : natural;
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file file_uart_tx_out : text open write_mode is "neorv32.testbench_" & get_name(handle.p_logger) & ".out";
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constant checker : checker_t := new_checker(handle.p_logger);
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constant character_queue : queue_t := new_queue;
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begin
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control : process
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variable request_msg, reply_msg : msg_t;
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variable msg_type : msg_type_t;
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procedure put_characters_in_queue(s : string) is
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begin
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for idx in s'range loop
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push(character_queue, s(idx));
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end loop;
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end procedure put_characters_in_queue;
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begin
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receive(net, handle.p_actor, request_msg);
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msg_type := message_type(request_msg);
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-- Standard handling of standard wait_for_time messages = wait for the given time
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-- before proceeeding
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handle_wait_for_time(net, msg_type, request_msg);
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if msg_type = check_uart_msg then
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put_characters_in_queue(pop(request_msg));
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-- Custom handling of standard wait_until_idle message
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elsif msg_type = wait_until_idle_msg then
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while not is_empty(character_queue) loop
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wait until rising_edge(clk);
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end loop;
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reply_msg := new_msg(wait_until_idle_reply_msg);
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reply(net, request_msg, reply_msg);
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else
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unexpected_msg_type(msg_type);
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end if;
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end process;
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uart_rx_console : process(clk)
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variable i : integer;
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variable l : line;
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variable expected_character : character;
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begin
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-- "UART" --
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if rising_edge(clk) then
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-- synchronizer --
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uart_rx_sync <= uart_rx_sync(3 downto 0) & uart_txd;
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-- arbiter --
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if (uart_rx_busy = '0') then -- idle
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uart_rx_busy <= '0';
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uart_rx_baud_cnt <= round(0.5 * handle.p_baud_val);
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uart_rx_bitcnt <= 9;
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if (uart_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
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uart_rx_busy <= '1';
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end if;
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else
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if (uart_rx_baud_cnt <= 0.0) then
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if (uart_rx_bitcnt = 1) then
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uart_rx_baud_cnt <= round(0.5 * handle.p_baud_val);
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else
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uart_rx_baud_cnt <= round(handle.p_baud_val);
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end if;
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if (uart_rx_bitcnt = 0) then
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uart_rx_busy <= '0'; -- done
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i := to_integer(unsigned(uart_rx_sreg(8 downto 1)));
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if is_empty(character_queue) then
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check_failed(checker, "Extra characters received");
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else
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expected_character := pop(character_queue);
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check_equal(checker, character'val(i), expected_character);
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end if;
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if (i = 10) then -- Linux line break
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writeline(file_uart_tx_out, l);
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elsif (i /= 13) then -- Remove additional carriage return
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write(l, character'val(i));
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end if;
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else
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uart_rx_sreg <= uart_rx_sync(4) & uart_rx_sreg(8 downto 1);
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uart_rx_bitcnt <= uart_rx_bitcnt - 1;
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end if;
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else
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uart_rx_baud_cnt <= uart_rx_baud_cnt - 1.0;
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end if;
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end if;
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end if;
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end process uart_rx_console;
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end architecture;
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