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SEm-Labos/Libs/RiscV/HEIRV32/MultiCycle/hds/control@unit/struct.bd
github-classroom[bot] d212040c30 Initial commit
2024-02-23 13:01:05 +00:00

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DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "numeric_std"
)
(DmPackageRef
library "gates"
unitName "gates"
)
]
instances [
(Instance
name "U_0"
duLibraryName "gates"
duName "or2"
elements [
(GiElement
name "delay"
type "time"
value "gateDelay"
)
]
mwi 0
uid 395,0
)
(Instance
name "U_1"
duLibraryName "gates"
duName "and2"
elements [
(GiElement
name "delay"
type "time"
value "gateDelay"
)
]
mwi 0
uid 420,0
)
(Instance
name "U_instrDecoder"
duLibraryName "HEIRV32_MC"
duName "instrDecoder"
elements [
]
mwi 0
uid 955,0
)
(Instance
name "U_mainFSM"
duLibraryName "HEIRV32_MC"
duName "mainFSM"
elements [
]
mwi 0
uid 1230,0
)
(Instance
name "U_aluDecoder"
duLibraryName "HEIRV32"
duName "aluDecoder"
elements [
(GiElement
name "g_tDec"
type "time"
value "25 ps"
)
]
mwi 0
uid 1415,0
)
]
libraryRefs [
"ieee"
"gates"
]
)
version "32.1"
appVersion "2019.2 (Build 5)"
noEmbeddedEditors 1
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds\\control@unit\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds\\control@unit\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "concat_file"
value "concatenated"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds\\control@unit"
)
(vvPair
variable "d_logical"
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds\\controlUnit"
)
(vvPair
variable "date"
value "04.11.2022"
)
(vvPair
variable "day"
value "ven."
)
(vvPair
variable "day_long"
value "vendredi"
)
(vvPair
variable "dd"
value "04"
)
(vvPair
variable "entity_name"
value "controlUnit"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "f_noext"
value "struct"
)
(vvPair
variable "graphical_source_author"
value "axel.amand"
)
(vvPair
variable "graphical_source_date"
value "04.11.2022"
)
(vvPair
variable "graphical_source_group"
value "UNKNOWN"
)
(vvPair
variable "graphical_source_host"
value "WE7860"
)
(vvPair
variable "graphical_source_time"
value "11:25:25"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "WE7860"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "HEIRV32_MC"
)
(vvPair
variable "library_downstream_Concatenation"
value "$HDS_PROJECT_DIR/../Board/concat"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/CAr/RiscV/HEIRV32/MultiCycle/work"
)
(vvPair
variable "mm"
value "11"
)
(vvPair
variable "module_name"
value "controlUnit"
)
(vvPair
variable "month"
value "nov."
)
(vvPair
variable "month_long"
value "novembre"
)
(vvPair
variable "p"
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds\\control@unit\\struct.bd"
)
(vvPair
variable "p_logical"
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds\\controlUnit\\struct.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "hds"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "struct"
)
(vvPair
variable "this_file_logical"
value "struct"
)
(vvPair
variable "time"
value "11:25:25"
)
(vvPair
variable "unit"
value "controlUnit"
)
(vvPair
variable "user"
value "axel.amand"
)
(vvPair
variable "version"
value "2019.2 (Build 5)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2022"
)
(vvPair
variable "yy"
value "22"
)
]
)
LanguageMgr "Vhdl2008LangMgr"
uid 310,0
optionalChildren [
*1 (PortIoIn
uid 9,0
shape (CompositeShape
uid 10,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 11,0
sl 0
ro 270
xt "34000,44625,35500,45375"
)
(Line
uid 12,0
sl 0
ro 270
xt "35500,45000,36000,45000"
pts [
"35500,45000"
"36000,45000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 13,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14,0
va (VaSet
)
xt "30800,44400,33000,45600"
st "clk"
ju 2
blo "33000,45400"
tm "WireNameMgr"
)
)
)
*2 (Net
uid 21,0
lang 11
decl (Decl
n "clk"
t "std_ulogic"
o 1
suid 1,0
)
declText (MLText
uid 22,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,2400,35000,3200"
st "clk : std_ulogic
"
)
)
*3 (PortIoIn
uid 23,0
shape (CompositeShape
uid 24,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 25,0
sl 0
ro 270
xt "33000,57625,34500,58375"
)
(Line
uid 26,0
sl 0
ro 270
xt "34500,58000,35000,58000"
pts [
"34500,58000"
"35000,58000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 27,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 28,0
va (VaSet
)
xt "28100,57400,32000,58600"
st "funct3"
ju 2
blo "32000,58400"
tm "WireNameMgr"
)
)
)
*4 (Net
uid 35,0
lang 11
decl (Decl
n "funct3"
t "std_ulogic_vector"
b "(2 DOWNTO 0)"
o 3
suid 2,0
)
declText (MLText
uid 36,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,4000,45000,4800"
st "funct3 : std_ulogic_vector(2 DOWNTO 0)
"
)
)
*5 (PortIoIn
uid 37,0
shape (CompositeShape
uid 38,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 39,0
sl 0
ro 270
xt "33000,59625,34500,60375"
)
(Line
uid 40,0
sl 0
ro 270
xt "34500,60000,35000,60000"
pts [
"34500,60000"
"35000,60000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 41,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 42,0
va (VaSet
)
xt "28100,59400,32000,60600"
st "funct7"
ju 2
blo "32000,60400"
tm "WireNameMgr"
)
)
)
*6 (Net
uid 49,0
lang 11
decl (Decl
n "funct7"
t "std_ulogic"
o 4
suid 3,0
)
declText (MLText
uid 50,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,4800,35000,5600"
st "funct7 : std_ulogic
"
)
)
*7 (PortIoIn
uid 51,0
shape (CompositeShape
uid 52,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 53,0
sl 0
ro 270
xt "27000,33625,28500,34375"
)
(Line
uid 54,0
sl 0
ro 270
xt "28500,34000,29000,34000"
pts [
"28500,34000"
"29000,34000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 55,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 56,0
va (VaSet
)
xt "24100,33400,26000,34600"
st "op"
ju 2
blo "26000,34400"
tm "WireNameMgr"
)
)
)
*8 (Net
uid 63,0
lang 11
decl (Decl
n "op"
t "std_ulogic_vector"
b "(6 DOWNTO 0)"
o 5
suid 4,0
)
declText (MLText
uid 64,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,5600,45000,6400"
st "op : std_ulogic_vector(6 DOWNTO 0)
"
)
)
*9 (PortIoIn
uid 65,0
shape (CompositeShape
uid 66,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 67,0
sl 0
ro 270
xt "34000,46625,35500,47375"
)
(Line
uid 68,0
sl 0
ro 270
xt "35500,47000,36000,47000"
pts [
"35500,47000"
"36000,47000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 69,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 70,0
va (VaSet
)
xt "30900,46400,33000,47600"
st "rst"
ju 2
blo "33000,47400"
tm "WireNameMgr"
)
)
)
*10 (Net
uid 77,0
lang 11
decl (Decl
n "rst"
t "std_ulogic"
o 6
suid 5,0
)
declText (MLText
uid 78,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,6400,35000,7200"
st "rst : std_ulogic
"
)
)
*11 (PortIoIn
uid 79,0
shape (CompositeShape
uid 80,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 81,0
sl 0
ro 270
xt "34000,24625,35500,25375"
)
(Line
uid 82,0
sl 0
ro 270
xt "35500,25000,36000,25000"
pts [
"35500,25000"
"36000,25000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 83,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 84,0
va (VaSet
)
xt "30200,24400,33000,25600"
st "zero"
ju 2
blo "33000,25400"
tm "WireNameMgr"
)
)
)
*12 (Net
uid 91,0
lang 11
decl (Decl
n "zero"
t "std_ulogic"
o 7
suid 6,0
)
declText (MLText
uid 92,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,7200,35000,8000"
st "zero : std_ulogic
"
)
)
*13 (PortIoOut
uid 93,0
shape (CompositeShape
uid 94,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 95,0
sl 0
ro 270
xt "56500,58625,58000,59375"
)
(Line
uid 96,0
sl 0
ro 270
xt "56000,59000,56500,59000"
pts [
"56000,59000"
"56500,59000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 97,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 98,0
va (VaSet
)
xt "59000,58400,66300,59600"
st "ALUControl"
blo "59000,59400"
tm "WireNameMgr"
)
)
)
*14 (Net
uid 105,0
lang 11
decl (Decl
n "ALUControl"
t "std_ulogic_vector"
b "(2 DOWNTO 0)"
o 8
suid 7,0
)
declText (MLText
uid 106,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,8000,45000,8800"
st "ALUControl : std_ulogic_vector(2 DOWNTO 0)
"
)
)
*15 (PortIoOut
uid 107,0
shape (CompositeShape
uid 108,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 109,0
sl 0
ro 270
xt "56500,44625,58000,45375"
)
(Line
uid 110,0
sl 0
ro 270
xt "56000,45000,56500,45000"
pts [
"56000,45000"
"56500,45000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 111,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 112,0
va (VaSet
)
xt "59000,44400,64400,45600"
st "ALUSrcA"
blo "59000,45400"
tm "WireNameMgr"
)
)
)
*16 (Net
uid 119,0
lang 11
decl (Decl
n "ALUSrcA"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 9
suid 8,0
)
declText (MLText
uid 120,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,8800,45000,9600"
st "ALUSrcA : std_ulogic_vector(1 DOWNTO 0)
"
)
)
*17 (PortIoOut
uid 121,0
shape (CompositeShape
uid 122,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 123,0
sl 0
ro 270
xt "56500,42625,58000,43375"
)
(Line
uid 124,0
sl 0
ro 270
xt "56000,43000,56500,43000"
pts [
"56000,43000"
"56500,43000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 125,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 126,0
va (VaSet
)
xt "59000,42400,64300,43600"
st "ALUSrcB"
blo "59000,43400"
tm "WireNameMgr"
)
)
)
*18 (Net
uid 133,0
lang 11
decl (Decl
n "ALUSrcB"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 10
suid 9,0
)
declText (MLText
uid 134,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,9600,45000,10400"
st "ALUSrcB : std_ulogic_vector(1 DOWNTO 0)
"
)
)
*19 (PortIoOut
uid 135,0
shape (CompositeShape
uid 136,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 137,0
sl 0
ro 270
xt "56500,38625,58000,39375"
)
(Line
uid 138,0
sl 0
ro 270
xt "56000,39000,56500,39000"
pts [
"56000,39000"
"56500,39000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 139,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 140,0
va (VaSet
)
xt "59000,38400,63500,39600"
st "IRWrite"
blo "59000,39400"
tm "WireNameMgr"
)
)
)
*20 (Net
uid 147,0
lang 11
decl (Decl
n "IRWrite"
t "std_ulogic"
o 11
suid 10,0
)
declText (MLText
uid 148,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,10400,35000,11200"
st "IRWrite : std_ulogic
"
)
)
*21 (PortIoOut
uid 149,0
shape (CompositeShape
uid 150,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 151,0
sl 0
ro 270
xt "79500,28625,81000,29375"
)
(Line
uid 152,0
sl 0
ro 270
xt "79000,29000,79500,29000"
pts [
"79000,29000"
"79500,29000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 153,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 154,0
va (VaSet
)
xt "82000,28400,86800,29600"
st "PCWrite"
blo "82000,29400"
tm "WireNameMgr"
)
)
)
*22 (Net
uid 161,0
lang 11
decl (Decl
n "PCWrite"
t "std_ulogic"
o 12
suid 11,0
)
declText (MLText
uid 162,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,11200,35000,12000"
st "PCWrite : std_ulogic
"
)
)
*23 (PortIoOut
uid 177,0
shape (CompositeShape
uid 178,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 179,0
sl 0
ro 270
xt "57500,69625,59000,70375"
)
(Line
uid 180,0
sl 0
ro 270
xt "57000,70000,57500,70000"
pts [
"57000,70000"
"57500,70000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 181,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 182,0
va (VaSet
)
xt "60000,69400,64500,70600"
st "immSrc"
blo "60000,70400"
tm "WireNameMgr"
)
)
)
*24 (Net
uid 189,0
lang 11
decl (Decl
n "immSrc"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 14
suid 13,0
)
declText (MLText
uid 190,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,12800,45000,13600"
st "immSrc : std_ulogic_vector(1 DOWNTO 0)
"
)
)
*25 (PortIoOut
uid 191,0
shape (CompositeShape
uid 192,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 193,0
sl 0
ro 270
xt "56500,36625,58000,37375"
)
(Line
uid 194,0
sl 0
ro 270
xt "56000,37000,56500,37000"
pts [
"56000,37000"
"56500,37000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 195,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 196,0
va (VaSet
)
xt "59000,36400,64700,37600"
st "memWrite"
blo "59000,37400"
tm "WireNameMgr"
)
)
)
*26 (Net
uid 203,0
lang 11
decl (Decl
n "memWrite"
t "std_ulogic"
o 15
suid 14,0
)
declText (MLText
uid 204,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,13600,35000,14400"
st "memWrite : std_ulogic
"
)
)
*27 (PortIoOut
uid 205,0
shape (CompositeShape
uid 206,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 207,0
sl 0
ro 270
xt "56500,34625,58000,35375"
)
(Line
uid 208,0
sl 0
ro 270
xt "56000,35000,56500,35000"
pts [
"56000,35000"
"56500,35000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 209,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 210,0
va (VaSet
)
xt "59000,34400,63700,35600"
st "regwrite"
blo "59000,35400"
tm "WireNameMgr"
)
)
)
*28 (Net
uid 217,0
lang 11
decl (Decl
n "regwrite"
t "std_ulogic"
o 16
suid 15,0
)
declText (MLText
uid 218,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,14400,35000,15200"
st "regwrite : std_ulogic
"
)
)
*29 (PortIoOut
uid 219,0
shape (CompositeShape
uid 220,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 221,0
sl 0
ro 270
xt "56500,40625,58000,41375"
)
(Line
uid 222,0
sl 0
ro 270
xt "56000,41000,56500,41000"
pts [
"56000,41000"
"56500,41000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 223,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 224,0
va (VaSet
)
xt "59000,40400,64300,41600"
st "resultSrc"
blo "59000,41400"
tm "WireNameMgr"
)
)
)
*30 (Net
uid 231,0
lang 11
decl (Decl
n "resultSrc"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 17
suid 16,0
)
declText (MLText
uid 232,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,15200,45000,16000"
st "resultSrc : std_ulogic_vector(1 DOWNTO 0)
"
)
)
*31 (Grouping
uid 267,0
optionalChildren [
*32 (CommentText
uid 269,0
shape (Rectangle
uid 270,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,4000,70000,5000"
)
oxt "18000,70000,35000,71000"
text (MLText
uid 271,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "53200,4000,64700,5000"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*33 (CommentText
uid 272,0
shape (Rectangle
uid 273,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "70000,0,74000,1000"
)
oxt "35000,66000,39000,67000"
text (MLText
uid 274,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "70200,0,73200,1000"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*34 (CommentText
uid 275,0
shape (Rectangle
uid 276,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,2000,70000,3000"
)
oxt "18000,68000,35000,69000"
text (MLText
uid 277,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "53200,2000,63200,3000"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*35 (CommentText
uid 278,0
shape (Rectangle
uid 279,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "49000,2000,53000,3000"
)
oxt "14000,68000,18000,69000"
text (MLText
uid 280,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "49200,2000,51300,3000"
st "
Title:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*36 (CommentText
uid 281,0
shape (Rectangle
uid 282,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "70000,1000,90000,5000"
)
oxt "35000,67000,55000,71000"
text (MLText
uid 283,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "70200,1200,79600,2200"
st "
<enter comments here>
"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
titleBlock 1
)
*37 (CommentText
uid 284,0
shape (Rectangle
uid 285,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "74000,0,90000,1000"
)
oxt "39000,66000,55000,67000"
text (MLText
uid 286,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "74200,0,75800,1000"
st "
%project_name
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
titleBlock 1
)
*38 (CommentText
uid 287,0
shape (Rectangle
uid 288,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "49000,0,70000,2000"
)
oxt "14000,66000,35000,68000"
text (MLText
uid 289,0
va (VaSet
fg "32768,0,0"
)
xt "54350,400,64650,1600"
st "
<company name>
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
titleBlock 1
)
*39 (CommentText
uid 290,0
shape (Rectangle
uid 291,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "49000,3000,53000,4000"
)
oxt "14000,69000,18000,70000"
text (MLText
uid 292,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "49200,3000,51300,4000"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*40 (CommentText
uid 293,0
shape (Rectangle
uid 294,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "49000,4000,53000,5000"
)
oxt "14000,70000,18000,71000"
text (MLText
uid 295,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "49200,4000,51900,5000"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*41 (CommentText
uid 296,0
shape (Rectangle
uid 297,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "53000,3000,70000,4000"
)
oxt "18000,69000,35000,70000"
text (MLText
uid 298,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "53200,3000,65300,4000"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
]
shape (GroupingShape
uid 268,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "49000,0,90000,5000"
)
oxt "14000,66000,55000,71000"
)
*42 (PortIoOut
uid 369,0
shape (CompositeShape
uid 370,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 371,0
sl 0
ro 270
xt "56500,46625,58000,47375"
)
(Line
uid 372,0
sl 0
ro 270
xt "56000,47000,56500,47000"
pts [
"56000,47000"
"56500,47000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 373,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 374,0
va (VaSet
)
xt "59000,46500,63000,47700"
st "adrSrc"
blo "59000,47500"
tm "WireNameMgr"
)
)
)
*43 (Net
uid 381,0
decl (Decl
n "adrSrc"
t "std_uLogic"
o 13
suid 17,0
)
declText (MLText
uid 382,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,12000,35000,12800"
st "adrSrc : std_uLogic
"
)
)
*44 (SaComponent
uid 395,0
optionalChildren [
*45 (CptPort
uid 383,0
ps "OnEdgeStrategy"
shape (Triangle
uid 384,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "67585,26625,68335,27375"
)
tg (CPTG
uid 385,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 386,0
va (VaSet
isHidden 1
)
xt "68557,26250,70857,27450"
st "in1"
blo "68557,27250"
)
s (Text
uid 405,0
va (VaSet
isHidden 1
)
xt "68557,27450,68557,27450"
blo "68557,27450"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
suid 1,0
)
)
)
*46 (CptPort
uid 387,0
ps "OnEdgeStrategy"
shape (Triangle
uid 388,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "67584,30625,68334,31375"
)
tg (CPTG
uid 389,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 390,0
va (VaSet
isHidden 1
)
xt "68557,30250,70857,31450"
st "in2"
blo "68557,31250"
)
s (Text
uid 406,0
va (VaSet
isHidden 1
)
xt "68557,31450,68557,31450"
blo "68557,31450"
)
)
thePort (LogicalPort
decl (Decl
n "in2"
t "std_uLogic"
o 2
suid 2,0
)
)
)
*47 (CptPort
uid 391,0
ps "OnEdgeStrategy"
shape (Triangle
uid 392,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "75000,28625,75750,29375"
)
tg (CPTG
uid 393,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 394,0
va (VaSet
isHidden 1
)
xt "71000,28250,74000,29450"
st "out1"
ju 2
blo "74000,29250"
)
s (Text
uid 407,0
va (VaSet
isHidden 1
)
xt "74000,29450,74000,29450"
ju 2
blo "74000,29450"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 3
suid 3,0
)
)
)
]
shape (Or
uid 396,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "68000,26000,75000,32000"
)
showPorts 0
oxt "35000,14000,42000,20000"
ttg (MlTextGroup
uid 397,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*48 (Text
uid 398,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "68600,31700,71700,32700"
st "gates"
blo "68600,32500"
tm "BdLibraryNameMgr"
)
*49 (Text
uid 399,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "68600,32700,70800,33700"
st "or2"
blo "68600,33500"
tm "CptNameMgr"
)
*50 (Text
uid 400,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "68600,32700,71100,33700"
st "U_0"
blo "68600,33500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 401,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 402,0
text (MLText
uid 403,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "68000,34600,82100,35600"
st "delay = gateDelay ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "gateDelay"
)
]
)
viewicon (ZoomableIcon
uid 404,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "68250,30250,69750,31750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
viewiconposition 0
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*51 (SaComponent
uid 420,0
optionalChildren [
*52 (CptPort
uid 408,0
ps "OnEdgeStrategy"
shape (Triangle
uid 409,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "58250,24625,59000,25375"
)
tg (CPTG
uid 410,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 411,0
va (VaSet
isHidden 1
)
xt "59000,24600,68500,25800"
st "in1 : std_uLogic"
blo "59000,25600"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
suid 1,0
)
)
)
*53 (CptPort
uid 412,0
ps "OnEdgeStrategy"
shape (Triangle
uid 413,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "58250,28625,59000,29375"
)
tg (CPTG
uid 414,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 415,0
va (VaSet
isHidden 1
)
xt "59000,28600,68500,29800"
st "in2 : std_uLogic"
blo "59000,29600"
)
)
thePort (LogicalPort
decl (Decl
n "in2"
t "std_uLogic"
o 2
suid 2,0
)
)
)
*54 (CptPort
uid 416,0
ps "OnEdgeStrategy"
shape (Triangle
uid 417,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "65950,26625,66700,27375"
)
tg (CPTG
uid 418,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 419,0
va (VaSet
isHidden 1
)
xt "55800,26550,66000,27750"
st "out1 : std_uLogic"
ju 2
blo "66000,27550"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 3
suid 3,0
)
)
)
]
shape (And
uid 421,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "59000,24000,66000,30000"
)
showPorts 0
oxt "31000,13000,38000,19000"
ttg (MlTextGroup
uid 422,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*55 (Text
uid 423,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "59600,29700,62700,30700"
st "gates"
blo "59600,30500"
tm "BdLibraryNameMgr"
)
*56 (Text
uid 424,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "59600,30700,62500,31700"
st "and2"
blo "59600,31500"
tm "CptNameMgr"
)
*57 (Text
uid 425,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "59600,30700,62100,31700"
st "U_1"
blo "59600,31500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 426,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 427,0
text (MLText
uid 428,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "59000,33600,73100,34600"
st "delay = gateDelay ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "gateDelay"
)
]
)
viewicon (ZoomableIcon
uid 429,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "59250,28250,60750,29750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
viewiconposition 0
portVis (PortSigDisplay
sN 0
sT 1
)
archFileType "UNKNOWN"
)
*58 (Net
uid 430,0
decl (Decl
n "out1"
t "std_uLogic"
o 21
suid 18,0
)
declText (MLText
uid 431,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,19600,38500,20400"
st "SIGNAL out1 : std_uLogic
"
)
)
*59 (Net
uid 444,0
decl (Decl
n "branch"
t "std_uLogic"
o 20
suid 20,0
)
declText (MLText
uid 445,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,18800,38500,19600"
st "SIGNAL branch : std_uLogic
"
)
)
*60 (Net
uid 490,0
decl (Decl
n "PCupdate"
t "std_uLogic"
o 19
suid 23,0
)
declText (MLText
uid 491,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,18000,38500,18800"
st "SIGNAL PCupdate : std_uLogic
"
)
)
*61 (Net
uid 619,0
lang 11
decl (Decl
n "ALUOp"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 18
suid 25,0
)
declText (MLText
uid 620,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,17200,48500,18000"
st "SIGNAL ALUOp : std_ulogic_vector(1 DOWNTO 0)
"
)
)
*62 (SaComponent
uid 955,0
optionalChildren [
*63 (CptPort
uid 947,0
ps "OnEdgeStrategy"
shape (Triangle
uid 948,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "52000,69625,52750,70375"
)
tg (CPTG
uid 949,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 950,0
va (VaSet
font "Verdana,12,0"
)
xt "45800,69300,51000,70700"
st "immSrc"
ju 2
blo "51000,70500"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "immSrc"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 13
suid 1,0
)
)
)
*64 (CptPort
uid 951,0
ps "OnEdgeStrategy"
shape (Triangle
uid 952,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41250,69625,42000,70375"
)
tg (CPTG
uid 953,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 954,0
va (VaSet
font "Verdana,12,0"
)
xt "43000,69300,45400,70700"
st "op"
blo "43000,70500"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "op"
t "std_ulogic_vector"
b "(6 DOWNTO 0)"
o 4
suid 2,0
)
)
)
]
shape (Rectangle
uid 956,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "42000,68000,52000,73000"
)
oxt "20000,16000,30000,21000"
ttg (MlTextGroup
uid 957,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*65 (Text
uid 958,0
va (VaSet
font "Verdana,9,1"
)
xt "42250,73300,49850,74500"
st "HEIRV32_MC"
blo "42250,74300"
tm "BdLibraryNameMgr"
)
*66 (Text
uid 959,0
va (VaSet
font "Verdana,9,1"
)
xt "42250,74500,49750,75700"
st "instrDecoder"
blo "42250,75500"
tm "CptNameMgr"
)
*67 (Text
uid 960,0
va (VaSet
font "Verdana,9,1"
)
xt "42250,75700,51050,76900"
st "U_instrDecoder"
blo "42250,76700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 961,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 962,0
text (MLText
uid 963,0
va (VaSet
font "Courier New,8,0"
)
xt "42000,77200,42000,77200"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 964,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "42250,71250,43750,72750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*68 (PortIoIn
uid 1017,0
shape (CompositeShape
uid 1018,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1019,0
sl 0
ro 270
xt "34000,42625,35500,43375"
)
(Line
uid 1020,0
sl 0
ro 270
xt "35500,43000,36000,43000"
pts [
"35500,43000"
"36000,43000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 1021,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1022,0
va (VaSet
)
xt "31100,42500,33000,43700"
st "en"
ju 2
blo "33000,43500"
tm "WireNameMgr"
)
)
)
*69 (Net
uid 1029,0
lang 11
decl (Decl
n "en"
t "std_ulogic"
o 2
suid 26,0
)
declText (MLText
uid 1030,0
va (VaSet
font "Courier New,8,0"
)
xt "22000,3200,35000,4000"
st "en : std_ulogic
"
)
)
*70 (SaComponent
uid 1230,0
optionalChildren [
*71 (CptPort
uid 1174,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1175,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "52000,46625,52750,47375"
)
tg (CPTG
uid 1176,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1177,0
va (VaSet
font "Verdana,12,0"
)
xt "46200,46300,51000,47700"
st "adrSrc"
ju 2
blo "51000,47500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "adrSrc"
t "std_uLogic"
o 10
suid 1,0
)
)
)
*72 (CptPort
uid 1178,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1179,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43625,50000,44375,50750"
)
tg (CPTG
uid 1180,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1181,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "43300,44000,44700,49000"
st "ALUOp"
blo "44500,49000"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "ALUOp"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 5
suid 2,0
)
)
)
*73 (CptPort
uid 1182,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1183,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "52000,44625,52750,45375"
)
tg (CPTG
uid 1184,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1185,0
va (VaSet
font "Verdana,12,0"
)
xt "45100,44300,51000,45700"
st "ALUSrcA"
ju 2
blo "51000,45500"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "ALUSrcA"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 6
suid 3,0
)
)
)
*74 (CptPort
uid 1186,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1187,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "52000,42625,52750,43375"
)
tg (CPTG
uid 1188,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1189,0
va (VaSet
font "Verdana,12,0"
)
xt "45100,42300,51000,43700"
st "ALUSrcB"
ju 2
blo "51000,43500"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "ALUSrcB"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 7
suid 4,0
)
)
)
*75 (CptPort
uid 1190,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1191,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "52000,30625,52750,31375"
)
tg (CPTG
uid 1192,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1193,0
va (VaSet
font "Verdana,12,0"
)
xt "45900,30300,51000,31700"
st "branch"
ju 2
blo "51000,31500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "branch"
t "std_uLogic"
o 11
suid 5,0
)
)
)
*76 (CptPort
uid 1194,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1195,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "38250,44625,39000,45375"
)
tg (CPTG
uid 1196,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1197,0
va (VaSet
font "Verdana,12,0"
)
xt "40000,44300,42400,45700"
st "clk"
blo "40000,45500"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "clk"
t "std_ulogic"
o 1
suid 6,0
)
)
)
*77 (CptPort
uid 1198,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1199,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "52000,38625,52750,39375"
)
tg (CPTG
uid 1200,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1201,0
va (VaSet
font "Verdana,12,0"
)
xt "45500,38300,51000,39700"
st "IRWrite"
ju 2
blo "51000,39500"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "IRWrite"
t "std_ulogic"
o 8
suid 7,0
)
)
)
*78 (CptPort
uid 1202,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1203,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "52000,36625,52750,37375"
)
tg (CPTG
uid 1204,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1205,0
va (VaSet
font "Verdana,12,0"
)
xt "43800,36300,51000,37700"
st "memWrite"
ju 2
blo "51000,37500"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "memWrite"
t "std_ulogic"
o 12
suid 8,0
)
)
)
*79 (CptPort
uid 1206,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1207,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "38250,33625,39000,34375"
)
tg (CPTG
uid 1208,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1209,0
va (VaSet
font "Verdana,12,0"
)
xt "40000,33300,42400,34700"
st "op"
blo "40000,34500"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "op"
t "std_ulogic_vector"
b "(6 DOWNTO 0)"
o 3
suid 9,0
)
)
)
*80 (CptPort
uid 1210,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1211,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "52000,32625,52750,33375"
)
tg (CPTG
uid 1212,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1213,0
va (VaSet
font "Verdana,12,0"
)
xt "44000,32300,51000,33700"
st "PCupdate"
ju 2
blo "51000,33500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "PCupdate"
t "std_uLogic"
o 9
suid 10,0
)
)
)
*81 (CptPort
uid 1214,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1215,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "52000,34625,52750,35375"
)
tg (CPTG
uid 1216,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1217,0
va (VaSet
font "Verdana,12,0"
)
xt "44900,34300,51000,35700"
st "regwrite"
ju 2
blo "51000,35500"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "regwrite"
t "std_ulogic"
o 13
suid 11,0
)
)
)
*82 (CptPort
uid 1218,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1219,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "52000,40625,52750,41375"
)
tg (CPTG
uid 1220,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1221,0
va (VaSet
font "Verdana,12,0"
)
xt "44700,40300,51000,41700"
st "resultSrc"
ju 2
blo "51000,41500"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "resultSrc"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 14
suid 12,0
)
)
)
*83 (CptPort
uid 1222,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1223,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "38250,46625,39000,47375"
)
tg (CPTG
uid 1224,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1225,0
va (VaSet
font "Verdana,12,0"
)
xt "40000,46300,42500,47700"
st "rst"
blo "40000,47500"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "rst"
t "std_ulogic"
o 4
suid 13,0
)
)
)
*84 (CptPort
uid 1226,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1227,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "38250,42625,39000,43375"
)
tg (CPTG
uid 1228,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1229,0
va (VaSet
font "Verdana,12,0"
)
xt "40000,42300,42400,43700"
st "en"
blo "40000,43500"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "en"
t "std_ulogic"
o 2
suid 14,0
)
)
)
]
shape (Rectangle
uid 1231,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "39000,30000,52000,50000"
)
oxt "12000,6000,25000,26000"
ttg (MlTextGroup
uid 1232,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*85 (Text
uid 1233,0
va (VaSet
font "Verdana,9,1"
)
xt "39500,25800,47100,27000"
st "HEIRV32_MC"
blo "39500,26800"
tm "BdLibraryNameMgr"
)
*86 (Text
uid 1234,0
va (VaSet
font "Verdana,9,1"
)
xt "39500,27000,44500,28200"
st "mainFSM"
blo "39500,28000"
tm "CptNameMgr"
)
*87 (Text
uid 1235,0
va (VaSet
font "Verdana,9,1"
)
xt "39500,28200,45800,29400"
st "U_mainFSM"
blo "39500,29200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1236,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1237,0
text (MLText
uid 1238,0
va (VaSet
font "Courier New,8,0"
)
xt "41000,29000,41000,29000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 1239,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "39250,48250,40750,49750"
iconName "StateMachineViewIcon.png"
iconMaskName "StateMachineViewIcon.msk"
ftype 3
)
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*88 (SaComponent
uid 1415,0
optionalChildren [
*89 (CptPort
uid 1395,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1396,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "53000,58625,53750,59375"
)
tg (CPTG
uid 1397,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1398,0
va (VaSet
font "Verdana,12,0"
)
xt "43400,58300,52000,59700"
st "ALUControl"
ju 2
blo "52000,59500"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "ALUControl"
t "std_ulogic_vector"
b "(2 DOWNTO 0)"
o 7
suid 1,0
)
)
)
*90 (CptPort
uid 1399,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1400,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43625,53250,44375,54000"
)
tg (CPTG
uid 1401,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1402,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "43300,55000,44700,60000"
st "ALUOp"
ju 2
blo "44500,55000"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "ALUOp"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 20
suid 2,0
)
)
)
*91 (CptPort
uid 1403,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1404,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,57625,37000,58375"
)
tg (CPTG
uid 1405,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1406,0
va (VaSet
font "Verdana,12,0"
)
xt "38000,57300,42700,58700"
st "funct3"
blo "38000,58500"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "funct3"
t "std_ulogic_vector"
b "(2 DOWNTO 0)"
o 2
suid 3,0
)
)
)
*92 (CptPort
uid 1407,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1408,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,59625,37000,60375"
)
tg (CPTG
uid 1409,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1410,0
va (VaSet
font "Verdana,12,0"
)
xt "38000,59300,42700,60700"
st "funct7"
blo "38000,60500"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "funct7"
t "std_ulogic"
o 3
suid 4,0
)
)
)
*93 (CptPort
uid 1411,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1412,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "36250,55625,37000,56375"
)
tg (CPTG
uid 1413,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1414,0
va (VaSet
font "Verdana,12,0"
)
xt "38000,55300,40400,56700"
st "op"
blo "38000,56500"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "op"
t "std_ulogic"
o 4
suid 5,0
)
)
)
]
shape (Rectangle
uid 1416,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "37000,54000,53000,63000"
)
oxt "20000,12000,36000,21000"
ttg (MlTextGroup
uid 1417,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*94 (Text
uid 1418,0
va (VaSet
font "Verdana,9,1"
)
xt "53650,60800,58650,62000"
st "HEIRV32"
blo "53650,61800"
tm "BdLibraryNameMgr"
)
*95 (Text
uid 1419,0
va (VaSet
font "Verdana,9,1"
)
xt "53650,62000,60350,63200"
st "aluDecoder"
blo "53650,63000"
tm "CptNameMgr"
)
*96 (Text
uid 1420,0
va (VaSet
font "Verdana,9,1"
)
xt "53650,63200,61650,64400"
st "U_aluDecoder"
blo "53650,64200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1421,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1422,0
text (MLText
uid 1423,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "54000,64200,69500,65000"
st "g_tDec = 25 ps ( time )
"
)
header ""
)
elements [
(GiElement
name "g_tDec"
type "time"
value "25 ps"
)
]
)
viewicon (ZoomableIcon
uid 1424,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "37250,61250,38750,62750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*97 (Wire
uid 15,0
shape (OrthoPolyLine
uid 16,0
va (VaSet
vasetType 3
)
xt "36000,45000,38250,45000"
pts [
"36000,45000"
"38250,45000"
]
)
start &1
end &76
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 19,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20,0
va (VaSet
isHidden 1
)
xt "37000,43800,39200,45000"
st "clk"
blo "37000,44800"
tm "WireNameMgr"
)
)
on &2
)
*98 (Wire
uid 29,0
shape (OrthoPolyLine
uid 30,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "35000,58000,36250,58000"
pts [
"35000,58000"
"36250,58000"
]
)
start &3
end &91
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 33,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 34,0
va (VaSet
isHidden 1
)
xt "30000,56800,38200,58000"
st "funct3 : (2:0)"
blo "30000,57800"
tm "WireNameMgr"
)
)
on &4
)
*99 (Wire
uid 43,0
shape (OrthoPolyLine
uid 44,0
va (VaSet
vasetType 3
)
xt "35000,60000,36250,60000"
pts [
"35000,60000"
"36250,60000"
]
)
start &5
end &92
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 47,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 48,0
va (VaSet
isHidden 1
)
xt "35000,58800,38900,60000"
st "funct7"
blo "35000,59800"
tm "WireNameMgr"
)
)
on &6
)
*100 (Wire
uid 57,0
optionalChildren [
*101 (Ripper
uid 488,0
ps "OnConnectorStrategy"
shape (Line2D
pts [
"31000,34000"
"30000,35000"
]
uid 489,0
va (VaSet
vasetType 3
)
xt "30000,34000,31000,35000"
)
)
]
shape (OrthoPolyLine
uid 58,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "29000,34000,38250,34000"
pts [
"29000,34000"
"38250,34000"
]
)
start &7
end &79
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 61,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 62,0
va (VaSet
isHidden 1
)
xt "30000,32800,36200,34000"
st "op : (6:0)"
blo "30000,33800"
tm "WireNameMgr"
)
)
on &8
)
*102 (Wire
uid 71,0
shape (OrthoPolyLine
uid 72,0
va (VaSet
vasetType 3
)
xt "36000,47000,38250,47000"
pts [
"36000,47000"
"38250,47000"
]
)
start &9
end &83
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 75,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 76,0
va (VaSet
isHidden 1
)
xt "37000,45800,39100,47000"
st "rst"
blo "37000,46800"
tm "WireNameMgr"
)
)
on &10
)
*103 (Wire
uid 85,0
shape (OrthoPolyLine
uid 86,0
va (VaSet
vasetType 3
)
xt "36000,25000,59000,25000"
pts [
"36000,25000"
"59000,25000"
]
)
start &11
end &52
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 89,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 90,0
va (VaSet
isHidden 1
)
xt "38000,23800,40800,25000"
st "zero"
blo "38000,24800"
tm "WireNameMgr"
)
)
on &12
)
*104 (Wire
uid 99,0
shape (OrthoPolyLine
uid 100,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "53750,59000,56000,59000"
pts [
"56000,59000"
"53750,59000"
]
)
start &13
end &89
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 103,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 104,0
va (VaSet
isHidden 1
)
xt "54000,57800,64900,59000"
st "ALUControl : (2:0)"
blo "54000,58800"
tm "WireNameMgr"
)
)
on &14
)
*105 (Wire
uid 113,0
shape (OrthoPolyLine
uid 114,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "52750,45000,56000,45000"
pts [
"56000,45000"
"52750,45000"
]
)
start &15
end &73
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 117,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 118,0
va (VaSet
isHidden 1
)
xt "52000,43800,61700,45000"
st "ALUSrcA : (1:0)"
blo "52000,44800"
tm "WireNameMgr"
)
)
on &16
)
*106 (Wire
uid 127,0
shape (OrthoPolyLine
uid 128,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "52750,43000,56000,43000"
pts [
"56000,43000"
"52750,43000"
]
)
start &17
end &74
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 131,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 132,0
va (VaSet
isHidden 1
)
xt "52000,41800,61600,43000"
st "ALUSrcB : (1:0)"
blo "52000,42800"
tm "WireNameMgr"
)
)
on &18
)
*107 (Wire
uid 141,0
shape (OrthoPolyLine
uid 142,0
va (VaSet
vasetType 3
)
xt "52750,39000,56000,39000"
pts [
"56000,39000"
"52750,39000"
]
)
start &19
end &77
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 145,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 146,0
va (VaSet
isHidden 1
)
xt "50000,37800,54500,39000"
st "IRWrite"
blo "50000,38800"
tm "WireNameMgr"
)
)
on &20
)
*108 (Wire
uid 155,0
shape (OrthoPolyLine
uid 156,0
va (VaSet
vasetType 3
)
xt "75000,29000,79000,29000"
pts [
"79000,29000"
"75000,29000"
]
)
start &21
end &47
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 159,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 160,0
va (VaSet
isHidden 1
)
xt "78000,27800,82800,29000"
st "PCWrite"
blo "78000,28800"
tm "WireNameMgr"
)
)
on &22
)
*109 (Wire
uid 183,0
shape (OrthoPolyLine
uid 184,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "52750,70000,57000,70000"
pts [
"57000,70000"
"52750,70000"
]
)
start &23
end &63
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 187,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 188,0
va (VaSet
isHidden 1
)
xt "56000,68800,64800,70000"
st "immSrc : (1:0)"
blo "56000,69800"
tm "WireNameMgr"
)
)
on &24
)
*110 (Wire
uid 197,0
shape (OrthoPolyLine
uid 198,0
va (VaSet
vasetType 3
)
xt "52750,37000,56000,37000"
pts [
"56000,37000"
"52750,37000"
]
)
start &25
end &78
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 201,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 202,0
va (VaSet
isHidden 1
)
xt "50000,35800,55700,37000"
st "memWrite"
blo "50000,36800"
tm "WireNameMgr"
)
)
on &26
)
*111 (Wire
uid 211,0
shape (OrthoPolyLine
uid 212,0
va (VaSet
vasetType 3
)
xt "52750,35000,56000,35000"
pts [
"56000,35000"
"52750,35000"
]
)
start &27
end &81
ss 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 215,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 216,0
va (VaSet
isHidden 1
)
xt "50000,33800,54700,35000"
st "regwrite"
blo "50000,34800"
tm "WireNameMgr"
)
)
on &28
)
*112 (Wire
uid 225,0
shape (OrthoPolyLine
uid 226,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "52750,41000,56000,41000"
pts [
"56000,41000"
"52750,41000"
]
)
start &29
end &82
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 229,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 230,0
va (VaSet
isHidden 1
)
xt "52000,39800,61600,41000"
st "resultSrc : (1:0)"
blo "52000,40800"
tm "WireNameMgr"
)
)
on &30
)
*113 (Wire
uid 375,0
shape (OrthoPolyLine
uid 376,0
va (VaSet
vasetType 3
)
xt "52750,47000,56000,47000"
pts [
"52750,47000"
"56000,47000"
]
)
start &71
end &42
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 379,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 380,0
va (VaSet
isHidden 1
)
xt "51000,45800,55000,47000"
st "adrSrc"
blo "51000,46800"
tm "WireNameMgr"
)
)
on &43
)
*114 (Wire
uid 432,0
shape (OrthoPolyLine
uid 433,0
va (VaSet
vasetType 3
)
xt "65950,27000,68335,27000"
pts [
"65950,27000"
"68335,27000"
]
)
start &54
end &45
sat 32
eat 32
sf 1
si 0
tg (WTG
uid 434,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 435,0
va (VaSet
isHidden 1
)
xt "65950,25800,76150,27000"
st "out1 : std_uLogic"
blo "65950,26800"
tm "WireNameMgr"
)
)
on &58
)
*115 (Wire
uid 438,0
shape (OrthoPolyLine
uid 439,0
va (VaSet
vasetType 3
)
xt "52750,29000,59000,31000"
pts [
"59000,29000"
"55000,29000"
"55000,31000"
"52750,31000"
]
)
start &53
end &75
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 442,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 443,0
va (VaSet
)
xt "55000,27800,59100,29000"
st "branch"
blo "55000,28800"
tm "WireNameMgr"
)
)
on &59
)
*116 (Wire
uid 448,0
shape (OrthoPolyLine
uid 449,0
va (VaSet
vasetType 3
)
xt "52750,31000,68334,33000"
pts [
"68334,31000"
"56000,31000"
"56000,33000"
"52750,33000"
]
)
start &46
end &80
sat 32
eat 32
stc 0
sf 1
si 0
tg (WTG
uid 452,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 453,0
va (VaSet
)
xt "63000,29800,68600,31000"
st "PCupdate"
blo "63000,30800"
tm "WireNameMgr"
)
s (Text
uid 549,0
va (VaSet
isHidden 1
)
xt "63000,31000,63000,31000"
blo "63000,31000"
tm "SignalTypeMgr"
)
)
on &60
)
*117 (Wire
uid 482,0
shape (OrthoPolyLine
uid 483,0
va (VaSet
vasetType 3
)
xt "30000,35000,36250,56000"
pts [
"30000,35000"
"30000,56000"
"36250,56000"
]
)
start &101
end &93
sat 32
eat 32
sl "(5)"
stc 0
st 0
sf 1
si 0
tg (WTG
uid 486,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 487,0
va (VaSet
)
xt "32000,54800,35400,56000"
st "op(5)"
blo "32000,55800"
tm "WireNameMgr"
)
)
on &8
)
*118 (Wire
uid 611,0
shape (OrthoPolyLine
uid 612,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "44000,50750,44000,53250"
pts [
"44000,50750"
"44000,53250"
]
)
start &72
end &90
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 617,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 618,0
va (VaSet
)
xt "45000,51800,49400,53000"
st "ALUOp"
blo "45000,52800"
tm "WireNameMgr"
)
)
on &61
)
*119 (Wire
uid 633,0
shape (OrthoPolyLine
uid 634,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "38000,70000,41250,70000"
pts [
"38000,70000"
"41250,70000"
]
)
end &64
sat 16
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 639,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 640,0
va (VaSet
)
xt "39000,68800,40900,70000"
st "op"
blo "39000,69800"
tm "WireNameMgr"
)
)
on &8
)
*120 (Wire
uid 1023,0
shape (OrthoPolyLine
uid 1024,0
va (VaSet
vasetType 3
)
xt "36000,43000,38250,43000"
pts [
"36000,43000"
"38250,43000"
]
)
start &68
end &84
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1027,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1028,0
va (VaSet
isHidden 1
)
xt "38000,41800,39900,43000"
st "en"
blo "38000,42800"
tm "WireNameMgr"
)
)
on &69
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 0
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *121 (PackageList
uid 299,0
stg "VerticalLayoutStrategy"
textVec [
*122 (Text
uid 300,0
va (VaSet
font "Verdana,9,1"
)
xt "-6000,800,1600,2000"
st "Package List"
blo "-6000,1800"
)
*123 (MLText
uid 301,0
va (VaSet
)
xt "-6000,2000,11500,8000"
st "LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY gates;
USE gates.gates.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 302,0
stg "VerticalLayoutStrategy"
textVec [
*124 (Text
uid 303,0
va (VaSet
isHidden 1
font "Verdana,9,1"
)
xt "20000,0,30800,1200"
st "Compiler Directives"
blo "20000,1000"
)
*125 (Text
uid 304,0
va (VaSet
isHidden 1
font "Verdana,9,1"
)
xt "20000,1200,33100,2400"
st "Pre-module directives:"
blo "20000,2200"
)
*126 (MLText
uid 305,0
va (VaSet
isHidden 1
)
xt "20000,2400,32100,4800"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*127 (Text
uid 306,0
va (VaSet
isHidden 1
font "Verdana,9,1"
)
xt "20000,4800,33700,6000"
st "Post-module directives:"
blo "20000,5800"
)
*128 (MLText
uid 307,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*129 (Text
uid 308,0
va (VaSet
isHidden 1
font "Verdana,9,1"
)
xt "20000,6000,33200,7200"
st "End-module directives:"
blo "20000,7000"
)
*130 (MLText
uid 309,0
va (VaSet
isHidden 1
)
xt "20000,7200,20000,7200"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "0,0,1921,1056"
viewArea "-7400,-1500,139891,76800"
cachedDiagramExtent "-6000,0,90000,76900"
pageSetupInfo (PageSetupInfo
ptrCmd ""
toPrinter 1
xMargin 49
yMargin 49
paperWidth 761
paperHeight 1077
windowsPaperWidth 761
windowsPaperHeight 1077
paperType "A4 (210 x 297 mm)"
windowsPaperName "A4 (210 x 297 mm)"
windowsPaperType 9
useAdjustTo 0
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
exportStdIncludeRefs 1
exportStdPackageRefs 1
)
hasePageBreakOrigin 1
pageBreakOrigin "-7000,0"
lastUid 1424,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,3200,1400"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "arial,8,0"
)
xt "500,2150,1400,3150"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Verdana,9,1"
)
xt "1000,1000,5000,2200"
st "Panel0"
blo "1000,2000"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*131 (Text
va (VaSet
font "Verdana,9,1"
)
xt "1300,3200,6700,4400"
st "<library>"
blo "1300,4200"
tm "BdLibraryNameMgr"
)
*132 (Text
va (VaSet
font "Verdana,9,1"
)
xt "1300,4400,6100,5600"
st "<block>"
blo "1300,5400"
tm "BlkNameMgr"
)
*133 (Text
va (VaSet
font "Verdana,9,1"
)
xt "1300,5600,3800,6800"
st "U_0"
blo "1300,6600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "1300,13200,1300,13200"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-850,0,8850,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*134 (Text
va (VaSet
font "Verdana,9,1"
)
xt "-350,3200,3750,4400"
st "Library"
blo "-350,4200"
)
*135 (Text
va (VaSet
font "Verdana,9,1"
)
xt "-350,4400,8350,5600"
st "MWComponent"
blo "-350,5400"
)
*136 (Text
va (VaSet
font "Verdana,9,1"
)
xt "-350,5600,2150,6800"
st "U_0"
blo "-350,6600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-7350,1200,-7350,1200"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*137 (Text
va (VaSet
font "Verdana,9,1"
)
xt "0,3200,4100,4400"
st "Library"
blo "0,4200"
tm "BdLibraryNameMgr"
)
*138 (Text
va (VaSet
font "Verdana,9,1"
)
xt "0,4400,8000,5600"
st "SaComponent"
blo "0,5400"
tm "CptNameMgr"
)
*139 (Text
va (VaSet
font "Verdana,9,1"
)
xt "0,5600,2500,6800"
st "U_0"
blo "0,6600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-7000,1200,-7000,1200"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-1000,0,9000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*140 (Text
va (VaSet
font "Verdana,9,1"
)
xt "-500,3200,3600,4400"
st "Library"
blo "-500,4200"
)
*141 (Text
va (VaSet
font "Verdana,9,1"
)
xt "-500,4400,8500,5600"
st "VhdlComponent"
blo "-500,5400"
)
*142 (Text
va (VaSet
font "Verdana,9,1"
)
xt "-500,5600,2000,6800"
st "U_0"
blo "-500,6600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-7500,1200,-7500,1200"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-1650,0,9650,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*143 (Text
va (VaSet
font "Verdana,9,1"
)
xt "-1150,3200,2950,4400"
st "Library"
blo "-1150,4200"
)
*144 (Text
va (VaSet
font "Verdana,9,1"
)
xt "-1150,4400,9150,5600"
st "VerilogComponent"
blo "-1150,5400"
)
*145 (Text
va (VaSet
font "Verdana,9,1"
)
xt "-1150,5600,1350,6800"
st "U_0"
blo "-1150,6600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-8150,1200,-8150,1200"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*146 (Text
va (VaSet
font "Verdana,9,1"
)
xt "2800,3800,5200,5000"
st "eb1"
blo "2800,4800"
tm "HdlTextNameMgr"
)
*147 (Text
va (VaSet
font "Verdana,9,1"
)
xt "2800,5000,4000,6200"
st "1"
blo "2800,6000"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,3200,1400"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
font "Verdana,9,1"
)
xt "-650,-600,650,600"
st "G"
blo "-650,400"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,2900,1200"
st "sig0"
blo "0,1000"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,3800,1200"
st "dbus0"
blo "0,1000"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineColor "32768,0,0"
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,4700,1200"
st "bundle0"
blo "0,1000"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1200,1500,2400"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
)
second (MLText
va (VaSet
)
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1300,18500,-100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1850,1650"
)
num (Text
va (VaSet
)
xt "250,250,1650,1450"
st "1"
blo "250,1250"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*148 (Text
va (VaSet
font "Verdana,9,1"
)
xt "11200,20000,22000,21200"
st "Frame Declarations"
blo "11200,21000"
)
*149 (MLText
va (VaSet
)
xt "11200,21200,11200,21200"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1300,11000,-100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1850,1650"
)
num (Text
va (VaSet
)
xt "250,250,1650,1450"
st "1"
blo "250,1250"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*150 (Text
va (VaSet
font "Verdana,9,1"
)
xt "11200,20000,22000,21200"
st "Frame Declarations"
blo "11200,21000"
)
*151 (MLText
va (VaSet
)
xt "11200,21200,11200,21200"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,2800,1950"
st "Port"
blo "0,1750"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,2800,1950"
st "Port"
blo "0,1750"
)
)
thePort (LogicalPort
lang 11
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Courier New,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Verdana,9,1"
)
xt "20000,0,27400,1200"
st "Declarations"
blo "20000,1000"
)
portLabel (Text
uid 3,0
va (VaSet
font "Verdana,9,1"
)
xt "20000,1200,23700,2400"
st "Ports:"
blo "20000,2200"
)
preUserLabel (Text
uid 4,0
va (VaSet
isHidden 1
font "Verdana,9,1"
)
xt "20000,0,25200,1200"
st "Pre User:"
blo "20000,1000"
)
preUserText (MLText
uid 5,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "20000,0,20000,0"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Verdana,9,1"
)
xt "20000,16000,29500,17200"
st "Diagram Signals:"
blo "20000,17000"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Verdana,9,1"
)
xt "20000,0,26400,1200"
st "Post User:"
blo "20000,1000"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "20000,0,20000,0"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 26,0
usingSuid 1
emptyRow *152 (LEmptyRow
)
uid 312,0
optionalChildren [
*153 (RefLabelRowHdr
)
*154 (TitleRowHdr
)
*155 (FilterRowHdr
)
*156 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*157 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*158 (GroupColHdr
tm "GroupColHdrMgr"
)
*159 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*160 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*161 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*162 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*163 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*164 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*165 (LeafLogPort
port (LogicalPort
lang 11
m 1
decl (Decl
n "PCWrite"
t "std_ulogic"
o 12
suid 11,0
)
)
uid 233,0
)
*166 (LeafLogPort
port (LogicalPort
lang 11
m 1
decl (Decl
n "memWrite"
t "std_ulogic"
o 15
suid 14,0
)
)
uid 237,0
)
*167 (LeafLogPort
port (LogicalPort
lang 11
m 1
decl (Decl
n "IRWrite"
t "std_ulogic"
o 11
suid 10,0
)
)
uid 239,0
)
*168 (LeafLogPort
port (LogicalPort
lang 11
decl (Decl
n "op"
t "std_ulogic_vector"
b "(6 DOWNTO 0)"
o 5
suid 4,0
)
)
uid 241,0
)
*169 (LeafLogPort
port (LogicalPort
lang 11
decl (Decl
n "funct3"
t "std_ulogic_vector"
b "(2 DOWNTO 0)"
o 3
suid 2,0
)
)
uid 243,0
)
*170 (LeafLogPort
port (LogicalPort
lang 11
decl (Decl
n "funct7"
t "std_ulogic"
o 4
suid 3,0
)
)
uid 245,0
)
*171 (LeafLogPort
port (LogicalPort
lang 11
decl (Decl
n "zero"
t "std_ulogic"
o 7
suid 6,0
)
)
uid 247,0
)
*172 (LeafLogPort
port (LogicalPort
lang 11
decl (Decl
n "clk"
t "std_ulogic"
o 1
suid 1,0
)
)
uid 249,0
)
*173 (LeafLogPort
port (LogicalPort
lang 11
m 1
decl (Decl
n "resultSrc"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 17
suid 16,0
)
)
uid 251,0
)
*174 (LeafLogPort
port (LogicalPort
lang 11
m 1
decl (Decl
n "ALUControl"
t "std_ulogic_vector"
b "(2 DOWNTO 0)"
o 8
suid 7,0
)
)
uid 253,0
)
*175 (LeafLogPort
port (LogicalPort
lang 11
decl (Decl
n "rst"
t "std_ulogic"
o 6
suid 5,0
)
)
uid 255,0
)
*176 (LeafLogPort
port (LogicalPort
lang 11
m 1
decl (Decl
n "ALUSrcB"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 10
suid 9,0
)
)
uid 257,0
)
*177 (LeafLogPort
port (LogicalPort
lang 11
m 1
decl (Decl
n "ALUSrcA"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 9
suid 8,0
)
)
uid 259,0
)
*178 (LeafLogPort
port (LogicalPort
lang 11
m 1
decl (Decl
n "immSrc"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 14
suid 13,0
)
)
uid 261,0
)
*179 (LeafLogPort
port (LogicalPort
lang 11
m 1
decl (Decl
n "regwrite"
t "std_ulogic"
o 16
suid 15,0
)
)
uid 263,0
)
*180 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "adrSrc"
t "std_uLogic"
o 13
suid 17,0
)
)
uid 368,0
)
*181 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "out1"
t "std_uLogic"
o 21
suid 18,0
)
)
uid 476,0
)
*182 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "branch"
t "std_uLogic"
o 20
suid 20,0
)
)
uid 478,0
)
*183 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "PCupdate"
t "std_uLogic"
o 19
suid 23,0
)
)
uid 492,0
)
*184 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "ALUOp"
t "std_ulogic_vector"
b "(1 DOWNTO 0)"
o 18
suid 25,0
)
)
uid 621,0
)
*185 (LeafLogPort
port (LogicalPort
lang 11
decl (Decl
n "en"
t "std_ulogic"
o 2
suid 26,0
)
)
uid 1016,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 325,0
optionalChildren [
*186 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *187 (MRCItem
litem &152
pos 21
dimension 20
)
uid 327,0
optionalChildren [
*188 (MRCItem
litem &153
pos 0
dimension 20
uid 328,0
)
*189 (MRCItem
litem &154
pos 1
dimension 23
uid 329,0
)
*190 (MRCItem
litem &155
pos 2
hidden 1
dimension 20
uid 330,0
)
*191 (MRCItem
litem &165
pos 8
dimension 20
uid 234,0
)
*192 (MRCItem
litem &166
pos 7
dimension 20
uid 238,0
)
*193 (MRCItem
litem &167
pos 6
dimension 20
uid 240,0
)
*194 (MRCItem
litem &168
pos 5
dimension 20
uid 242,0
)
*195 (MRCItem
litem &169
pos 12
dimension 20
uid 244,0
)
*196 (MRCItem
litem &170
pos 13
dimension 20
uid 246,0
)
*197 (MRCItem
litem &171
pos 11
dimension 20
uid 248,0
)
*198 (MRCItem
litem &172
pos 14
dimension 20
uid 250,0
)
*199 (MRCItem
litem &173
pos 10
dimension 20
uid 252,0
)
*200 (MRCItem
litem &174
pos 1
dimension 20
uid 254,0
)
*201 (MRCItem
litem &175
pos 15
dimension 20
uid 256,0
)
*202 (MRCItem
litem &176
pos 3
dimension 20
uid 258,0
)
*203 (MRCItem
litem &177
pos 2
dimension 20
uid 260,0
)
*204 (MRCItem
litem &178
pos 4
dimension 20
uid 262,0
)
*205 (MRCItem
litem &179
pos 9
dimension 20
uid 264,0
)
*206 (MRCItem
litem &180
pos 0
dimension 20
uid 367,0
)
*207 (MRCItem
litem &181
pos 17
dimension 20
uid 477,0
)
*208 (MRCItem
litem &182
pos 18
dimension 20
uid 479,0
)
*209 (MRCItem
litem &183
pos 19
dimension 20
uid 493,0
)
*210 (MRCItem
litem &184
pos 20
dimension 20
uid 622,0
)
*211 (MRCItem
litem &185
pos 16
dimension 20
uid 1015,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 331,0
optionalChildren [
*212 (MRCItem
litem &156
pos 0
dimension 20
uid 332,0
)
*213 (MRCItem
litem &158
pos 1
dimension 50
uid 333,0
)
*214 (MRCItem
litem &159
pos 2
dimension 100
uid 334,0
)
*215 (MRCItem
litem &160
pos 3
dimension 50
uid 335,0
)
*216 (MRCItem
litem &161
pos 4
dimension 100
uid 336,0
)
*217 (MRCItem
litem &162
pos 5
dimension 100
uid 337,0
)
*218 (MRCItem
litem &163
pos 6
dimension 50
uid 338,0
)
*219 (MRCItem
litem &164
pos 7
dimension 80
uid 339,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 326,0
vaOverrides [
]
)
]
)
uid 311,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *220 (LEmptyRow
)
uid 341,0
optionalChildren [
*221 (RefLabelRowHdr
)
*222 (TitleRowHdr
)
*223 (FilterRowHdr
)
*224 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*225 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*226 (GroupColHdr
tm "GroupColHdrMgr"
)
*227 (NameColHdr
tm "GenericNameColHdrMgr"
)
*228 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*229 (InitColHdr
tm "GenericValueColHdrMgr"
)
*230 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*231 (EolColHdr
tm "GenericEolColHdrMgr"
)
*232 (LogGeneric
generic (GiElement
name "g_datawidth"
type "positive"
value "32"
)
uid 265,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 353,0
optionalChildren [
*233 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *234 (MRCItem
litem &220
pos 1
dimension 20
)
uid 355,0
optionalChildren [
*235 (MRCItem
litem &221
pos 0
dimension 20
uid 356,0
)
*236 (MRCItem
litem &222
pos 1
dimension 23
uid 357,0
)
*237 (MRCItem
litem &223
pos 2
hidden 1
dimension 20
uid 358,0
)
*238 (MRCItem
litem &232
pos 0
dimension 20
uid 266,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 359,0
optionalChildren [
*239 (MRCItem
litem &224
pos 0
dimension 20
uid 360,0
)
*240 (MRCItem
litem &226
pos 1
dimension 50
uid 361,0
)
*241 (MRCItem
litem &227
pos 2
dimension 100
uid 362,0
)
*242 (MRCItem
litem &228
pos 3
dimension 100
uid 363,0
)
*243 (MRCItem
litem &229
pos 4
dimension 50
uid 364,0
)
*244 (MRCItem
litem &230
pos 5
dimension 50
uid 365,0
)
*245 (MRCItem
litem &231
pos 6
dimension 80
uid 366,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 354,0
vaOverrides [
]
)
]
)
uid 340,0
type 1
)
activeModelName "BlockDiag"
)
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