5466 lines
64 KiB
Plaintext
5466 lines
64 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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instances [
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(Instance
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name "I_rx"
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duLibraryName "RS232"
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duName "serialPortReceiver"
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elements [
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(GiElement
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name "dataBitNb"
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type "positive"
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value "dataBitNb"
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)
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(GiElement
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name "baudRateDivide"
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type "positive"
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value "baudRateDivide"
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)
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]
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mwi 0
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uid 1663,0
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)
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(Instance
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name "I_tx"
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duLibraryName "RS232"
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duName "serialPortTransmitter"
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elements [
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(GiElement
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name "dataBitNb"
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type "positive"
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value "dataBitNb"
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)
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(GiElement
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name "baudRateDivide"
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type "positive"
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value "baudRateDivide"
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)
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]
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mwi 0
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uid 1696,0
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)
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(Instance
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name "I_rxFifo"
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duLibraryName "memory"
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duName "FIFO"
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elements [
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(GiElement
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name "dataBitNb"
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type "positive"
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value "dataBitNb"
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)
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(GiElement
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name "depth"
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type "positive"
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value "rxFifoDepth"
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)
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]
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mwi 0
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uid 1778,0
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)
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(Instance
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name "I_txFifo"
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duLibraryName "memory"
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duName "FIFO"
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elements [
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(GiElement
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name "dataBitNb"
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type "positive"
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value "dataBitNb"
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)
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(GiElement
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name "depth"
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type "positive"
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value "txFifoDepth"
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)
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]
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mwi 0
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uid 1819,0
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)
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]
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embeddedInstances [
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(EmbeddedInstance
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name "eb1"
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number "1"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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model (BlockDiag
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VExpander (VariableExpander
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vvMap [
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(vvPair
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variable " "
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value " "
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)
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(vvPair
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variable "HDLDir"
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value "C:\\dev\\did-inverter\\Libs\\RS232\\hdl"
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)
|
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(vvPair
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|
variable "HDSDir"
|
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value "C:\\dev\\did-inverter\\Libs\\RS232\\hds"
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|
)
|
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(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\dev\\did-inverter\\Libs\\RS232\\hds\\serial@port@f@i@f@o\\struct.bd.info"
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)
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(vvPair
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variable "SideDataUserDir"
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value "C:\\dev\\did-inverter\\Libs\\RS232\\hds\\serial@port@f@i@f@o\\struct.bd.user"
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)
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(vvPair
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variable "SourceDir"
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value "C:\\dev\\did-inverter\\Libs\\RS232\\hds"
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)
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(vvPair
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variable "appl"
|
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value "HDL Designer"
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)
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(vvPair
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variable "arch_name"
|
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value "struct"
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)
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(vvPair
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variable "concat_file"
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value "concatenated"
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)
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(vvPair
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variable "config"
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value "%(unit)_%(view)_config"
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)
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(vvPair
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variable "d"
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value "C:\\dev\\did-inverter\\Libs\\RS232\\hds\\serial@port@f@i@f@o"
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)
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(vvPair
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variable "d_logical"
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value "C:\\dev\\did-inverter\\Libs\\RS232\\hds\\serialPortFIFO"
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)
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(vvPair
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variable "date"
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value "04.04.2023"
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)
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(vvPair
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variable "day"
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value "mar."
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)
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(vvPair
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variable "day_long"
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value "mardi"
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)
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(vvPair
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variable "dd"
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value "04"
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)
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(vvPair
|
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variable "designName"
|
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value "$DESIGN_NAME"
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)
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(vvPair
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variable "entity_name"
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value "serialPortFIFO"
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)
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(vvPair
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variable "ext"
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value "<TBD>"
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)
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(vvPair
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variable "f"
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value "struct.bd"
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)
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(vvPair
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variable "f_logical"
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value "struct.bd"
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)
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(vvPair
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variable "f_noext"
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value "struct"
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(vvPair
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variable "graphical_source_author"
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value "axel.amand"
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(vvPair
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variable "graphical_source_date"
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value "04.04.2023"
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)
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(vvPair
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variable "graphical_source_group"
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value "UNKNOWN"
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)
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(vvPair
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variable "graphical_source_host"
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value "WE7860"
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)
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(vvPair
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variable "graphical_source_time"
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value "13:25:55"
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)
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(vvPair
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variable "group"
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value "UNKNOWN"
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)
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(vvPair
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variable "host"
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value "WE7860"
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)
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(vvPair
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variable "language"
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value "VHDL"
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)
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(vvPair
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variable "library"
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value "RS232"
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)
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(vvPair
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variable "library_downstream_Concatenation"
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value "U:/ELN_Board/Synthesis"
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)
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(vvPair
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variable "library_downstream_Generic_1_file"
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value "U:\\ELN_Board\\Synthesis"
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)
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(vvPair
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variable "library_downstream_HdsLintPlugin"
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value "$HDS_PROJECT_DIR/../Demo/designcheck"
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)
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(vvPair
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variable "library_downstream_ModelSim"
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value "D:\\Users\\ELN_labs\\VHDL_comp"
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)
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(vvPair
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variable "library_downstream_ModelSimCompiler"
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value "$SCRATCH_DIR/Libraries/RS232/work"
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)
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(vvPair
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variable "library_downstream_SpyGlass"
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value "U:\\ELN_Board\\Synthesis"
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)
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(vvPair
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variable "mm"
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value "04"
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)
|
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(vvPair
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variable "module_name"
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value "serialPortFIFO"
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)
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(vvPair
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variable "month"
|
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value "avr."
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)
|
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(vvPair
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|
variable "month_long"
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value "avril"
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)
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(vvPair
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variable "p"
|
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value "C:\\dev\\did-inverter\\Libs\\RS232\\hds\\serial@port@f@i@f@o\\struct.bd"
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)
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(vvPair
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variable "p_logical"
|
|
value "C:\\dev\\did-inverter\\Libs\\RS232\\hds\\serialPortFIFO\\struct.bd"
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)
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(vvPair
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variable "package_name"
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value "<Undefined Variable>"
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)
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(vvPair
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variable "project_name"
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value "hds"
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)
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(vvPair
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variable "series"
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value "HDL Designer Series"
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)
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(vvPair
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variable "task_ActelPath"
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value "$ACTEL_HOME"
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)
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(vvPair
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variable "task_ActelProjectPath"
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value "$SCRATCH_DIR\\$DESIGN_NAME\\$ACTEL_WORK_DIR"
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)
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(vvPair
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variable "task_DesignCompilerPath"
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value "<TBD>"
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)
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(vvPair
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variable "task_HDSPath"
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value "$HDS_HOME"
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)
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(vvPair
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variable "task_ISEPath"
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value "D:\\Labs\\ElN\\BoardTester\\Board\\ise"
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)
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(vvPair
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variable "task_LeonardoPath"
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value "<TBD>"
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)
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(vvPair
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variable "task_ModelSimPath"
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value "<TBD>"
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)
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(vvPair
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variable "task_NC-SimPath"
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value "<TBD>"
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)
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(vvPair
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variable "task_PrecisionRTLPath"
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value "<TBD>"
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)
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(vvPair
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variable "task_QuestaSimPath"
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value "<TBD>"
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)
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(vvPair
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variable "task_VCSPath"
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value "<TBD>"
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)
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(vvPair
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variable "this_ext"
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value "bd"
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(vvPair
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variable "this_file"
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value "struct"
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(vvPair
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variable "this_file_logical"
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value "struct"
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(vvPair
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variable "time"
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value "13:25:55"
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(vvPair
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variable "unit"
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value "serialPortFIFO"
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(vvPair
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variable "user"
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value "axel.amand"
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variable "version"
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value "2019.2 (Build 5)"
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variable "view"
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value "struct"
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variable "year"
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value "2023"
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variable "yy"
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oxt "14000,70000,18000,71000"
|
|
text (MLText
|
|
uid 37,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
)
|
|
xt "70200,73500,70200,73500"
|
|
st "
|
|
Edited:
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 4000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
)
|
|
*11 (CommentText
|
|
uid 38,0
|
|
shape (Rectangle
|
|
uid 39,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "74000,72000,91000,73000"
|
|
)
|
|
oxt "18000,69000,35000,70000"
|
|
text (MLText
|
|
uid 40,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
)
|
|
xt "74200,72500,74200,72500"
|
|
st "
|
|
%library/%unit/%view
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 17000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
)
|
|
]
|
|
shape (GroupingShape
|
|
uid 10,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
lineWidth 2
|
|
)
|
|
xt "70000,69000,111000,74000"
|
|
)
|
|
oxt "14000,66000,55000,71000"
|
|
)
|
|
*12 (PortIoIn
|
|
uid 53,0
|
|
shape (CompositeShape
|
|
uid 54,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
uid 55,0
|
|
sl 0
|
|
ro 270
|
|
xt "15000,28625,16500,29375"
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)
|
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(Line
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|
uid 56,0
|
|
sl 0
|
|
ro 270
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|
xt "16500,29000,17000,29000"
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pts [
|
|
"16500,29000"
|
|
"17000,29000"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
uid 57,0
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 58,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "10200,28300,14000,29700"
|
|
st "clock"
|
|
ju 2
|
|
blo "14000,29500"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
*13 (Net
|
|
uid 65,0
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 1,0
|
|
)
|
|
declText (MLText
|
|
uid 66,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,8700,12300,9700"
|
|
st "clock : std_ulogic"
|
|
)
|
|
)
|
|
*14 (PortIoIn
|
|
uid 95,0
|
|
shape (CompositeShape
|
|
uid 96,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
uid 97,0
|
|
sl 0
|
|
ro 270
|
|
xt "15000,30625,16500,31375"
|
|
)
|
|
(Line
|
|
uid 98,0
|
|
sl 0
|
|
ro 270
|
|
xt "16500,31000,17000,31000"
|
|
pts [
|
|
"16500,31000"
|
|
"17000,31000"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
uid 99,0
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 100,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "9900,30300,14000,31700"
|
|
st "reset"
|
|
ju 2
|
|
blo "14000,31500"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
*15 (Net
|
|
uid 107,0
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 4,0
|
|
)
|
|
declText (MLText
|
|
uid 108,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,9500,12300,10500"
|
|
st "reset : std_ulogic"
|
|
)
|
|
)
|
|
*16 (PortIoIn
|
|
uid 109,0
|
|
shape (CompositeShape
|
|
uid 110,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
uid 111,0
|
|
sl 0
|
|
ro 270
|
|
xt "15000,24625,16500,25375"
|
|
)
|
|
(Line
|
|
uid 112,0
|
|
sl 0
|
|
ro 270
|
|
xt "16500,25000,17000,25000"
|
|
pts [
|
|
"16500,25000"
|
|
"17000,25000"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
uid 113,0
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 114,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "10800,24300,14000,25700"
|
|
st "RxD"
|
|
ju 2
|
|
blo "14000,25500"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
*17 (Net
|
|
uid 121,0
|
|
decl (Decl
|
|
n "RxD"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 5,0
|
|
)
|
|
declText (MLText
|
|
uid 122,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,7100,12600,8100"
|
|
st "RxD : std_ulogic"
|
|
)
|
|
)
|
|
*18 (PortIoOut
|
|
uid 137,0
|
|
shape (CompositeShape
|
|
uid 138,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
uid 139,0
|
|
sl 0
|
|
ro 90
|
|
xt "15000,46625,16500,47375"
|
|
)
|
|
(Line
|
|
uid 140,0
|
|
sl 0
|
|
ro 90
|
|
xt "16500,47000,17000,47000"
|
|
pts [
|
|
"17000,47000"
|
|
"16500,47000"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
uid 141,0
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 142,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "10900,46300,14000,47700"
|
|
st "TxD"
|
|
ju 2
|
|
blo "14000,47500"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
*19 (Net
|
|
uid 149,0
|
|
decl (Decl
|
|
n "TxD"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 7,0
|
|
)
|
|
declText (MLText
|
|
uid 150,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,7900,12500,8900"
|
|
st "TxD : std_ulogic"
|
|
)
|
|
)
|
|
*20 (Net
|
|
uid 670,0
|
|
decl (Decl
|
|
n "txFifoEmpty"
|
|
t "std_ulogic"
|
|
o 14
|
|
suid 16,0
|
|
)
|
|
declText (MLText
|
|
uid 671,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,18500,16600,19500"
|
|
st "SIGNAL txFifoEmpty : std_ulogic"
|
|
)
|
|
)
|
|
*21 (Net
|
|
uid 763,0
|
|
decl (Decl
|
|
n "txBusy"
|
|
t "std_ulogic"
|
|
o 16
|
|
suid 18,0
|
|
)
|
|
declText (MLText
|
|
uid 764,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,20100,15900,21100"
|
|
st "SIGNAL txBusy : std_ulogic"
|
|
)
|
|
)
|
|
*22 (Net
|
|
uid 773,0
|
|
decl (Decl
|
|
n "txSend"
|
|
t "std_ulogic"
|
|
o 11
|
|
suid 19,0
|
|
)
|
|
declText (MLText
|
|
uid 774,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,16100,16000,17100"
|
|
st "SIGNAL txSend : std_ulogic"
|
|
)
|
|
)
|
|
*23 (PortIoOut
|
|
uid 1370,0
|
|
shape (CompositeShape
|
|
uid 1371,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
uid 1372,0
|
|
sl 0
|
|
ro 270
|
|
xt "77500,28625,79000,29375"
|
|
)
|
|
(Line
|
|
uid 1373,0
|
|
sl 0
|
|
ro 270
|
|
xt "77000,29000,77500,29000"
|
|
pts [
|
|
"77000,29000"
|
|
"77500,29000"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
uid 1374,0
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1375,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "80000,28500,85900,29900"
|
|
st "rxEmpty"
|
|
blo "80000,29700"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
*24 (Net
|
|
uid 1382,0
|
|
decl (Decl
|
|
n "rxEmpty"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 20,0
|
|
)
|
|
declText (MLText
|
|
uid 1383,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,10300,13100,11300"
|
|
st "rxEmpty : std_ulogic"
|
|
)
|
|
)
|
|
*25 (PortIoIn
|
|
uid 1384,0
|
|
shape (CompositeShape
|
|
uid 1385,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
uid 1386,0
|
|
sl 0
|
|
ro 90
|
|
xt "77500,26625,79000,27375"
|
|
)
|
|
(Line
|
|
uid 1387,0
|
|
sl 0
|
|
ro 90
|
|
xt "77000,27000,77500,27000"
|
|
pts [
|
|
"77500,27000"
|
|
"77000,27000"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
uid 1388,0
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1389,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "80000,26300,83600,27700"
|
|
st "rxRd"
|
|
blo "80000,27500"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
*26 (Net
|
|
uid 1396,0
|
|
decl (Decl
|
|
n "rxRd"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 21,0
|
|
)
|
|
declText (MLText
|
|
uid 1397,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,11100,12500,12100"
|
|
st "rxRd : std_ulogic"
|
|
)
|
|
)
|
|
*27 (Net
|
|
uid 1398,0
|
|
decl (Decl
|
|
n "rxWord"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 12
|
|
suid 22,0
|
|
)
|
|
declText (MLText
|
|
uid 1399,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,16900,30000,17900"
|
|
st "SIGNAL rxWord : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
|
|
)
|
|
)
|
|
*28 (Net
|
|
uid 1400,0
|
|
decl (Decl
|
|
n "txWord"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 15
|
|
suid 23,0
|
|
)
|
|
declText (MLText
|
|
uid 1401,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,19300,30000,20300"
|
|
st "SIGNAL txWord : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
|
|
)
|
|
)
|
|
*29 (Net
|
|
uid 1402,0
|
|
decl (Decl
|
|
n "rxWordValid"
|
|
t "std_ulogic"
|
|
o 13
|
|
suid 24,0
|
|
)
|
|
declText (MLText
|
|
uid 1403,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,17700,16500,18700"
|
|
st "SIGNAL rxWordValid : std_ulogic"
|
|
)
|
|
)
|
|
*30 (HdlText
|
|
uid 1410,0
|
|
optionalChildren [
|
|
*31 (EmbeddedText
|
|
uid 1415,0
|
|
commentText (CommentText
|
|
uid 1416,0
|
|
ps "CenterOffsetStrategy"
|
|
shape (Rectangle
|
|
uid 1417,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
)
|
|
xt "53000,52000,69000,66000"
|
|
)
|
|
oxt "0,0,18000,5000"
|
|
text (MLText
|
|
uid 1418,0
|
|
va (VaSet
|
|
)
|
|
xt "53200,52200,68500,65400"
|
|
st "
|
|
process(reset, clock)
|
|
begin
|
|
if reset = '1' then
|
|
txSend <= '0';
|
|
elsif rising_edge(clock) then
|
|
if ( (txFifoEmpty = '0') and (txBusy = '0') ) then
|
|
txSend <= '1';
|
|
else
|
|
txSend <= '0';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
"
|
|
tm "HdlTextMgr"
|
|
wrapOption 3
|
|
visibleHeight 14000
|
|
visibleWidth 16000
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 1411,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,32768"
|
|
)
|
|
xt "53000,51000,69000,67000"
|
|
)
|
|
oxt "0,0,8000,10000"
|
|
ttg (MlTextGroup
|
|
uid 1412,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*32 (Text
|
|
uid 1413,0
|
|
va (VaSet
|
|
)
|
|
xt "53400,67000,56000,68200"
|
|
st "eb1"
|
|
blo "53400,68000"
|
|
tm "HdlTextNameMgr"
|
|
)
|
|
*33 (Text
|
|
uid 1414,0
|
|
va (VaSet
|
|
)
|
|
xt "53400,68000,54800,69200"
|
|
st "1"
|
|
blo "53400,69000"
|
|
tm "HdlTextNumberMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
*34 (PortIoOut
|
|
uid 1431,0
|
|
shape (CompositeShape
|
|
uid 1432,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
uid 1433,0
|
|
sl 0
|
|
ro 270
|
|
xt "105500,64625,107000,65375"
|
|
)
|
|
(Line
|
|
uid 1434,0
|
|
sl 0
|
|
ro 270
|
|
xt "105000,65000,105500,65000"
|
|
pts [
|
|
"105000,65000"
|
|
"105500,65000"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
uid 1435,0
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1436,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "108000,64300,112100,65700"
|
|
st "txFull"
|
|
blo "108000,65500"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
*35 (Net
|
|
uid 1443,0
|
|
decl (Decl
|
|
n "txFull"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 25,0
|
|
)
|
|
declText (MLText
|
|
uid 1444,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,13500,12200,14500"
|
|
st "txFull : std_ulogic"
|
|
)
|
|
)
|
|
*36 (PortIoIn
|
|
uid 1445,0
|
|
shape (CompositeShape
|
|
uid 1446,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
uid 1447,0
|
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sl 0
|
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ro 90
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|
xt "105500,48625,107000,49375"
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)
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(Line
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|
uid 1448,0
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sl 0
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ro 90
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xt "105000,49000,105500,49000"
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pts [
|
|
"105500,49000"
|
|
"105000,49000"
|
|
]
|
|
)
|
|
]
|
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)
|
|
tg (WTG
|
|
uid 1449,0
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1450,0
|
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va (VaSet
|
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isHidden 1
|
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font "Verdana,12,0"
|
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)
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xt "108000,48300,111800,49700"
|
|
st "txWr"
|
|
blo "108000,49500"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
*37 (Net
|
|
uid 1457,0
|
|
decl (Decl
|
|
n "txWr"
|
|
t "std_ulogic"
|
|
o 10
|
|
suid 26,0
|
|
)
|
|
declText (MLText
|
|
uid 1458,0
|
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va (VaSet
|
|
font "Verdana,8,0"
|
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)
|
|
xt "2000,14300,12500,15300"
|
|
st "txWr : std_ulogic"
|
|
)
|
|
)
|
|
*38 (PortIoOut
|
|
uid 1459,0
|
|
shape (CompositeShape
|
|
uid 1460,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
uid 1461,0
|
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sl 0
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ro 270
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xt "77500,24625,79000,25375"
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)
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(Line
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|
uid 1462,0
|
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sl 0
|
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ro 270
|
|
xt "77000,25000,77500,25000"
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pts [
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"77000,25000"
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|
"77500,25000"
|
|
]
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|
)
|
|
]
|
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)
|
|
tg (WTG
|
|
uid 1463,0
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1464,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "80000,24300,103800,25700"
|
|
st "rxData : (dataBitNb-1 DOWNTO 0)"
|
|
blo "80000,25500"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
*39 (Net
|
|
uid 1465,0
|
|
decl (Decl
|
|
n "rxData"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 7
|
|
suid 27,0
|
|
)
|
|
declText (MLText
|
|
uid 1466,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,11900,26600,12900"
|
|
st "rxData : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
|
|
)
|
|
)
|
|
*40 (Net
|
|
uid 1469,0
|
|
decl (Decl
|
|
n "txData"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 8
|
|
suid 28,0
|
|
)
|
|
declText (MLText
|
|
uid 1470,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,12700,26600,13700"
|
|
st "txData : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
|
|
)
|
|
)
|
|
*41 (PortIoIn
|
|
uid 1471,0
|
|
shape (CompositeShape
|
|
uid 1472,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
uid 1473,0
|
|
sl 0
|
|
ro 90
|
|
xt "105500,46625,107000,47375"
|
|
)
|
|
(Line
|
|
uid 1474,0
|
|
sl 0
|
|
ro 90
|
|
xt "105000,47000,105500,47000"
|
|
pts [
|
|
"105500,47000"
|
|
"105000,47000"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
uid 1475,0
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1476,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "108000,46500,131800,47900"
|
|
st "txData : (dataBitNb-1 DOWNTO 0)"
|
|
blo "108000,47700"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
*42 (SaComponent
|
|
uid 1663,0
|
|
optionalChildren [
|
|
*43 (CptPort
|
|
uid 1643,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1644,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "24250,24625,25000,25375"
|
|
)
|
|
tg (CPTG
|
|
uid 1645,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1646,0
|
|
va (VaSet
|
|
)
|
|
xt "26000,24400,28800,25600"
|
|
st "RxD"
|
|
blo "26000,25400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "RxD"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*44 (CptPort
|
|
uid 1647,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1648,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "24250,28625,25000,29375"
|
|
)
|
|
tg (CPTG
|
|
uid 1649,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1650,0
|
|
va (VaSet
|
|
)
|
|
xt "26000,28400,29400,29600"
|
|
st "clock"
|
|
blo "26000,29400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 2,0
|
|
)
|
|
)
|
|
)
|
|
*45 (CptPort
|
|
uid 1651,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1652,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "24250,30625,25000,31375"
|
|
)
|
|
tg (CPTG
|
|
uid 1653,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1654,0
|
|
va (VaSet
|
|
)
|
|
xt "26000,30400,29300,31600"
|
|
st "reset"
|
|
blo "26000,31400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*46 (CptPort
|
|
uid 1655,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1656,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "41000,24625,41750,25375"
|
|
)
|
|
tg (CPTG
|
|
uid 1657,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1658,0
|
|
va (VaSet
|
|
)
|
|
xt "35201,24400,40001,25600"
|
|
st "dataOut"
|
|
ju 2
|
|
blo "40001,25400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "dataOut"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
*47 (CptPort
|
|
uid 1659,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1660,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "41000,26625,41750,27375"
|
|
)
|
|
tg (CPTG
|
|
uid 1661,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1662,0
|
|
va (VaSet
|
|
)
|
|
xt "34500,26400,40000,27600"
|
|
st "dataValid"
|
|
ju 2
|
|
blo "40000,27400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "dataValid"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 5,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 1664,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
bg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "25000,21000,41000,33000"
|
|
)
|
|
oxt "34000,16000,50000,28000"
|
|
ttg (MlTextGroup
|
|
uid 1665,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*48 (Text
|
|
uid 1666,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "25600,32800,29300,34000"
|
|
st "RS232"
|
|
blo "25600,33800"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*49 (Text
|
|
uid 1667,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "25600,34000,36000,35200"
|
|
st "serialPortReceiver"
|
|
blo "25600,35000"
|
|
tm "CptNameMgr"
|
|
)
|
|
*50 (Text
|
|
uid 1668,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "25600,35200,28300,36400"
|
|
st "I_rx"
|
|
blo "25600,36200"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 1669,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 1670,0
|
|
text (MLText
|
|
uid 1671,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "25000,36400,47400,38400"
|
|
st "dataBitNb = dataBitNb ( positive )
|
|
baudRateDivide = baudRateDivide ( positive ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "dataBitNb"
|
|
type "positive"
|
|
value "dataBitNb"
|
|
)
|
|
(GiElement
|
|
name "baudRateDivide"
|
|
type "positive"
|
|
value "baudRateDivide"
|
|
)
|
|
]
|
|
)
|
|
ordering 1
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*51 (SaComponent
|
|
uid 1696,0
|
|
optionalChildren [
|
|
*52 (CptPort
|
|
uid 1672,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1673,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "24250,46625,25000,47375"
|
|
)
|
|
tg (CPTG
|
|
uid 1674,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1675,0
|
|
va (VaSet
|
|
)
|
|
xt "26000,46400,28800,47600"
|
|
st "TxD"
|
|
blo "26000,47400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "TxD"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*53 (CptPort
|
|
uid 1676,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1677,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "41000,54625,41750,55375"
|
|
)
|
|
tg (CPTG
|
|
uid 1678,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1679,0
|
|
va (VaSet
|
|
)
|
|
xt "36600,54400,40000,55600"
|
|
st "clock"
|
|
ju 2
|
|
blo "40000,55400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 2,0
|
|
)
|
|
)
|
|
)
|
|
*54 (CptPort
|
|
uid 1680,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1681,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "41000,56625,41750,57375"
|
|
)
|
|
tg (CPTG
|
|
uid 1682,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1683,0
|
|
va (VaSet
|
|
)
|
|
xt "36700,56400,40000,57600"
|
|
st "reset"
|
|
ju 2
|
|
blo "40000,57400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*55 (CptPort
|
|
uid 1684,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1685,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "41000,46625,41750,47375"
|
|
)
|
|
tg (CPTG
|
|
uid 1686,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1687,0
|
|
va (VaSet
|
|
)
|
|
xt "36001,46400,40001,47600"
|
|
st "dataIn"
|
|
ju 2
|
|
blo "40001,47400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "dataIn"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
*56 (CptPort
|
|
uid 1688,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1689,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "41000,48625,41750,49375"
|
|
)
|
|
tg (CPTG
|
|
uid 1690,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1691,0
|
|
va (VaSet
|
|
)
|
|
xt "36900,48400,40000,49600"
|
|
st "send"
|
|
ju 2
|
|
blo "40000,49400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "send"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 5,0
|
|
)
|
|
)
|
|
)
|
|
*57 (CptPort
|
|
uid 1692,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1693,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "41000,50625,41750,51375"
|
|
)
|
|
tg (CPTG
|
|
uid 1694,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1695,0
|
|
va (VaSet
|
|
)
|
|
xt "36900,50400,40000,51600"
|
|
st "busy"
|
|
ju 2
|
|
blo "40000,51400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "busy"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 6,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 1697,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
bg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "25000,43000,41000,59000"
|
|
)
|
|
oxt "34000,12000,50000,28000"
|
|
ttg (MlTextGroup
|
|
uid 1698,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*58 (Text
|
|
uid 1699,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "25600,58800,29300,60000"
|
|
st "RS232"
|
|
blo "25600,59800"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*59 (Text
|
|
uid 1700,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "25600,60000,38200,61200"
|
|
st "serialPortTransmitter"
|
|
blo "25600,61000"
|
|
tm "CptNameMgr"
|
|
)
|
|
*60 (Text
|
|
uid 1701,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "25600,61200,28400,62400"
|
|
st "I_tx"
|
|
blo "25600,62200"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 1702,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 1703,0
|
|
text (MLText
|
|
uid 1704,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "25000,62400,47400,64400"
|
|
st "dataBitNb = dataBitNb ( positive )
|
|
baudRateDivide = baudRateDivide ( positive ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "dataBitNb"
|
|
type "positive"
|
|
value "dataBitNb"
|
|
)
|
|
(GiElement
|
|
name "baudRateDivide"
|
|
type "positive"
|
|
value "baudRateDivide"
|
|
)
|
|
]
|
|
)
|
|
ordering 1
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*61 (SaComponent
|
|
uid 1778,0
|
|
optionalChildren [
|
|
*62 (CptPort
|
|
uid 1746,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1747,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "52250,26625,53000,27375"
|
|
)
|
|
tg (CPTG
|
|
uid 1748,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1749,0
|
|
va (VaSet
|
|
)
|
|
xt "54000,26400,57100,27600"
|
|
st "write"
|
|
blo "54000,27400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "write"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*63 (CptPort
|
|
uid 1750,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1751,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "52250,30625,53000,31375"
|
|
)
|
|
tg (CPTG
|
|
uid 1752,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1753,0
|
|
va (VaSet
|
|
)
|
|
xt "54000,30400,57400,31600"
|
|
st "clock"
|
|
blo "54000,31400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 2,0
|
|
)
|
|
)
|
|
)
|
|
*64 (CptPort
|
|
uid 1754,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1755,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "52250,32625,53000,33375"
|
|
)
|
|
tg (CPTG
|
|
uid 1756,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1757,0
|
|
va (VaSet
|
|
)
|
|
xt "54000,32400,57300,33600"
|
|
st "reset"
|
|
blo "54000,33400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*65 (CptPort
|
|
uid 1758,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1759,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "69000,24625,69750,25375"
|
|
)
|
|
tg (CPTG
|
|
uid 1760,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1761,0
|
|
va (VaSet
|
|
)
|
|
xt "63201,24400,68001,25600"
|
|
st "dataOut"
|
|
ju 2
|
|
blo "68001,25400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "dataOut"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
*66 (CptPort
|
|
uid 1762,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1763,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "69000,26625,69750,27375"
|
|
)
|
|
tg (CPTG
|
|
uid 1764,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1765,0
|
|
va (VaSet
|
|
)
|
|
xt "65100,26400,68000,27600"
|
|
st "read"
|
|
ju 2
|
|
blo "68000,27400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "read"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 5,0
|
|
)
|
|
)
|
|
)
|
|
*67 (CptPort
|
|
uid 1766,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1767,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "52250,24625,53000,25375"
|
|
)
|
|
tg (CPTG
|
|
uid 1768,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1769,0
|
|
va (VaSet
|
|
)
|
|
xt "53999,24400,57999,25600"
|
|
st "dataIn"
|
|
blo "53999,25400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "dataIn"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 6
|
|
suid 6,0
|
|
)
|
|
)
|
|
)
|
|
*68 (CptPort
|
|
uid 1770,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1771,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "69000,28625,69750,29375"
|
|
)
|
|
tg (CPTG
|
|
uid 1772,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1773,0
|
|
va (VaSet
|
|
)
|
|
xt "64200,28400,68000,29600"
|
|
st "empty"
|
|
ju 2
|
|
blo "68000,29400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "empty"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 7,0
|
|
)
|
|
)
|
|
)
|
|
*69 (CptPort
|
|
uid 1774,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1775,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "69000,30625,69750,31375"
|
|
)
|
|
tg (CPTG
|
|
uid 1776,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1777,0
|
|
va (VaSet
|
|
)
|
|
xt "65800,30400,68000,31600"
|
|
st "full"
|
|
ju 2
|
|
blo "68000,31400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "full"
|
|
t "std_ulogic"
|
|
o 8
|
|
suid 8,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 1779,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
bg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "53000,21000,69000,35000"
|
|
)
|
|
oxt "34000,14000,50000,28000"
|
|
ttg (MlTextGroup
|
|
uid 1780,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*70 (Text
|
|
uid 1781,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "53600,34800,58200,36000"
|
|
st "memory"
|
|
blo "53600,35800"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*71 (Text
|
|
uid 1782,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "53600,36000,56700,37200"
|
|
st "FIFO"
|
|
blo "53600,37000"
|
|
tm "CptNameMgr"
|
|
)
|
|
*72 (Text
|
|
uid 1783,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "53600,37200,58300,38400"
|
|
st "I_rxFifo"
|
|
blo "53600,38200"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 1784,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 1785,0
|
|
text (MLText
|
|
uid 1786,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "53000,38400,71000,40400"
|
|
st "dataBitNb = dataBitNb ( positive )
|
|
depth = rxFifoDepth ( positive ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "dataBitNb"
|
|
type "positive"
|
|
value "dataBitNb"
|
|
)
|
|
(GiElement
|
|
name "depth"
|
|
type "positive"
|
|
value "rxFifoDepth"
|
|
)
|
|
]
|
|
)
|
|
ordering 1
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*73 (SaComponent
|
|
uid 1819,0
|
|
optionalChildren [
|
|
*74 (CptPort
|
|
uid 1787,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1788,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "97000,48625,97750,49375"
|
|
)
|
|
tg (CPTG
|
|
uid 1789,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1790,0
|
|
va (VaSet
|
|
)
|
|
xt "92900,48400,96000,49600"
|
|
st "write"
|
|
ju 2
|
|
blo "96000,49400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "write"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*75 (CptPort
|
|
uid 1791,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1792,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "97000,52625,97750,53375"
|
|
)
|
|
tg (CPTG
|
|
uid 1793,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1794,0
|
|
va (VaSet
|
|
)
|
|
xt "92600,52400,96000,53600"
|
|
st "clock"
|
|
ju 2
|
|
blo "96000,53400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 2,0
|
|
)
|
|
)
|
|
)
|
|
*76 (CptPort
|
|
uid 1795,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1796,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "97000,54625,97750,55375"
|
|
)
|
|
tg (CPTG
|
|
uid 1797,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1798,0
|
|
va (VaSet
|
|
)
|
|
xt "92700,54400,96000,55600"
|
|
st "reset"
|
|
ju 2
|
|
blo "96000,55400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*77 (CptPort
|
|
uid 1799,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1800,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "80250,46625,81000,47375"
|
|
)
|
|
tg (CPTG
|
|
uid 1801,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1802,0
|
|
va (VaSet
|
|
)
|
|
xt "81999,46400,86799,47600"
|
|
st "dataOut"
|
|
blo "81999,47400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "dataOut"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
*78 (CptPort
|
|
uid 1803,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1804,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "80250,48625,81000,49375"
|
|
)
|
|
tg (CPTG
|
|
uid 1805,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1806,0
|
|
va (VaSet
|
|
)
|
|
xt "82000,48400,84900,49600"
|
|
st "read"
|
|
blo "82000,49400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "read"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 5,0
|
|
)
|
|
)
|
|
)
|
|
*79 (CptPort
|
|
uid 1807,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1808,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "97000,46625,97750,47375"
|
|
)
|
|
tg (CPTG
|
|
uid 1809,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1810,0
|
|
va (VaSet
|
|
)
|
|
xt "92001,46400,96001,47600"
|
|
st "dataIn"
|
|
ju 2
|
|
blo "96001,47400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "dataIn"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 6
|
|
suid 6,0
|
|
)
|
|
)
|
|
)
|
|
*80 (CptPort
|
|
uid 1811,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1812,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "80250,50625,81000,51375"
|
|
)
|
|
tg (CPTG
|
|
uid 1813,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1814,0
|
|
va (VaSet
|
|
)
|
|
xt "82000,50400,85800,51600"
|
|
st "empty"
|
|
blo "82000,51400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "empty"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 7,0
|
|
)
|
|
)
|
|
)
|
|
*81 (CptPort
|
|
uid 1815,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1816,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "80250,52625,81000,53375"
|
|
)
|
|
tg (CPTG
|
|
uid 1817,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1818,0
|
|
va (VaSet
|
|
)
|
|
xt "82000,52400,84200,53600"
|
|
st "full"
|
|
blo "82000,53400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "full"
|
|
t "std_ulogic"
|
|
o 8
|
|
suid 8,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 1820,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
bg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "81000,43000,97000,57000"
|
|
)
|
|
oxt "34000,14000,50000,28000"
|
|
ttg (MlTextGroup
|
|
uid 1821,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*82 (Text
|
|
uid 1822,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "81600,56800,86200,58000"
|
|
st "memory"
|
|
blo "81600,57800"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*83 (Text
|
|
uid 1823,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "81600,58000,84700,59200"
|
|
st "FIFO"
|
|
blo "81600,59000"
|
|
tm "CptNameMgr"
|
|
)
|
|
*84 (Text
|
|
uid 1824,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "81600,59200,86400,60400"
|
|
st "I_txFifo"
|
|
blo "81600,60200"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 1825,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 1826,0
|
|
text (MLText
|
|
uid 1827,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "81000,60400,99000,62400"
|
|
st "dataBitNb = dataBitNb ( positive )
|
|
depth = txFifoDepth ( positive ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "dataBitNb"
|
|
type "positive"
|
|
value "dataBitNb"
|
|
)
|
|
(GiElement
|
|
name "depth"
|
|
type "positive"
|
|
value "txFifoDepth"
|
|
)
|
|
]
|
|
)
|
|
ordering 1
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*85 (Wire
|
|
uid 59,0
|
|
shape (OrthoPolyLine
|
|
uid 60,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "17000,29000,24250,29000"
|
|
pts [
|
|
"17000,29000"
|
|
"24250,29000"
|
|
]
|
|
)
|
|
start &12
|
|
end &44
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 63,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 64,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "19000,27600,22800,29000"
|
|
st "clock"
|
|
blo "19000,28800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &13
|
|
)
|
|
*86 (Wire
|
|
uid 101,0
|
|
shape (OrthoPolyLine
|
|
uid 102,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "17000,31000,24250,31000"
|
|
pts [
|
|
"17000,31000"
|
|
"24250,31000"
|
|
]
|
|
)
|
|
start &14
|
|
end &45
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 105,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 106,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "19000,29600,23100,31000"
|
|
st "reset"
|
|
blo "19000,30800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &15
|
|
)
|
|
*87 (Wire
|
|
uid 115,0
|
|
shape (OrthoPolyLine
|
|
uid 116,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "17000,25000,24250,25000"
|
|
pts [
|
|
"17000,25000"
|
|
"24250,25000"
|
|
]
|
|
)
|
|
start &16
|
|
end &43
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 119,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 120,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "19000,23600,22200,25000"
|
|
st "RxD"
|
|
blo "19000,24800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &17
|
|
)
|
|
*88 (Wire
|
|
uid 143,0
|
|
shape (OrthoPolyLine
|
|
uid 144,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "17000,47000,24250,47000"
|
|
pts [
|
|
"24250,47000"
|
|
"17000,47000"
|
|
]
|
|
)
|
|
start &52
|
|
end &18
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 147,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 148,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "20000,44600,23100,46000"
|
|
st "TxD"
|
|
blo "20000,45800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &19
|
|
)
|
|
*89 (Wire
|
|
uid 230,0
|
|
shape (OrthoPolyLine
|
|
uid 231,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "41750,25000,52250,25000"
|
|
pts [
|
|
"41750,25000"
|
|
"52250,25000"
|
|
]
|
|
)
|
|
start &46
|
|
end &67
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 234,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 235,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "43000,23600,48400,25000"
|
|
st "rxWord"
|
|
blo "43000,24800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &27
|
|
)
|
|
*90 (Wire
|
|
uid 240,0
|
|
shape (OrthoPolyLine
|
|
uid 241,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "41750,27000,52250,27000"
|
|
pts [
|
|
"41750,27000"
|
|
"52250,27000"
|
|
]
|
|
)
|
|
start &47
|
|
end &62
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 244,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 245,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "43000,25600,52200,27000"
|
|
st "rxWordValid"
|
|
blo "43000,26800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &29
|
|
)
|
|
*91 (Wire
|
|
uid 374,0
|
|
shape (OrthoPolyLine
|
|
uid 375,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "49000,33000,52250,33000"
|
|
pts [
|
|
"49000,33000"
|
|
"52250,33000"
|
|
]
|
|
)
|
|
end &64
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 380,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 381,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "48000,31600,52100,33000"
|
|
st "reset"
|
|
blo "48000,32800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &15
|
|
)
|
|
*92 (Wire
|
|
uid 382,0
|
|
shape (OrthoPolyLine
|
|
uid 383,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "49000,31000,52250,31000"
|
|
pts [
|
|
"49000,31000"
|
|
"52250,31000"
|
|
]
|
|
)
|
|
end &63
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 388,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 389,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "48000,29600,51800,31000"
|
|
st "clock"
|
|
blo "48000,30800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &13
|
|
)
|
|
*93 (Wire
|
|
uid 444,0
|
|
shape (OrthoPolyLine
|
|
uid 445,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "69750,25000,77000,25000"
|
|
pts [
|
|
"69750,25000"
|
|
"77000,25000"
|
|
]
|
|
)
|
|
start &65
|
|
end &38
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 448,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 449,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "72000,23600,77000,25000"
|
|
st "rxData"
|
|
blo "72000,24800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &39
|
|
)
|
|
*94 (Wire
|
|
uid 601,0
|
|
shape (OrthoPolyLine
|
|
uid 602,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "97750,55000,101000,55000"
|
|
pts [
|
|
"101000,55000"
|
|
"97750,55000"
|
|
]
|
|
)
|
|
end &76
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 607,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 608,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "99000,53600,103100,55000"
|
|
st "reset"
|
|
blo "99000,54800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &15
|
|
)
|
|
*95 (Wire
|
|
uid 609,0
|
|
shape (OrthoPolyLine
|
|
uid 610,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "97750,53000,101000,53000"
|
|
pts [
|
|
"101000,53000"
|
|
"97750,53000"
|
|
]
|
|
)
|
|
end &75
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 615,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 616,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "99000,51600,102800,53000"
|
|
st "clock"
|
|
blo "99000,52800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &13
|
|
)
|
|
*96 (Wire
|
|
uid 654,0
|
|
shape (OrthoPolyLine
|
|
uid 655,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "97750,47000,105000,47000"
|
|
pts [
|
|
"97750,47000"
|
|
"105000,47000"
|
|
]
|
|
)
|
|
start &79
|
|
end &41
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 658,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 659,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "101000,45600,106000,47000"
|
|
st "txData"
|
|
blo "101000,46800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &40
|
|
)
|
|
*97 (Wire
|
|
uid 664,0
|
|
shape (OrthoPolyLine
|
|
uid 665,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "69000,51000,80250,55000"
|
|
pts [
|
|
"80250,51000"
|
|
"73000,51000"
|
|
"73000,55000"
|
|
"69000,55000"
|
|
]
|
|
)
|
|
start &80
|
|
end &30
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 668,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 669,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "71000,49600,79900,51000"
|
|
st "txFifoEmpty"
|
|
blo "71000,50800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &20
|
|
)
|
|
*98 (Wire
|
|
uid 674,0
|
|
shape (OrthoPolyLine
|
|
uid 675,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "41750,47000,80250,47000"
|
|
pts [
|
|
"80250,47000"
|
|
"41750,47000"
|
|
]
|
|
)
|
|
start &77
|
|
end &55
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 678,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 679,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "74000,45600,79400,47000"
|
|
st "txWord"
|
|
blo "74000,46800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &28
|
|
)
|
|
*99 (Wire
|
|
uid 739,0
|
|
shape (OrthoPolyLine
|
|
uid 740,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "41750,57000,45000,57000"
|
|
pts [
|
|
"45000,57000"
|
|
"41750,57000"
|
|
]
|
|
)
|
|
end &54
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 745,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 746,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "43000,55600,47100,57000"
|
|
st "reset"
|
|
blo "43000,56800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &15
|
|
)
|
|
*100 (Wire
|
|
uid 747,0
|
|
shape (OrthoPolyLine
|
|
uid 748,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "41750,55000,45000,55000"
|
|
pts [
|
|
"45000,55000"
|
|
"41750,55000"
|
|
]
|
|
)
|
|
end &53
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 753,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 754,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "43000,53600,46800,55000"
|
|
st "clock"
|
|
blo "43000,54800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &13
|
|
)
|
|
*101 (Wire
|
|
uid 757,0
|
|
shape (OrthoPolyLine
|
|
uid 758,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "41750,51000,53000,57000"
|
|
pts [
|
|
"41750,51000"
|
|
"49000,51000"
|
|
"49000,57000"
|
|
"53000,57000"
|
|
]
|
|
)
|
|
start &57
|
|
end &30
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 761,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 762,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "43750,49600,48750,51000"
|
|
st "txBusy"
|
|
blo "43750,50800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &21
|
|
)
|
|
*102 (Wire
|
|
uid 765,0
|
|
optionalChildren [
|
|
*103 (BdJunction
|
|
uid 1425,0
|
|
ps "OnConnectorStrategy"
|
|
shape (Circle
|
|
uid 1426,0
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "50600,48600,51400,49400"
|
|
radius 400
|
|
)
|
|
)
|
|
]
|
|
shape (OrthoPolyLine
|
|
uid 766,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "41750,49000,80250,49000"
|
|
pts [
|
|
"80250,49000"
|
|
"41750,49000"
|
|
]
|
|
)
|
|
start &78
|
|
end &56
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 771,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 772,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "43000,47600,48200,49000"
|
|
st "txSend"
|
|
blo "43000,48800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &22
|
|
)
|
|
*104 (Wire
|
|
uid 1376,0
|
|
shape (OrthoPolyLine
|
|
uid 1377,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "69750,29000,77000,29000"
|
|
pts [
|
|
"69750,29000"
|
|
"77000,29000"
|
|
]
|
|
)
|
|
start &68
|
|
end &23
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1380,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1381,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "71000,27600,76900,29000"
|
|
st "rxEmpty"
|
|
blo "71000,28800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &24
|
|
)
|
|
*105 (Wire
|
|
uid 1390,0
|
|
shape (OrthoPolyLine
|
|
uid 1391,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "69750,27000,77000,27000"
|
|
pts [
|
|
"77000,27000"
|
|
"69750,27000"
|
|
]
|
|
)
|
|
start &25
|
|
end &66
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1394,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1395,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "73000,25600,76600,27000"
|
|
st "rxRd"
|
|
blo "73000,26800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &26
|
|
)
|
|
*106 (Wire
|
|
uid 1419,0
|
|
shape (OrthoPolyLine
|
|
uid 1420,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "51000,49000,53000,55000"
|
|
pts [
|
|
"51000,49000"
|
|
"51000,55000"
|
|
"53000,55000"
|
|
]
|
|
)
|
|
start &103
|
|
end &30
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1423,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1424,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "47000,50600,52200,52000"
|
|
st "txSend"
|
|
blo "47000,51800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &22
|
|
)
|
|
*107 (Wire
|
|
uid 1437,0
|
|
shape (OrthoPolyLine
|
|
uid 1438,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "75000,53000,105000,65000"
|
|
pts [
|
|
"80250,53000"
|
|
"75000,53000"
|
|
"75000,65000"
|
|
"105000,65000"
|
|
]
|
|
)
|
|
start &81
|
|
end &34
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1441,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1442,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "101000,63600,105100,65000"
|
|
st "txFull"
|
|
blo "101000,64800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &35
|
|
)
|
|
*108 (Wire
|
|
uid 1451,0
|
|
shape (OrthoPolyLine
|
|
uid 1452,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "97750,49000,105000,49000"
|
|
pts [
|
|
"105000,49000"
|
|
"97750,49000"
|
|
]
|
|
)
|
|
start &36
|
|
end &74
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1455,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1456,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "102000,47600,105800,49000"
|
|
st "txWr"
|
|
blo "102000,48800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &37
|
|
)
|
|
]
|
|
bg "65535,65535,65535"
|
|
grid (Grid
|
|
origin "0,0"
|
|
isVisible 0
|
|
isActive 1
|
|
xSpacing 1000
|
|
xySpacing 1000
|
|
xShown 1
|
|
yShown 1
|
|
color "26368,26368,26368"
|
|
)
|
|
packageList *109 (PackageList
|
|
uid 42,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*110 (Text
|
|
uid 43,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,0,6900,1000"
|
|
st "Package List"
|
|
blo "0,800"
|
|
)
|
|
*111 (MLText
|
|
uid 44,0
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,17500,4600"
|
|
st "LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.ALL;"
|
|
tm "PackageList"
|
|
)
|
|
]
|
|
)
|
|
compDirBlock (MlTextGroup
|
|
uid 45,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*112 (Text
|
|
uid 46,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,0,30200,1000"
|
|
st "Compiler Directives"
|
|
blo "20000,800"
|
|
)
|
|
*113 (Text
|
|
uid 47,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,1000,32200,2000"
|
|
st "Pre-module directives:"
|
|
blo "20000,1800"
|
|
)
|
|
*114 (MLText
|
|
uid 48,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,2000,32100,4400"
|
|
st "`resetall
|
|
`timescale 1ns/10ps"
|
|
tm "BdCompilerDirectivesTextMgr"
|
|
)
|
|
*115 (Text
|
|
uid 49,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,4000,32800,5000"
|
|
st "Post-module directives:"
|
|
blo "20000,4800"
|
|
)
|
|
*116 (MLText
|
|
uid 50,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,0,20000,0"
|
|
tm "BdCompilerDirectivesTextMgr"
|
|
)
|
|
*117 (Text
|
|
uid 51,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,5000,32400,6000"
|
|
st "End-module directives:"
|
|
blo "20000,5800"
|
|
)
|
|
*118 (MLText
|
|
uid 52,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,6000,20000,6000"
|
|
tm "BdCompilerDirectivesTextMgr"
|
|
)
|
|
]
|
|
associable 1
|
|
)
|
|
windowSize "-8,-8,1928,1048"
|
|
viewArea "-1604,-1604,141072,75916"
|
|
cachedDiagramExtent "0,0,131800,74000"
|
|
pageSetupInfo (PageSetupInfo
|
|
ptrCmd ""
|
|
toPrinter 1
|
|
xMargin 48
|
|
yMargin 48
|
|
paperWidth 761
|
|
paperHeight 1077
|
|
unixPaperWidth 595
|
|
unixPaperHeight 842
|
|
windowsPaperWidth 761
|
|
windowsPaperHeight 1077
|
|
paperType "A4"
|
|
unixPaperName "A4 (210mm x 297mm)"
|
|
windowsPaperName "A4"
|
|
scale 67
|
|
exportedDirectories [
|
|
"$HDS_PROJECT_DIR/HTMLExport"
|
|
]
|
|
boundaryWidth 0
|
|
)
|
|
hasePageBreakOrigin 1
|
|
pageBreakOrigin "0,0"
|
|
lastUid 2312,0
|
|
defaultCommentText (CommentText
|
|
shape (Rectangle
|
|
layer 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
)
|
|
xt "0,0,15000,5000"
|
|
)
|
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text (MLText
|
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va (VaSet
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fg "65535,0,0"
|
|
)
|
|
xt "200,200,3200,1400"
|
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st "
|
|
Text
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 4600
|
|
visibleWidth 14600
|
|
)
|
|
)
|
|
defaultRequirementText (RequirementText
|
|
shape (ZoomableIcon
|
|
layer 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "59904,39936,65280"
|
|
lineColor "0,0,32768"
|
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)
|
|
xt "0,0,1500,1750"
|
|
iconName "reqTracerRequirement.bmp"
|
|
iconMaskName "reqTracerRequirement.msk"
|
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)
|
|
autoResize 1
|
|
text (MLText
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va (VaSet
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fg "0,0,32768"
|
|
font "Verdana,8,0"
|
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)
|
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xt "450,2150,1450,3150"
|
|
st "
|
|
Text
|
|
"
|
|
tm "RequirementText"
|
|
wrapOption 3
|
|
visibleHeight 1350
|
|
visibleWidth 1100
|
|
)
|
|
)
|
|
defaultPanel (Panel
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "32768,0,0"
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
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|
ps "TopLeftStrategy"
|
|
text (Text
|
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va (VaSet
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font "Verdana,10,1"
|
|
)
|
|
xt "1000,1000,4400,2200"
|
|
st "Panel0"
|
|
blo "1000,2000"
|
|
tm "PanelText"
|
|
)
|
|
)
|
|
)
|
|
defaultBlk (Blk
|
|
shape (Rectangle
|
|
va (VaSet
|
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vasetType 1
|
|
fg "40000,56832,65535"
|
|
)
|
|
xt "0,0,8000,10000"
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)
|
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ttg (MlTextGroup
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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textVec [
|
|
*119 (Text
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va (VaSet
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)
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xt "2450,3500,5550,4500"
|
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st "<library>"
|
|
blo "2450,4300"
|
|
tm "BdLibraryNameMgr"
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)
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*120 (Text
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va (VaSet
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)
|
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xt "2450,4500,5150,5500"
|
|
st "<block>"
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|
blo "2450,5300"
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tm "BlkNameMgr"
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)
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*121 (Text
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va (VaSet
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)
|
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xt "2450,5500,3050,6500"
|
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st "I0"
|
|
blo "2450,6300"
|
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tm "InstanceNameMgr"
|
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)
|
|
]
|
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)
|
|
ga (GenericAssociation
|
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ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
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text (MLText
|
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va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "2450,13500,2450,13500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
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)
|
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)
|
|
defaultMWComponent (MWC
|
|
shape (Rectangle
|
|
va (VaSet
|
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vasetType 1
|
|
fg "0,65535,0"
|
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)
|
|
xt "0,0,8000,10000"
|
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)
|
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ttg (MlTextGroup
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ps "CenterOffsetStrategy"
|
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stg "VerticalLayoutStrategy"
|
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textVec [
|
|
*122 (Text
|
|
va (VaSet
|
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)
|
|
xt "1000,3500,3300,4500"
|
|
st "Library"
|
|
blo "1000,4300"
|
|
)
|
|
*123 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1000,4500,7000,5500"
|
|
st "MWComponent"
|
|
blo "1000,5300"
|
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)
|
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*124 (Text
|
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va (VaSet
|
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)
|
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xt "1000,5500,1600,6500"
|
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st "I0"
|
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blo "1000,6300"
|
|
tm "InstanceNameMgr"
|
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)
|
|
]
|
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)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
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isHidden 1
|
|
)
|
|
xt "-6000,1500,-6000,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
prms (Property
|
|
pclass "params"
|
|
pname "params"
|
|
ptn "String"
|
|
)
|
|
visOptions (mwParamsVisibilityOptions
|
|
)
|
|
)
|
|
defaultSaComponent (SaComponent
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,8000,10000"
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)
|
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ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
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textVec [
|
|
*125 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1250,3500,3550,4500"
|
|
st "Library"
|
|
blo "1250,4300"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*126 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1250,4500,6750,5500"
|
|
st "SaComponent"
|
|
blo "1250,5300"
|
|
tm "CptNameMgr"
|
|
)
|
|
*127 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1250,5500,1850,6500"
|
|
st "I0"
|
|
blo "1250,6300"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-5750,1500,-5750,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
defaultVhdlComponent (VhdlComponent
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*128 (Text
|
|
va (VaSet
|
|
)
|
|
xt "950,3500,3250,4500"
|
|
st "Library"
|
|
blo "950,4300"
|
|
)
|
|
*129 (Text
|
|
va (VaSet
|
|
)
|
|
xt "950,4500,7050,5500"
|
|
st "VhdlComponent"
|
|
blo "950,5300"
|
|
)
|
|
*130 (Text
|
|
va (VaSet
|
|
)
|
|
xt "950,5500,1550,6500"
|
|
st "I0"
|
|
blo "950,6300"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-6050,1500,-6050,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
entityPath ""
|
|
archName ""
|
|
archPath ""
|
|
)
|
|
defaultVerilogComponent (VerilogComponent
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "-50,0,8050,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*131 (Text
|
|
va (VaSet
|
|
)
|
|
xt "450,3500,2750,4500"
|
|
st "Library"
|
|
blo "450,4300"
|
|
)
|
|
*132 (Text
|
|
va (VaSet
|
|
)
|
|
xt "450,4500,7550,5500"
|
|
st "VerilogComponent"
|
|
blo "450,5300"
|
|
)
|
|
*133 (Text
|
|
va (VaSet
|
|
)
|
|
xt "450,5500,1050,6500"
|
|
st "I0"
|
|
blo "450,6300"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-6550,1500,-6550,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
entityPath ""
|
|
)
|
|
defaultHdlText (HdlText
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,32768"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*134 (Text
|
|
va (VaSet
|
|
)
|
|
xt "3400,4000,4600,5000"
|
|
st "eb1"
|
|
blo "3400,4800"
|
|
tm "HdlTextNameMgr"
|
|
)
|
|
*135 (Text
|
|
va (VaSet
|
|
)
|
|
xt "3400,5000,3800,6000"
|
|
st "1"
|
|
blo "3400,5800"
|
|
tm "HdlTextNumberMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultEmbeddedText (EmbeddedText
|
|
commentText (CommentText
|
|
ps "CenterOffsetStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
)
|
|
xt "0,0,18000,5000"
|
|
)
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "200,200,3200,1400"
|
|
st "
|
|
Text
|
|
"
|
|
tm "HdlTextMgr"
|
|
wrapOption 3
|
|
visibleHeight 4600
|
|
visibleWidth 17600
|
|
)
|
|
)
|
|
)
|
|
defaultGlobalConnector (GlobalConnector
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,0"
|
|
)
|
|
xt "-1000,-1000,1000,1000"
|
|
radius 1000
|
|
)
|
|
name (Text
|
|
va (VaSet
|
|
)
|
|
xt "-300,-500,300,500"
|
|
st "G"
|
|
blo "-300,300"
|
|
)
|
|
)
|
|
defaultRipper (Ripper
|
|
ps "OnConnectorStrategy"
|
|
shape (Line2D
|
|
pts [
|
|
"0,0"
|
|
"1000,1000"
|
|
]
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "0,0,1000,1000"
|
|
)
|
|
)
|
|
defaultBdJunction (BdJunction
|
|
ps "OnConnectorStrategy"
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "-400,-400,400,400"
|
|
radius 400
|
|
)
|
|
)
|
|
defaultPortIoIn (PortIoIn
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "-2000,-375,-500,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "-500,0,0,0"
|
|
pts [
|
|
"-500,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "-1375,-1000,-1375,-1000"
|
|
ju 2
|
|
blo "-1375,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoOut (PortIoOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "625,-1000,625,-1000"
|
|
blo "625,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoInOut (PortIoInOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoBuffer (PortIoBuffer
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultSignal (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,2600,1400"
|
|
st "sig0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBus (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,3900,1400"
|
|
st "dbus0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineStyle 3
|
|
lineWidth 1
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,2600,1000"
|
|
st "bundle0"
|
|
blo "0,800"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,1500,2200"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,50000"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,0,5000,1200"
|
|
st "Auto list"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,9600,2200"
|
|
st "User defined list"
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,18500,100"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*136 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*137 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,11000,100"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*138 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*139 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,5100,7000,6100"
|
|
st "Declarations"
|
|
blo "0,5900"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,6100,3400,7100"
|
|
st "Ports:"
|
|
blo "0,6900"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,5100,4800,6100"
|
|
st "Pre User:"
|
|
blo "0,5900"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,5100,0,5100"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,15100,9000,16100"
|
|
st "Diagram Signals:"
|
|
blo "0,15900"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,5100,6000,6100"
|
|
st "Post User:"
|
|
blo "0,5900"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,5100,0,5100"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
ordering 1
|
|
suid 28,0
|
|
usingSuid 1
|
|
emptyRow *140 (LEmptyRow
|
|
)
|
|
uid 1151,0
|
|
optionalChildren [
|
|
*141 (RefLabelRowHdr
|
|
)
|
|
*142 (TitleRowHdr
|
|
)
|
|
*143 (FilterRowHdr
|
|
)
|
|
*144 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*145 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*146 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*147 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*148 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*149 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*150 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*151 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*152 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*153 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 1,0
|
|
)
|
|
)
|
|
uid 1112,0
|
|
)
|
|
*154 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 4,0
|
|
)
|
|
)
|
|
uid 1118,0
|
|
)
|
|
*155 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "RxD"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 5,0
|
|
)
|
|
)
|
|
uid 1120,0
|
|
)
|
|
*156 (LeafLogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "TxD"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 7,0
|
|
)
|
|
)
|
|
uid 1124,0
|
|
)
|
|
*157 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "txFifoEmpty"
|
|
t "std_ulogic"
|
|
o 14
|
|
suid 16,0
|
|
)
|
|
)
|
|
uid 1142,0
|
|
)
|
|
*158 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "txBusy"
|
|
t "std_ulogic"
|
|
o 16
|
|
suid 18,0
|
|
)
|
|
)
|
|
uid 1146,0
|
|
)
|
|
*159 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "txSend"
|
|
t "std_ulogic"
|
|
o 11
|
|
suid 19,0
|
|
)
|
|
)
|
|
uid 1148,0
|
|
)
|
|
*160 (LeafLogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "rxEmpty"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 20,0
|
|
)
|
|
)
|
|
uid 1367,0
|
|
)
|
|
*161 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "rxRd"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 21,0
|
|
)
|
|
)
|
|
uid 1369,0
|
|
)
|
|
*162 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "rxWord"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 12
|
|
suid 22,0
|
|
)
|
|
)
|
|
uid 1404,0
|
|
)
|
|
*163 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "txWord"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 15
|
|
suid 23,0
|
|
)
|
|
)
|
|
uid 1406,0
|
|
)
|
|
*164 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "rxWordValid"
|
|
t "std_ulogic"
|
|
o 13
|
|
suid 24,0
|
|
)
|
|
)
|
|
uid 1408,0
|
|
)
|
|
*165 (LeafLogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "txFull"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 25,0
|
|
)
|
|
)
|
|
uid 1428,0
|
|
)
|
|
*166 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "txWr"
|
|
t "std_ulogic"
|
|
o 10
|
|
suid 26,0
|
|
)
|
|
)
|
|
uid 1430,0
|
|
)
|
|
*167 (LeafLogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "rxData"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 7
|
|
suid 27,0
|
|
)
|
|
)
|
|
uid 1467,0
|
|
)
|
|
*168 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "txData"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 8
|
|
suid 28,0
|
|
)
|
|
)
|
|
uid 1477,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 1164,0
|
|
optionalChildren [
|
|
*169 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *170 (MRCItem
|
|
litem &140
|
|
pos 16
|
|
dimension 20
|
|
)
|
|
uid 1166,0
|
|
optionalChildren [
|
|
*171 (MRCItem
|
|
litem &141
|
|
pos 0
|
|
dimension 20
|
|
uid 1167,0
|
|
)
|
|
*172 (MRCItem
|
|
litem &142
|
|
pos 1
|
|
dimension 23
|
|
uid 1168,0
|
|
)
|
|
*173 (MRCItem
|
|
litem &143
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 1169,0
|
|
)
|
|
*174 (MRCItem
|
|
litem &153
|
|
pos 0
|
|
dimension 20
|
|
uid 1113,0
|
|
)
|
|
*175 (MRCItem
|
|
litem &154
|
|
pos 2
|
|
dimension 20
|
|
uid 1119,0
|
|
)
|
|
*176 (MRCItem
|
|
litem &155
|
|
pos 3
|
|
dimension 20
|
|
uid 1121,0
|
|
)
|
|
*177 (MRCItem
|
|
litem &156
|
|
pos 5
|
|
dimension 20
|
|
uid 1125,0
|
|
)
|
|
*178 (MRCItem
|
|
litem &157
|
|
pos 10
|
|
dimension 20
|
|
uid 1143,0
|
|
)
|
|
*179 (MRCItem
|
|
litem &158
|
|
pos 11
|
|
dimension 20
|
|
uid 1147,0
|
|
)
|
|
*180 (MRCItem
|
|
litem &159
|
|
pos 12
|
|
dimension 20
|
|
uid 1149,0
|
|
)
|
|
*181 (MRCItem
|
|
litem &160
|
|
pos 4
|
|
dimension 20
|
|
uid 1366,0
|
|
)
|
|
*182 (MRCItem
|
|
litem &161
|
|
pos 1
|
|
dimension 20
|
|
uid 1368,0
|
|
)
|
|
*183 (MRCItem
|
|
litem &162
|
|
pos 13
|
|
dimension 20
|
|
uid 1405,0
|
|
)
|
|
*184 (MRCItem
|
|
litem &163
|
|
pos 14
|
|
dimension 20
|
|
uid 1407,0
|
|
)
|
|
*185 (MRCItem
|
|
litem &164
|
|
pos 15
|
|
dimension 20
|
|
uid 1409,0
|
|
)
|
|
*186 (MRCItem
|
|
litem &165
|
|
pos 6
|
|
dimension 20
|
|
uid 1427,0
|
|
)
|
|
*187 (MRCItem
|
|
litem &166
|
|
pos 7
|
|
dimension 20
|
|
uid 1429,0
|
|
)
|
|
*188 (MRCItem
|
|
litem &167
|
|
pos 8
|
|
dimension 20
|
|
uid 1468,0
|
|
)
|
|
*189 (MRCItem
|
|
litem &168
|
|
pos 9
|
|
dimension 20
|
|
uid 1478,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 1170,0
|
|
optionalChildren [
|
|
*190 (MRCItem
|
|
litem &144
|
|
pos 0
|
|
dimension 20
|
|
uid 1171,0
|
|
)
|
|
*191 (MRCItem
|
|
litem &146
|
|
pos 1
|
|
dimension 50
|
|
uid 1172,0
|
|
)
|
|
*192 (MRCItem
|
|
litem &147
|
|
pos 2
|
|
dimension 100
|
|
uid 1173,0
|
|
)
|
|
*193 (MRCItem
|
|
litem &148
|
|
pos 3
|
|
dimension 50
|
|
uid 1174,0
|
|
)
|
|
*194 (MRCItem
|
|
litem &149
|
|
pos 4
|
|
dimension 100
|
|
uid 1175,0
|
|
)
|
|
*195 (MRCItem
|
|
litem &150
|
|
pos 5
|
|
dimension 100
|
|
uid 1176,0
|
|
)
|
|
*196 (MRCItem
|
|
litem &151
|
|
pos 6
|
|
dimension 50
|
|
uid 1177,0
|
|
)
|
|
*197 (MRCItem
|
|
litem &152
|
|
pos 7
|
|
dimension 80
|
|
uid 1178,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 1165,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 1150,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *198 (LEmptyRow
|
|
)
|
|
uid 1180,0
|
|
optionalChildren [
|
|
*199 (RefLabelRowHdr
|
|
)
|
|
*200 (TitleRowHdr
|
|
)
|
|
*201 (FilterRowHdr
|
|
)
|
|
*202 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*203 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*204 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*205 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*206 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*207 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*208 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*209 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*210 (LogGeneric
|
|
generic (GiElement
|
|
name "dataBitNb"
|
|
type "positive"
|
|
value "8"
|
|
)
|
|
uid 1243,0
|
|
)
|
|
*211 (LogGeneric
|
|
generic (GiElement
|
|
name "baudRateDivide"
|
|
type "positive"
|
|
value "2083"
|
|
)
|
|
uid 1247,0
|
|
)
|
|
*212 (LogGeneric
|
|
generic (GiElement
|
|
name "txFifoDepth"
|
|
type "positive"
|
|
value "8"
|
|
)
|
|
uid 2075,0
|
|
)
|
|
*213 (LogGeneric
|
|
generic (GiElement
|
|
name "rxFifoDepth"
|
|
type "positive"
|
|
value "8"
|
|
)
|
|
uid 2077,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 1192,0
|
|
optionalChildren [
|
|
*214 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *215 (MRCItem
|
|
litem &198
|
|
pos 4
|
|
dimension 20
|
|
)
|
|
uid 1194,0
|
|
optionalChildren [
|
|
*216 (MRCItem
|
|
litem &199
|
|
pos 0
|
|
dimension 20
|
|
uid 1195,0
|
|
)
|
|
*217 (MRCItem
|
|
litem &200
|
|
pos 1
|
|
dimension 23
|
|
uid 1196,0
|
|
)
|
|
*218 (MRCItem
|
|
litem &201
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 1197,0
|
|
)
|
|
*219 (MRCItem
|
|
litem &210
|
|
pos 1
|
|
dimension 20
|
|
uid 1242,0
|
|
)
|
|
*220 (MRCItem
|
|
litem &211
|
|
pos 0
|
|
dimension 20
|
|
uid 1246,0
|
|
)
|
|
*221 (MRCItem
|
|
litem &212
|
|
pos 2
|
|
dimension 20
|
|
uid 2074,0
|
|
)
|
|
*222 (MRCItem
|
|
litem &213
|
|
pos 3
|
|
dimension 20
|
|
uid 2076,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 1198,0
|
|
optionalChildren [
|
|
*223 (MRCItem
|
|
litem &202
|
|
pos 0
|
|
dimension 20
|
|
uid 1199,0
|
|
)
|
|
*224 (MRCItem
|
|
litem &204
|
|
pos 1
|
|
dimension 50
|
|
uid 1200,0
|
|
)
|
|
*225 (MRCItem
|
|
litem &205
|
|
pos 2
|
|
dimension 100
|
|
uid 1201,0
|
|
)
|
|
*226 (MRCItem
|
|
litem &206
|
|
pos 3
|
|
dimension 100
|
|
uid 1202,0
|
|
)
|
|
*227 (MRCItem
|
|
litem &207
|
|
pos 4
|
|
dimension 50
|
|
uid 1203,0
|
|
)
|
|
*228 (MRCItem
|
|
litem &208
|
|
pos 5
|
|
dimension 50
|
|
uid 1204,0
|
|
)
|
|
*229 (MRCItem
|
|
litem &209
|
|
pos 6
|
|
dimension 80
|
|
uid 1205,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 1193,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 1179,0
|
|
type 1
|
|
)
|
|
activeModelName "BlockDiag"
|
|
)
|