27 lines
959 B
VHDL
27 lines
959 B
VHDL
ARCHITECTURE RTL OF registerFile IS
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subtype registerType is signed(registersIn'range);
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type registerArrayType is array (0 to 2**registerAddressBitNb-1) of registerType;
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signal registerArray : registerArrayType;
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BEGIN
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------------------------------------------------------------------------------
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-- write to registers
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updateRegister: process(reset, clock)
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begin
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if reset = '1' then
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registerArray <= (others => (others => '0'));
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elsif rising_edge(clock) then
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if regWrite = '1' then
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registerArray(to_integer(addrA)) <= registersIn;
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end if;
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end if;
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end process updateRegister;
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------------------------------------------------------------------------------
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-- read from registers
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opA <= registerArray(to_integer(addrA));
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opB <= registerArray(to_integer(addrB));
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END ARCHITECTURE RTL;
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