SEm-Labos/06-07-08-09-SystemOnChip/SystemOnChip/hds/beamer@periph@registers/struct.bd

DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "numeric_std"
itemName "ALL"
)
]
instances [
(Instance
name "I19"
duLibraryName "Beamer"
duName "blockRAMControl"
elements [
]
mwi 0
uid 11639,0
)
(Instance
name "I31"
duLibraryName "Beamer"
duName "blockRAMControl"
elements [
]
mwi 0
uid 11714,0
)
(Instance
name "I2"
duLibraryName "Beamer"
duName "periphAddressDecoder"
elements [
(GiElement
name "addressBitNb"
type "positive"
value "addressBitNb"
)
]
mwi 0
uid 17547,0
)
(Instance
name "I4"
duLibraryName "Beamer"
duName "periphControlReg"
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "patternSizeBitNb"
type "positive"
value "patternAddressBitNb"
)
]
mwi 0
uid 18007,0
)
(Instance
name "I20"
duLibraryName "Beamer"
duName "blockRAMAddressCounter"
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
]
mwi 0
uid 18179,0
)
(Instance
name "I30"
duLibraryName "Beamer"
duName "blockRAMAddressCounter"
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
]
mwi 0
uid 18212,0
)
(Instance
name "I3"
duLibraryName "Beamer"
duName "periphSpeedReg"
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "updatePeriodBitNb"
type "positive"
value "updatePeriodBitNb"
)
]
mwi 0
uid 18249,0
)
(Instance
name "I18"
duLibraryName "Beamer"
duName "blockRAM"
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "initFileSpec"
type "string"
value "\"$SIMULATION_DIR\\ramYInit.txt\""
)
]
mwi 0
uid 19180,0
)
(Instance
name "I17"
duLibraryName "Beamer"
duName "blockRAM"
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "initFileSpec"
type "string"
value "\"$SIMULATION_DIR\\ramXInit.txt\""
)
]
mwi 0
uid 19217,0
)
]
embeddedInstances [
(EmbeddedInstance
name "eb3"
number "3"
)
(EmbeddedInstance
name "eb8"
number "8"
)
(EmbeddedInstance
name "eb9"
number "9"
)
(EmbeddedInstance
name "eb10"
number "10"
)
]
libraryRefs [
"ieee"
]
)
version "32.1"
appVersion "2019.2 (Build 5)"
noEmbeddedEditors 1
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable " "
value " "
)
(vvPair
variable "HDLDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds\\beamer@periph@registers\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds\\beamer@periph@registers\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "asm_file"
value "beamer.asm"
)
(vvPair
variable "concat_file"
value "concatenated"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds\\beamer@periph@registers"
)
(vvPair
variable "d_logical"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds\\beamerPeriphRegisters"
)
(vvPair
variable "date"
value "28.04.2023"
)
(vvPair
variable "day"
value "ven."
)
(vvPair
variable "day_long"
value "vendredi"
)
(vvPair
variable "dd"
value "28"
)
(vvPair
variable "designName"
value "$DESIGN_NAME"
)
(vvPair
variable "entity_name"
value "beamerPeriphRegisters"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "f_noext"
value "struct"
)
(vvPair
variable "graphical_source_author"
value "axel.amand"
)
(vvPair
variable "graphical_source_date"
value "28.04.2023"
)
(vvPair
variable "graphical_source_group"
value "UNKNOWN"
)
(vvPair
variable "graphical_source_host"
value "WE7860"
)
(vvPair
variable "graphical_source_time"
value "15:02:17"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "WE7860"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "SystemOnChip"
)
(vvPair
variable "library_downstream_Generic_1_file"
value "U:\\SEm_curves\\Synthesis"
)
(vvPair
variable "library_downstream_ModelSim"
value "D:\\Users\\ELN_labs\\VHDL_comp"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/SystemOnChip"
)
(vvPair
variable "library_downstream_SpyGlass"
value "U:\\SEm_curves\\Synthesis"
)
(vvPair
variable "mm"
value "04"
)
(vvPair
variable "module_name"
value "beamerPeriphRegisters"
)
(vvPair
variable "month"
value "avr."
)
(vvPair
variable "month_long"
value "avril"
)
(vvPair
variable "p"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds\\beamer@periph@registers\\struct.bd"
)
(vvPair
variable "p_logical"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds\\beamerPeriphRegisters\\struct.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "hds"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_ADMS"
value "<TBD>"
)
(vvPair
variable "task_AsmPath"
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_HDSPath"
value "$HDS_HOME"
)
(vvPair
variable "task_ISEBinPath"
value "$ISE_HOME"
)
(vvPair
variable "task_ISEPath"
value "$ISE_WORK_DIR"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "$MODELSIM_HOME/modeltech/bin"
)
(vvPair
variable "task_NC"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "struct"
)
(vvPair
variable "this_file_logical"
value "struct"
)
(vvPair
variable "time"
value "15:02:17"
)
(vvPair
variable "unit"
value "beamerPeriphRegisters"
)
(vvPair
variable "user"
value "axel.amand"
)
(vvPair
variable "version"
value "2019.2 (Build 5)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2023"
)
(vvPair
variable "yy"
value "23"
)
]
)
LanguageMgr "Vhdl2008LangMgr"
uid 41,0
optionalChildren [
*1 (Grouping
uid 9,0
optionalChildren [
*2 (CommentText
uid 11,0
shape (Rectangle
uid 12,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "110000,197000,127000,198000"
)
oxt "18000,70000,35000,71000"
text (MLText
uid 13,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "110200,197500,110200,197500"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
*3 (CommentText
uid 14,0
shape (Rectangle
uid 15,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "127000,193000,131000,194000"
)
oxt "35000,66000,39000,67000"
text (MLText
uid 16,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "127200,193500,127200,193500"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*4 (CommentText
uid 17,0
shape (Rectangle
uid 18,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "110000,195000,127000,196000"
)
oxt "18000,68000,35000,69000"
text (MLText
uid 19,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "110200,195500,110200,195500"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
*5 (CommentText
uid 20,0
shape (Rectangle
uid 21,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "106000,195000,110000,196000"
)
oxt "14000,68000,18000,69000"
text (MLText
uid 22,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "106200,195500,106200,195500"
st "
Title:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*6 (CommentText
uid 23,0
shape (Rectangle
uid 24,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "127000,194000,147000,198000"
)
oxt "35000,67000,55000,71000"
text (MLText
uid 25,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "127200,194200,141300,195400"
st "
<enter comments here>
"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
)
*7 (CommentText
uid 26,0
shape (Rectangle
uid 27,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "131000,193000,147000,194000"
)
oxt "39000,66000,55000,67000"
text (MLText
uid 28,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "131200,193500,131200,193500"
st "
<enter project name here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
)
*8 (CommentText
uid 29,0
shape (Rectangle
uid 30,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "106000,193000,127000,195000"
)
oxt "14000,66000,35000,68000"
text (MLText
uid 31,0
va (VaSet
fg "32768,0,0"
)
xt "111350,193400,121650,194600"
st "
<company name>
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
)
*9 (CommentText
uid 32,0
shape (Rectangle
uid 33,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "106000,196000,110000,197000"
)
oxt "14000,69000,18000,70000"
text (MLText
uid 34,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "106200,196500,106200,196500"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*10 (CommentText
uid 35,0
shape (Rectangle
uid 36,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "106000,197000,110000,198000"
)
oxt "14000,70000,18000,71000"
text (MLText
uid 37,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "106200,197500,106200,197500"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*11 (CommentText
uid 38,0
shape (Rectangle
uid 39,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "110000,196000,127000,197000"
)
oxt "18000,69000,35000,70000"
text (MLText
uid 40,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "110200,196500,110200,196500"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
]
shape (GroupingShape
uid 10,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "106000,193000,147000,198000"
)
oxt "14000,66000,55000,71000"
)
*12 (PortIoIn
uid 67,0
shape (CompositeShape
uid 68,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 69,0
sl 0
ro 270
xt "72000,53625,73500,54375"
)
(Line
uid 70,0
sl 0
ro 270
xt "73500,54000,74000,54000"
pts [
"73500,54000"
"74000,54000"
]
)
]
)
tg (WTG
uid 71,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 72,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "67200,53300,71000,54700"
st "clock"
ju 2
blo "71000,54500"
tm "WireNameMgr"
)
)
)
*13 (Net
uid 79,0
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2,0
)
declText (MLText
uid 80,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,102200,13200,103200"
st "clock          : std_ulogic"
)
)
*14 (Net
uid 163,0
decl (Decl
n "reset"
t "std_ulogic"
o 10
suid 7,0
)
declText (MLText
uid 164,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,108600,13200,109600"
st "reset          : std_ulogic"
)
)
*15 (Net
uid 436,0
decl (Decl
n "newPolynom"
t "std_ulogic"
o 11
suid 10,0
)
declText (MLText
uid 437,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,109400,14900,110400"
st "newPolynom     : std_ulogic"
)
)
*16 (Net
uid 990,0
decl (Decl
n "selControl"
t "std_ulogic"
o 24
suid 33,0
)
declText (MLText
uid 991,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,123400,16900,124400"
st "SIGNAL selControl     : std_ulogic"
)
)
*17 (Net
uid 1055,0
decl (Decl
n "selSpeed"
t "std_ulogic"
o 25
suid 35,0
)
declText (MLText
uid 1056,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,124200,17100,125200"
st "SIGNAL selSpeed       : std_ulogic"
)
)
*18 (Net
uid 1063,0
decl (Decl
n "selX"
t "std_ulogic"
o 26
suid 36,0
)
declText (MLText
uid 1064,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,125000,16300,126000"
st "SIGNAL selX           : std_ulogic"
)
)
*19 (Net
uid 1071,0
decl (Decl
n "selY"
t "std_ulogic"
o 27
suid 37,0
)
declText (MLText
uid 1072,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,125800,16300,126800"
st "SIGNAL selY           : std_ulogic"
)
)
*20 (Net
uid 1348,0
decl (Decl
n "run"
t "std_ulogic"
o 7
suid 38,0
)
declText (MLText
uid 1349,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,106200,13100,107200"
st "run            : std_ulogic"
)
)
*21 (Net
uid 1356,0
decl (Decl
n "updatePattern"
t "std_ulogic"
o 28
suid 39,0
)
declText (MLText
uid 1357,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,126600,17700,127600"
st "SIGNAL updatePattern  : std_ulogic"
)
)
*22 (Net
uid 1470,0
decl (Decl
n "patternSize"
t "unsigned"
b "(patternAddressBitNb-1 DOWNTO 0)"
o 23
suid 40,0
)
declText (MLText
uid 1471,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,122600,31800,123600"
st "SIGNAL patternSize    : unsigned(patternAddressBitNb-1 DOWNTO 0)"
)
)
*23 (Net
uid 1589,0
decl (Decl
n "dataOut"
t "std_logic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 18
suid 41,0
)
declText (MLText
uid 1590,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,118600,30400,119600"
st "SIGNAL dataOut        : std_logic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*24 (Net
uid 1776,0
decl (Decl
n "updatePeriod"
t "unsigned"
b "(updatePeriodBitNb-1 DOWNTO 0)"
o 8
suid 42,0
)
declText (MLText
uid 1777,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,107000,28400,108000"
st "updatePeriod   : unsigned(updatePeriodBitNb-1 DOWNTO 0)"
)
)
*25 (Net
uid 2776,0
decl (Decl
n "addrX"
t "unsigned"
b "(patternAddressBitNb-1 DOWNTO 0)"
o 13
suid 44,0
)
declText (MLText
uid 2777,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,114600,31400,115600"
st "SIGNAL addrX          : unsigned(patternAddressBitNb-1 DOWNTO 0)"
)
)
*26 (Net
uid 2850,0
decl (Decl
n "cntIncrX"
t "std_ulogic"
o 15
suid 45,0
)
declText (MLText
uid 2851,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,116200,16700,117200"
st "SIGNAL cntIncrX       : std_ulogic"
)
)
*27 (Net
uid 2852,0
decl (Decl
n "memWrX"
t "std_ulogic"
o 21
suid 46,0
)
declText (MLText
uid 2853,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,121000,17800,122000"
st "SIGNAL memWrX         : std_ulogic"
)
)
*28 (Net
uid 2854,0
decl (Decl
n "memEnX"
t "std_ulogic"
o 19
suid 47,0
)
declText (MLText
uid 2855,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,119400,17700,120400"
st "SIGNAL memEnX         : std_ulogic"
)
)
*29 (Net
uid 3152,0
decl (Decl
n "memX"
t "std_ulogic_vector"
b "(signalBitNb-1 DOWNTO 0)"
o 5
suid 48,0
)
declText (MLText
uid 3153,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,104600,28500,105600"
st "memX           : std_ulogic_vector(signalBitNb-1 DOWNTO 0)"
)
)
*30 (Net
uid 3827,0
decl (Decl
n "cntIncrY"
t "std_ulogic"
o 16
suid 49,0
)
declText (MLText
uid 3828,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,117000,16700,118000"
st "SIGNAL cntIncrY       : std_ulogic"
)
)
*31 (Net
uid 3890,0
decl (Decl
n "addrY"
t "unsigned"
b "(patternAddressBitNb-1 DOWNTO 0)"
o 14
suid 50,0
)
declText (MLText
uid 3891,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,115400,31400,116400"
st "SIGNAL addrY          : unsigned(patternAddressBitNb-1 DOWNTO 0)"
)
)
*32 (Net
uid 3892,0
decl (Decl
n "memWrY"
t "std_ulogic"
o 22
suid 51,0
)
declText (MLText
uid 3893,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,121800,17800,122800"
st "SIGNAL memWrY         : std_ulogic"
)
)
*33 (Net
uid 3894,0
decl (Decl
n "memEnY"
t "std_ulogic"
o 20
suid 52,0
)
declText (MLText
uid 3895,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,120200,17700,121200"
st "SIGNAL memEnY         : std_ulogic"
)
)
*34 (Net
uid 3913,0
decl (Decl
n "memY"
t "std_ulogic_vector"
b "(signalBitNb-1 DOWNTO 0)"
o 6
suid 53,0
)
declText (MLText
uid 3914,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,105400,28500,106400"
st "memY           : std_ulogic_vector(signalBitNb-1 DOWNTO 0)"
)
)
*35 (PortIoOut
uid 4041,0
shape (CompositeShape
uid 4042,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4043,0
sl 0
ro 270
xt "143500,3625,145000,4375"
)
(Line
uid 4044,0
sl 0
ro 270
xt "143000,4000,143500,4000"
pts [
"143000,4000"
"143500,4000"
]
)
]
)
tg (WTG
uid 4045,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4046,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "146000,3300,166900,4700"
st "testOut : (1 TO testOutBitNb)"
blo "146000,4500"
tm "WireNameMgr"
)
)
)
*36 (Net
uid 4053,0
decl (Decl
n "testOut"
t "std_ulogic_vector"
b "(1 TO testOutBitNb)"
o 4
suid 54,0
)
declText (MLText
uid 4054,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,103800,25000,104800"
st "testOut        : std_ulogic_vector(1 TO testOutBitNb)"
)
)
*37 (HdlText
uid 4055,0
optionalChildren [
*38 (EmbeddedText
uid 4060,0
commentText (CommentText
uid 4061,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 4062,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "120000,3000,134000,25000"
)
oxt "0,0,18000,5000"
text (MLText
uid 4063,0
va (VaSet
)
xt "120200,3200,134200,24800"
st "
testout(1) <= '0';
testout(2) <= updatePattern;
testout(3) <= '0';
testout(4) <= newPolynom;
testout(5) <= '0';
testout(6) <= '0';
testout(7) <= '0';
testout(8) <= '0';
testout(9) <= '0';
testout(10) <= addr(1);
testout(11) <= dataIn(0);
--testout(10) <= selControl;
--testout(11) <= selSize;
testout(12) <= selSpeed;
testout(13) <= selX;
testout(14) <= selY;
testout(15) <= cntIncrX;
testout(16) <= cntIncrY;
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 22000
visibleWidth 14000
)
)
)
]
shape (Rectangle
uid 4056,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "119000,2000,135000,26000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 4057,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*39 (Text
uid 4058,0
va (VaSet
)
xt "119400,26000,122000,27200"
st "eb3"
blo "119400,27000"
tm "HdlTextNameMgr"
)
*40 (Text
uid 4059,0
va (VaSet
)
xt "119400,27000,120800,28200"
st "3"
blo "119400,28000"
tm "HdlTextNumberMgr"
)
]
)
)
*41 (Net
uid 9646,0
decl (Decl
n "interpolateLin"
t "std_ulogic"
o 9
suid 70,0
)
declText (MLText
uid 9647,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,107800,13900,108800"
st "interpolateLin : std_ulogic"
)
)
*42 (SaComponent
uid 11639,0
optionalChildren [
*43 (CptPort
uid 11603,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11604,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,133625,94750,134375"
)
tg (CPTG
uid 11605,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11606,0
va (VaSet
)
xt "88600,133400,93000,134600"
st "memWr"
ju 2
blo "93000,134400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memWr"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*44 (CptPort
uid 11607,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11608,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,129625,78000,130375"
)
tg (CPTG
uid 11609,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11610,0
va (VaSet
)
xt "79000,129400,81200,130600"
st "sel"
blo "79000,130400"
)
)
thePort (LogicalPort
decl (Decl
n "sel"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*45 (CptPort
uid 11611,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11612,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,135625,94750,136375"
)
tg (CPTG
uid 11613,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11614,0
va (VaSet
)
xt "88600,135400,93000,136600"
st "memEn"
ju 2
blo "93000,136400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memEn"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*46 (CptPort
uid 11615,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11616,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,133625,78000,134375"
)
tg (CPTG
uid 11617,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11618,0
va (VaSet
)
xt "79000,133400,83100,134600"
st "update"
blo "79000,134400"
)
)
thePort (LogicalPort
decl (Decl
n "update"
t "std_ulogic"
o 4
suid 4,0
)
)
)
*47 (CptPort
uid 11619,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11620,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,131625,78000,132375"
)
tg (CPTG
uid 11621,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11622,0
va (VaSet
)
xt "79000,131400,80800,132600"
st "wr"
blo "79000,132400"
)
)
thePort (LogicalPort
decl (Decl
n "wr"
t "std_ulogic"
o 5
suid 5,0
)
)
)
*48 (CptPort
uid 11623,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11624,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,129625,94750,130375"
)
tg (CPTG
uid 11625,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11626,0
va (VaSet
)
xt "88600,129400,93000,130600"
st "cntIncr"
ju 2
blo "93000,130400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "cntIncr"
t "std_ulogic"
o 6
suid 6,0
)
)
)
*49 (CptPort
uid 11627,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11628,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,135625,78000,136375"
)
tg (CPTG
uid 11629,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11630,0
va (VaSet
)
xt "79000,135400,85300,136600"
st "newSample"
blo "79000,136400"
)
)
thePort (LogicalPort
decl (Decl
n "newSample"
t "std_ulogic"
o 7
suid 7,0
)
)
)
*50 (CptPort
uid 11631,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11632,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,139625,78000,140375"
)
tg (CPTG
uid 11633,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11634,0
va (VaSet
)
xt "79000,139400,82400,140600"
st "clock"
blo "79000,140400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 8
suid 8,0
)
)
)
*51 (CptPort
uid 11635,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11636,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,141625,78000,142375"
)
tg (CPTG
uid 11637,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11638,0
va (VaSet
)
xt "79000,141400,82300,142600"
st "reset"
blo "79000,142400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 9
suid 9,0
)
)
)
]
shape (Rectangle
uid 11640,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "78000,126000,94000,144000"
)
oxt "32000,8000,48000,26000"
ttg (MlTextGroup
uid 11641,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*52 (Text
uid 11642,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,143800,83000,145000"
st "Beamer"
blo "78600,144800"
tm "BdLibraryNameMgr"
)
*53 (Text
uid 11643,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,145000,88300,146200"
st "blockRAMControl"
blo "78600,146000"
tm "CptNameMgr"
)
*54 (Text
uid 11644,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,146200,80900,147400"
st "I19"
blo "78600,147200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 11645,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 11646,0
text (MLText
uid 11647,0
va (VaSet
font "Verdana,8,0"
)
xt "78000,139800,78000,139800"
)
header ""
)
elements [
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*55 (SaComponent
uid 11714,0
optionalChildren [
*56 (CptPort
uid 11723,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11724,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,183625,94750,184375"
)
tg (CPTG
uid 11725,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11726,0
va (VaSet
)
xt "88600,183400,93000,184600"
st "memWr"
ju 2
blo "93000,184400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memWr"
t "std_ulogic"
o 1
)
)
)
*57 (CptPort
uid 11727,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11728,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,179625,78000,180375"
)
tg (CPTG
uid 11729,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11730,0
va (VaSet
)
xt "79000,179400,81200,180600"
st "sel"
blo "79000,180400"
)
)
thePort (LogicalPort
decl (Decl
n "sel"
t "std_ulogic"
o 2
)
)
)
*58 (CptPort
uid 11731,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11732,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,185625,94750,186375"
)
tg (CPTG
uid 11733,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11734,0
va (VaSet
)
xt "88600,185400,93000,186600"
st "memEn"
ju 2
blo "93000,186400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memEn"
t "std_ulogic"
o 3
)
)
)
*59 (CptPort
uid 11735,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11736,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,183625,78000,184375"
)
tg (CPTG
uid 11737,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11738,0
va (VaSet
)
xt "79000,183400,83100,184600"
st "update"
blo "79000,184400"
)
)
thePort (LogicalPort
decl (Decl
n "update"
t "std_ulogic"
o 4
)
)
)
*60 (CptPort
uid 11739,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11740,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,181625,78000,182375"
)
tg (CPTG
uid 11741,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11742,0
va (VaSet
)
xt "79000,181400,80800,182600"
st "wr"
blo "79000,182400"
)
)
thePort (LogicalPort
decl (Decl
n "wr"
t "std_ulogic"
o 5
)
)
)
*61 (CptPort
uid 11743,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11744,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,179625,94750,180375"
)
tg (CPTG
uid 11745,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11746,0
va (VaSet
)
xt "88600,179400,93000,180600"
st "cntIncr"
ju 2
blo "93000,180400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "cntIncr"
t "std_ulogic"
o 6
)
)
)
*62 (CptPort
uid 11747,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11748,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,185625,78000,186375"
)
tg (CPTG
uid 11749,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11750,0
va (VaSet
)
xt "79000,185400,85300,186600"
st "newSample"
blo "79000,186400"
)
)
thePort (LogicalPort
decl (Decl
n "newSample"
t "std_ulogic"
o 7
)
)
)
*63 (CptPort
uid 11751,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11752,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,189625,78000,190375"
)
tg (CPTG
uid 11753,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11754,0
va (VaSet
)
xt "79000,189400,82400,190600"
st "clock"
blo "79000,190400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 8
)
)
)
*64 (CptPort
uid 11755,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11756,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,191625,78000,192375"
)
tg (CPTG
uid 11757,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11758,0
va (VaSet
)
xt "79000,191400,82300,192600"
st "reset"
blo "79000,192400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 9
)
)
)
]
shape (Rectangle
uid 11715,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "78000,176000,94000,194000"
)
oxt "32000,8000,48000,26000"
ttg (MlTextGroup
uid 11716,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*65 (Text
uid 11717,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,193800,83000,195000"
st "Beamer"
blo "78600,194800"
tm "BdLibraryNameMgr"
)
*66 (Text
uid 11718,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,195000,88300,196200"
st "blockRAMControl"
blo "78600,196000"
tm "CptNameMgr"
)
*67 (Text
uid 11719,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,196200,80900,197400"
st "I31"
blo "78600,197200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 11720,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 11721,0
text (MLText
uid 11722,0
va (VaSet
font "Verdana,8,0"
)
xt "78000,189800,78000,189800"
)
header ""
)
elements [
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*68 (PortIoIn
uid 13128,0
shape (CompositeShape
uid 13129,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 13130,0
sl 0
ro 270
xt "20000,41625,21500,42375"
)
(Line
uid 13131,0
sl 0
ro 270
xt "21500,42000,22000,42000"
pts [
"21500,42000"
"22000,42000"
]
)
]
)
tg (WTG
uid 13132,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13133,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "15500,41500,19000,42900"
st "apbi"
ju 2
blo "19000,42700"
tm "WireNameMgr"
)
)
)
*69 (Net
uid 13140,0
decl (Decl
n "apbi"
t "apb_slv_in_type"
o 1
suid 71,0
)
declText (MLText
uid 13141,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,101400,15800,102400"
st "apbi           : apb_slv_in_type"
)
)
*70 (PortIoOut
uid 13373,0
shape (CompositeShape
uid 13374,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 13375,0
sl 0
ro 90
xt "20000,25625,21500,26375"
)
(Line
uid 13376,0
sl 0
ro 90
xt "21500,26000,22000,26000"
pts [
"22000,26000"
"21500,26000"
]
)
]
)
tg (WTG
uid 13377,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13378,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "15000,25300,19000,26700"
st "apbo"
ju 2
blo "19000,26500"
tm "WireNameMgr"
)
)
)
*71 (Net
uid 13385,0
decl (Decl
n "apbo"
t "apb_slv_out_type"
o 3
suid 72,0
)
declText (MLText
uid 13386,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,103000,16700,104000"
st "apbo           : apb_slv_out_type"
)
)
*72 (PortIoOut
uid 14845,0
shape (CompositeShape
uid 14846,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 14847,0
sl 0
ro 270
xt "134500,115625,136000,116375"
)
(Line
uid 14848,0
sl 0
ro 270
xt "134000,116000,134500,116000"
pts [
"134000,116000"
"134500,116000"
]
)
]
)
tg (WTG
uid 14849,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14850,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "137000,115300,161100,116700"
st "memY : (signalBitNb-1 DOWNTO 0)"
blo "137000,116500"
tm "WireNameMgr"
)
)
)
*73 (PortIoOut
uid 14851,0
shape (CompositeShape
uid 14852,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 14853,0
sl 0
ro 270
xt "134500,153625,136000,154375"
)
(Line
uid 14854,0
sl 0
ro 270
xt "134000,154000,134500,154000"
pts [
"134000,154000"
"134500,154000"
]
)
]
)
tg (WTG
uid 14855,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14856,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "137000,153300,161200,154700"
st "memX : (signalBitNb-1 DOWNTO 0)"
blo "137000,154500"
tm "WireNameMgr"
)
)
)
*74 (PortIoOut
uid 14857,0
shape (CompositeShape
uid 14858,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 14859,0
sl 0
ro 270
xt "109750,41625,111250,42375"
)
(Line
uid 14860,0
sl 0
ro 270
xt "109250,42000,109750,42000"
pts [
"109250,42000"
"109750,42000"
]
)
]
)
tg (WTG
uid 14861,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14862,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "112000,41300,114900,42700"
st "run"
blo "112000,42500"
tm "WireNameMgr"
)
)
)
*75 (PortIoOut
uid 14863,0
shape (CompositeShape
uid 14864,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 14865,0
sl 0
ro 270
xt "109750,69625,111250,70375"
)
(Line
uid 14866,0
sl 0
ro 270
xt "109250,70000,109750,70000"
pts [
"109250,70000"
"109750,70000"
]
)
]
)
tg (WTG
uid 14867,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14868,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "112000,69300,146500,70700"
st "updatePeriod : (updatePeriodBitNb-1 DOWNTO 0)"
blo "112000,70500"
tm "WireNameMgr"
)
)
)
*76 (PortIoOut
uid 14869,0
shape (CompositeShape
uid 14870,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 14871,0
sl 0
ro 270
xt "109500,43625,111000,44375"
)
(Line
uid 14872,0
sl 0
ro 270
xt "109000,44000,109500,44000"
pts [
"109000,44000"
"109500,44000"
]
)
]
)
tg (WTG
uid 14873,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14874,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "112000,43300,122300,44700"
st "interpolateLin"
blo "112000,44500"
tm "WireNameMgr"
)
)
)
*77 (PortIoIn
uid 16542,0
shape (CompositeShape
uid 16543,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 16544,0
sl 0
ro 270
xt "72000,55625,73500,56375"
)
(Line
uid 16545,0
sl 0
ro 270
xt "73500,56000,74000,56000"
pts [
"73500,56000"
"74000,56000"
]
)
]
)
tg (WTG
uid 16546,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16547,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "66900,55500,71000,56900"
st "reset"
ju 2
blo "71000,56700"
tm "WireNameMgr"
)
)
)
*78 (Net
uid 16705,0
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 17
suid 74,0
)
declText (MLText
uid 16706,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,117800,30600,118800"
st "SIGNAL dataIn         : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*79 (HdlText
uid 16707,0
optionalChildren [
*80 (EmbeddedText
uid 16712,0
commentText (CommentText
uid 16713,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 16714,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "30000,39000,46000,49000"
)
oxt "0,0,18000,5000"
text (MLText
uid 16715,0
va (VaSet
)
xt "30200,39200,45700,48800"
st "
dataIn <= std_ulogic_vector(apbi.pwdata);
addr <= unsigned(apbi.paddr);
write <= apbi.pwrite and apbi.psel(pindex) and apbi.penable;
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 10000
visibleWidth 16000
)
)
)
]
shape (Rectangle
uid 16708,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "30000,38000,46000,50000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 16709,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*81 (Text
uid 16710,0
va (VaSet
)
xt "30400,50000,33000,51200"
st "eb8"
blo "30400,51000"
tm "HdlTextNameMgr"
)
*82 (Text
uid 16711,0
va (VaSet
)
xt "30400,51000,31800,52200"
st "8"
blo "30400,52000"
tm "HdlTextNumberMgr"
)
]
)
)
*83 (Net
uid 16716,0
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 12
suid 75,0
)
declText (MLText
uid 16717,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,113800,28300,114800"
st "SIGNAL addr           : unsigned(addressBitNb-1 DOWNTO 0)"
)
)
*84 (HdlText
uid 17145,0
optionalChildren [
*85 (EmbeddedText
uid 17150,0
commentText (CommentText
uid 17151,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 17152,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "58000,87000,66000,93000"
)
oxt "0,0,18000,5000"
text (MLText
uid 17153,0
va (VaSet
)
xt "58200,87200,65800,92000"
st "
memDataIn <= dataIn(memDataIn'range);
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 6000
visibleWidth 8000
)
)
)
]
shape (Rectangle
uid 17146,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "58000,86000,66000,94000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 17147,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*86 (Text
uid 17148,0
va (VaSet
)
xt "58400,94000,61000,95200"
st "eb9"
blo "58400,95000"
tm "HdlTextNameMgr"
)
*87 (Text
uid 17149,0
va (VaSet
)
xt "58400,95000,59800,96200"
st "9"
blo "58400,96000"
tm "HdlTextNumberMgr"
)
]
)
)
*88 (Net
uid 17162,0
decl (Decl
n "memDataIn"
t "std_ulogic_vector"
b "(signalBitNb-1 DOWNTO 0)"
o 30
suid 77,0
)
declText (MLText
uid 17163,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,128200,32400,129200"
st "SIGNAL memDataIn      : std_ulogic_vector(signalBitNb-1 DOWNTO 0)"
)
)
*89 (Net
uid 17505,0
decl (Decl
n "write"
t "std_ulogic"
o 29
suid 78,0
)
declText (MLText
uid 17506,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,127400,16400,128400"
st "SIGNAL write          : std_ulogic"
)
)
*90 (SaComponent
uid 17547,0
optionalChildren [
*91 (CptPort
uid 17523,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17524,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46000,71625,46750,72375"
)
tg (CPTG
uid 17525,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17526,0
va (VaSet
)
xt "38400,71400,45000,72600"
st "selControl"
ju 2
blo "45000,72400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "selControl"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*92 (CptPort
uid 17527,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17528,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "29250,71625,30000,72375"
)
tg (CPTG
uid 17529,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17530,0
va (VaSet
)
xt "31000,71400,33900,72600"
st "addr"
blo "31000,72400"
)
)
thePort (LogicalPort
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*93 (CptPort
uid 17531,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17532,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46000,73625,46750,74375"
)
tg (CPTG
uid 17533,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17534,0
va (VaSet
)
xt "39700,73400,45000,74600"
st "selSpeed"
ju 2
blo "45000,74400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "selSpeed"
t "std_ulogic"
o 3
suid 4,0
)
)
)
*94 (CptPort
uid 17535,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17536,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46000,77625,46750,78375"
)
tg (CPTG
uid 17537,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17538,0
va (VaSet
)
xt "42100,77400,45000,78600"
st "selX"
ju 2
blo "45000,78400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "selX"
t "std_ulogic"
o 4
suid 5,0
)
)
)
*95 (CptPort
uid 17539,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17540,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46000,79625,46750,80375"
)
tg (CPTG
uid 17541,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17542,0
va (VaSet
)
xt "42100,79400,45000,80600"
st "selY"
ju 2
blo "45000,80400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "selY"
t "std_ulogic"
o 5
suid 6,0
)
)
)
*96 (CptPort
uid 17543,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17544,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46000,81625,46750,82375"
)
tg (CPTG
uid 17545,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17546,0
va (VaSet
)
xt "42100,81400,45000,82600"
st "selZ"
ju 2
blo "45000,82400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "selZ"
t "std_ulogic"
o 6
suid 7,0
)
)
)
]
shape (Rectangle
uid 17548,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "30000,68000,46000,86000"
)
oxt "34000,9000,50000,27000"
ttg (MlTextGroup
uid 17549,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*97 (Text
uid 17550,0
va (VaSet
font "Verdana,9,1"
)
xt "30600,85800,35000,87000"
st "Beamer"
blo "30600,86800"
tm "BdLibraryNameMgr"
)
*98 (Text
uid 17551,0
va (VaSet
font "Verdana,9,1"
)
xt "30600,87000,43500,88200"
st "periphAddressDecoder"
blo "30600,88000"
tm "CptNameMgr"
)
*99 (Text
uid 17552,0
va (VaSet
font "Verdana,9,1"
)
xt "30600,88200,32300,89400"
st "I2"
blo "30600,89200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 17553,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 17554,0
text (MLText
uid 17555,0
va (VaSet
font "Verdana,8,0"
)
xt "30000,89600,50000,90600"
st "addressBitNb = addressBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "addressBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*100 (HdlText
uid 17860,0
optionalChildren [
*101 (EmbeddedText
uid 17865,0
commentText (CommentText
uid 17866,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 17867,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "30000,23000,46000,29000"
)
oxt "0,0,18000,5000"
text (MLText
uid 17868,0
va (VaSet
)
xt "30200,23200,44700,29200"
st "
apbo.prdata <= dataOut;

apbo.pindex <= pindex;

apbo.pconfig <= (
  0 => ahb_device_reg ( 16#ff#, 16#3ff#, 0, 1, 7),
  1 => apb_iobar(paddr, pmask)
);

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 6000
visibleWidth 16000
)
)
)
]
shape (Rectangle
uid 17861,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "30000,22000,46000,30000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 17862,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*102 (Text
uid 17863,0
va (VaSet
)
xt "30400,30000,33700,31200"
st "eb10"
blo "30400,31000"
tm "HdlTextNameMgr"
)
*103 (Text
uid 17864,0
va (VaSet
)
xt "30400,31000,32500,32200"
st "10"
blo "30400,32000"
tm "HdlTextNumberMgr"
)
]
)
)
*104 (SaComponent
uid 18007,0
optionalChildren [
*105 (CptPort
uid 17967,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17968,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,41625,94750,42375"
)
tg (CPTG
uid 17969,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17970,0
va (VaSet
)
xt "90700,41400,93000,42600"
st "run"
ju 2
blo "93000,42400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "run"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*106 (CptPort
uid 17971,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17972,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,41625,78000,42375"
)
tg (CPTG
uid 17973,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17974,0
va (VaSet
)
xt "79000,41400,83000,42600"
st "dataIn"
blo "79000,42400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*107 (CptPort
uid 17975,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17976,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,47625,94750,48375"
)
tg (CPTG
uid 17977,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17978,0
va (VaSet
)
xt "84500,47400,93000,48600"
st "updatePattern"
ju 2
blo "93000,48400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "updatePattern"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*108 (CptPort
uid 17979,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17980,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,43625,78000,44375"
)
tg (CPTG
uid 17981,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17982,0
va (VaSet
)
xt "79000,43400,83800,44600"
st "dataOut"
blo "79000,44400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_logic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 4
suid 4,0
)
)
)
*109 (CptPort
uid 17983,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17984,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,47625,78000,48375"
)
tg (CPTG
uid 17985,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17986,0
va (VaSet
)
xt "79000,47400,82100,48600"
st "write"
blo "79000,48400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 5
suid 5,0
)
)
)
*110 (CptPort
uid 17987,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17988,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,49625,78000,50375"
)
tg (CPTG
uid 17989,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17990,0
va (VaSet
)
xt "79000,49400,80900,50600"
st "en"
blo "79000,50400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 6
suid 6,0
)
)
)
*111 (CptPort
uid 17991,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17992,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,53625,78000,54375"
)
tg (CPTG
uid 17993,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17994,0
va (VaSet
)
xt "79000,53400,82400,54600"
st "clock"
blo "79000,54400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 7
suid 7,0
)
)
)
*112 (CptPort
uid 17995,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17996,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,55625,78000,56375"
)
tg (CPTG
uid 17997,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17998,0
va (VaSet
)
xt "79000,55400,82300,56600"
st "reset"
blo "79000,56400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 8
suid 8,0
)
)
)
*113 (CptPort
uid 17999,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18000,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,43625,94750,44375"
)
tg (CPTG
uid 18001,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18002,0
va (VaSet
)
xt "83100,43400,93000,44600"
st "interpolateLinear"
ju 2
blo "93000,44400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "interpolateLinear"
t "std_ulogic"
o 9
suid 9,0
)
)
)
*114 (CptPort
uid 18003,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18004,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,49625,94750,50375"
)
tg (CPTG
uid 18005,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18006,0
va (VaSet
)
xt "85900,49400,93000,50600"
st "patternSize"
ju 2
blo "93000,50400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "patternSize"
t "unsigned"
b "(patternSizeBitNb-1 downto 0)"
o 10
suid 2011,0
)
)
)
]
shape (Rectangle
uid 18008,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "78000,38000,94000,58000"
)
oxt "38000,9000,54000,29000"
ttg (MlTextGroup
uid 18009,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*115 (Text
uid 18010,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,57800,83000,59000"
st "Beamer"
blo "78600,58800"
tm "BdLibraryNameMgr"
)
*116 (Text
uid 18011,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,59000,88400,60200"
st "periphControlReg"
blo "78600,60000"
tm "CptNameMgr"
)
*117 (Text
uid 18012,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,60200,80300,61400"
st "I4"
blo "78600,61200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 18013,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 18014,0
text (MLText
uid 18015,0
va (VaSet
font "Verdana,8,0"
)
xt "78000,61600,102300,63600"
st "dataBitNb        = dataBitNb              ( positive )  
patternSizeBitNb = patternAddressBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "patternSizeBitNb"
type "positive"
value "patternAddressBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*118 (SaComponent
uid 18179,0
optionalChildren [
*119 (CptPort
uid 18155,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18156,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,109625,78000,110375"
)
tg (CPTG
uid 18157,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18158,0
va (VaSet
)
xt "79000,109400,80900,110600"
st "en"
blo "79000,110400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*120 (CptPort
uid 18159,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18160,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,113625,78000,114375"
)
tg (CPTG
uid 18161,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18162,0
va (VaSet
)
xt "79000,113400,82400,114600"
st "clock"
blo "79000,114400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*121 (CptPort
uid 18163,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18164,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,115625,78000,116375"
)
tg (CPTG
uid 18165,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18166,0
va (VaSet
)
xt "79000,115400,82300,116600"
st "reset"
blo "79000,116400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*122 (CptPort
uid 18167,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18168,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,107625,78000,108375"
)
tg (CPTG
uid 18169,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18170,0
va (VaSet
)
xt "79000,107400,85500,108600"
st "updateMem"
blo "79000,108400"
)
)
thePort (LogicalPort
decl (Decl
n "updateMem"
t "std_ulogic"
o 4
suid 4,0
)
)
)
*123 (CptPort
uid 18171,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18172,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,105625,94750,106375"
)
tg (CPTG
uid 18173,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18174,0
va (VaSet
)
xt "90100,105400,93000,106600"
st "addr"
ju 2
blo "93000,106400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 5
suid 5,0
)
)
)
*124 (CptPort
uid 18175,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18176,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,105625,78000,106375"
)
tg (CPTG
uid 18177,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18178,0
va (VaSet
)
xt "79000,105400,86100,106600"
st "patternSize"
blo "79000,106400"
)
)
thePort (LogicalPort
decl (Decl
n "patternSize"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 6
suid 6,0
)
)
)
]
shape (Rectangle
uid 18180,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "78000,102000,94000,118000"
)
oxt "38000,13000,54000,29000"
ttg (MlTextGroup
uid 18181,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*125 (Text
uid 18182,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,117800,83000,119000"
st "Beamer"
blo "78600,118800"
tm "BdLibraryNameMgr"
)
*126 (Text
uid 18183,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,119000,93200,120200"
st "blockRAMAddressCounter"
blo "78600,120000"
tm "CptNameMgr"
)
*127 (Text
uid 18184,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,120200,80900,121400"
st "I20"
blo "78600,121200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 18185,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 18186,0
text (MLText
uid 18187,0
va (VaSet
font "Verdana,8,0"
)
xt "78000,121600,100900,122600"
st "addressBitNb = patternAddressBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*128 (SaComponent
uid 18212,0
optionalChildren [
*129 (CptPort
uid 18188,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18189,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,159625,78000,160375"
)
tg (CPTG
uid 18190,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18191,0
va (VaSet
)
xt "79000,159400,80900,160600"
st "en"
blo "79000,160400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*130 (CptPort
uid 18192,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18193,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,163625,78000,164375"
)
tg (CPTG
uid 18194,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18195,0
va (VaSet
)
xt "79000,163400,82400,164600"
st "clock"
blo "79000,164400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*131 (CptPort
uid 18196,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18197,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,165625,78000,166375"
)
tg (CPTG
uid 18198,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18199,0
va (VaSet
)
xt "79000,165400,82300,166600"
st "reset"
blo "79000,166400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*132 (CptPort
uid 18200,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18201,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,157625,78000,158375"
)
tg (CPTG
uid 18202,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18203,0
va (VaSet
)
xt "79000,157400,85500,158600"
st "updateMem"
blo "79000,158400"
)
)
thePort (LogicalPort
decl (Decl
n "updateMem"
t "std_ulogic"
o 4
suid 4,0
)
)
)
*133 (CptPort
uid 18204,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18205,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,155625,94750,156375"
)
tg (CPTG
uid 18206,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18207,0
va (VaSet
)
xt "90100,155400,93000,156600"
st "addr"
ju 2
blo "93000,156400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 5
suid 5,0
)
)
)
*134 (CptPort
uid 18208,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18209,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,155625,78000,156375"
)
tg (CPTG
uid 18210,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18211,0
va (VaSet
)
xt "79000,155400,86100,156600"
st "patternSize"
blo "79000,156400"
)
)
thePort (LogicalPort
decl (Decl
n "patternSize"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 6
suid 6,0
)
)
)
]
shape (Rectangle
uid 18213,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "78000,152000,94000,168000"
)
oxt "38000,13000,54000,29000"
ttg (MlTextGroup
uid 18214,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*135 (Text
uid 18215,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,167800,83000,169000"
st "Beamer"
blo "78600,168800"
tm "BdLibraryNameMgr"
)
*136 (Text
uid 18216,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,169000,93200,170200"
st "blockRAMAddressCounter"
blo "78600,170000"
tm "CptNameMgr"
)
*137 (Text
uid 18217,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,170200,80900,171400"
st "I30"
blo "78600,171200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 18218,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 18219,0
text (MLText
uid 18220,0
va (VaSet
font "Verdana,8,0"
)
xt "78000,171600,100900,172600"
st "addressBitNb = patternAddressBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*138 (SaComponent
uid 18249,0
optionalChildren [
*139 (CptPort
uid 18221,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18222,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,69625,94750,70375"
)
tg (CPTG
uid 18223,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18224,0
va (VaSet
)
xt "85000,69400,93000,70600"
st "updatePeriod"
ju 2
blo "93000,70400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "updatePeriod"
t "unsigned"
b "(updatePeriodBitNb-1 DOWNTO 0)"
o 1
suid 1,0
)
)
)
*140 (CptPort
uid 18225,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18226,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,69625,78000,70375"
)
tg (CPTG
uid 18227,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18228,0
va (VaSet
)
xt "79000,69400,83000,70600"
st "dataIn"
blo "79000,70400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*141 (CptPort
uid 18229,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18230,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,71625,78000,72375"
)
tg (CPTG
uid 18231,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18232,0
va (VaSet
)
xt "79000,71400,83800,72600"
st "dataOut"
blo "79000,72400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_logic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 3
suid 3,0
)
)
)
*142 (CptPort
uid 18233,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18234,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,77625,78000,78375"
)
tg (CPTG
uid 18235,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18236,0
va (VaSet
)
xt "79000,77400,80900,78600"
st "en"
blo "79000,78400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 4
suid 5,0
)
)
)
*143 (CptPort
uid 18237,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18238,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,81625,78000,82375"
)
tg (CPTG
uid 18239,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18240,0
va (VaSet
)
xt "79000,81400,82400,82600"
st "clock"
blo "79000,82400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 5
suid 6,0
)
)
)
*144 (CptPort
uid 18241,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18242,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,83625,78000,84375"
)
tg (CPTG
uid 18243,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18244,0
va (VaSet
)
xt "79000,83400,82300,84600"
st "reset"
blo "79000,84400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 6
suid 7,0
)
)
)
*145 (CptPort
uid 18245,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18246,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,75625,78000,76375"
)
tg (CPTG
uid 18247,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18248,0
va (VaSet
)
xt "79000,75400,82100,76600"
st "write"
blo "79000,76400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 7
suid 8,0
)
)
)
]
shape (Rectangle
uid 18250,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "78000,66000,94000,86000"
)
oxt "38000,9000,54000,29000"
ttg (MlTextGroup
uid 18251,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*146 (Text
uid 18252,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,85800,83000,87000"
st "Beamer"
blo "78600,86800"
tm "BdLibraryNameMgr"
)
*147 (Text
uid 18253,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,87000,87800,88200"
st "periphSpeedReg"
blo "78600,88000"
tm "CptNameMgr"
)
*148 (Text
uid 18254,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,88200,80300,89400"
st "I3"
blo "78600,89200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 18255,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 18256,0
text (MLText
uid 18257,0
va (VaSet
font "Verdana,8,0"
)
xt "78000,89600,102400,91600"
st "dataBitNb         = dataBitNb            ( positive )  
updatePeriodBitNb = updatePeriodBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "updatePeriodBitNb"
type "positive"
value "updatePeriodBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*149 (PortIoIn
uid 18266,0
shape (CompositeShape
uid 18267,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 18268,0
sl 0
ro 270
xt "68000,135625,69500,136375"
)
(Line
uid 18269,0
sl 0
ro 270
xt "69500,136000,70000,136000"
pts [
"69500,136000"
"70000,136000"
]
)
]
)
tg (WTG
uid 18270,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18271,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "57400,135300,67000,136700"
st "newPolynom"
ju 2
blo "67000,136500"
tm "WireNameMgr"
)
)
)
*150 (SaComponent
uid 19180,0
optionalChildren [
*151 (CptPort
uid 19152,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19153,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,153625,110000,154375"
)
tg (CPTG
uid 19154,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19155,0
va (VaSet
)
xt "111000,153400,115000,154600"
st "dataIn"
blo "111000,154400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 1
suid 1,0
)
)
)
*152 (CptPort
uid 19156,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19157,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126000,153625,126750,154375"
)
tg (CPTG
uid 19158,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 19159,0
va (VaSet
)
xt "120200,153400,125000,154600"
st "dataOut"
ju 2
blo "125000,154400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*153 (CptPort
uid 19160,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19161,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,161625,110000,162375"
)
tg (CPTG
uid 19162,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19163,0
va (VaSet
)
xt "111000,161400,112900,162600"
st "en"
blo "111000,162400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*154 (CptPort
uid 19164,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19165,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,165625,110000,166375"
)
tg (CPTG
uid 19166,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19167,0
va (VaSet
)
xt "111000,165400,114400,166600"
st "clock"
blo "111000,166400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 4
suid 4,0
)
)
)
*155 (CptPort
uid 19168,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19169,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,167625,110000,168375"
)
tg (CPTG
uid 19170,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19171,0
va (VaSet
)
xt "111000,167400,114300,168600"
st "reset"
blo "111000,168400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 5
suid 5,0
)
)
)
*156 (CptPort
uid 19172,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19173,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,159625,110000,160375"
)
tg (CPTG
uid 19174,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19175,0
va (VaSet
)
xt "111000,159400,114100,160600"
st "write"
blo "111000,160400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 6
suid 6,0
)
)
)
*157 (CptPort
uid 19176,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19177,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,155625,110000,156375"
)
tg (CPTG
uid 19178,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19179,0
va (VaSet
)
xt "111000,155400,113900,156600"
st "addr"
blo "111000,156400"
)
)
thePort (LogicalPort
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 7
suid 7,0
)
)
)
]
shape (Rectangle
uid 19181,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "110000,150000,126000,170000"
)
oxt "38000,9000,54000,29000"
ttg (MlTextGroup
uid 19182,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*158 (Text
uid 19183,0
va (VaSet
font "Verdana,9,1"
)
xt "110600,169800,115000,171000"
st "Beamer"
blo "110600,170800"
tm "BdLibraryNameMgr"
)
*159 (Text
uid 19184,0
va (VaSet
font "Verdana,9,1"
)
xt "110600,171000,116100,172200"
st "blockRAM"
blo "110600,172000"
tm "CptNameMgr"
)
*160 (Text
uid 19185,0
va (VaSet
font "Verdana,9,1"
)
xt "110600,172200,112900,173400"
st "I18"
blo "110600,173200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 19186,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 19187,0
text (MLText
uid 19188,0
va (VaSet
font "Verdana,8,0"
)
xt "110000,173600,137300,176600"
st "addressBitNb = patternAddressBitNb               ( positive )  
dataBitNb    = signalBitNb                       ( positive )  
initFileSpec = \"$SIMULATION_DIR\\ramYInit.txt\"    ( string   )  "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "initFileSpec"
type "string"
value "\"$SIMULATION_DIR\\ramYInit.txt\""
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*161 (SaComponent
uid 19217,0
optionalChildren [
*162 (CptPort
uid 19189,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19190,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,115625,110000,116375"
)
tg (CPTG
uid 19191,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19192,0
va (VaSet
)
xt "111000,115400,115000,116600"
st "dataIn"
blo "111000,116400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 1
suid 1,0
)
)
)
*163 (CptPort
uid 19193,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19194,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126000,115625,126750,116375"
)
tg (CPTG
uid 19195,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 19196,0
va (VaSet
)
xt "120200,115400,125000,116600"
st "dataOut"
ju 2
blo "125000,116400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*164 (CptPort
uid 19197,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19198,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,123625,110000,124375"
)
tg (CPTG
uid 19199,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19200,0
va (VaSet
)
xt "111000,123400,112900,124600"
st "en"
blo "111000,124400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*165 (CptPort
uid 19201,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19202,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,127625,110000,128375"
)
tg (CPTG
uid 19203,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19204,0
va (VaSet
)
xt "111000,127400,114400,128600"
st "clock"
blo "111000,128400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 4
suid 4,0
)
)
)
*166 (CptPort
uid 19205,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19206,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,129625,110000,130375"
)
tg (CPTG
uid 19207,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19208,0
va (VaSet
)
xt "111000,129400,114300,130600"
st "reset"
blo "111000,130400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 5
suid 5,0
)
)
)
*167 (CptPort
uid 19209,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19210,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,121625,110000,122375"
)
tg (CPTG
uid 19211,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19212,0
va (VaSet
)
xt "111000,121400,114100,122600"
st "write"
blo "111000,122400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 6
suid 6,0
)
)
)
*168 (CptPort
uid 19213,0
ps "OnEdgeStrategy"
shape (Triangle
uid 19214,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,117625,110000,118375"
)
tg (CPTG
uid 19215,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19216,0
va (VaSet
)
xt "111000,117400,113900,118600"
st "addr"
blo "111000,118400"
)
)
thePort (LogicalPort
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 7
suid 7,0
)
)
)
]
shape (Rectangle
uid 19218,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "110000,112000,126000,132000"
)
oxt "38000,9000,54000,29000"
ttg (MlTextGroup
uid 19219,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*169 (Text
uid 19220,0
va (VaSet
font "Verdana,9,1"
)
xt "110600,131800,115000,133000"
st "Beamer"
blo "110600,132800"
tm "BdLibraryNameMgr"
)
*170 (Text
uid 19221,0
va (VaSet
font "Verdana,9,1"
)
xt "110600,133000,116100,134200"
st "blockRAM"
blo "110600,134000"
tm "CptNameMgr"
)
*171 (Text
uid 19222,0
va (VaSet
font "Verdana,9,1"
)
xt "110600,134200,112900,135400"
st "I17"
blo "110600,135200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 19223,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 19224,0
text (MLText
uid 19225,0
va (VaSet
font "Verdana,8,0"
)
xt "110000,135600,137300,138600"
st "addressBitNb = patternAddressBitNb               ( positive )  
dataBitNb    = signalBitNb                       ( positive )  
initFileSpec = \"$SIMULATION_DIR\\ramXInit.txt\"    ( string   )  "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "initFileSpec"
type "string"
value "\"$SIMULATION_DIR\\ramXInit.txt\""
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*172 (Wire
uid 73,0
shape (OrthoPolyLine
uid 74,0
va (VaSet
vasetType 3
)
xt "74000,54000,77250,54000"
pts [
"74000,54000"
"77250,54000"
]
)
start &12
end &111
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 77,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 78,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,52600,77800,54000"
st "clock"
blo "74000,53800"
tm "WireNameMgr"
)
)
on &13
)
*173 (Wire
uid 157,0
shape (OrthoPolyLine
uid 158,0
va (VaSet
vasetType 3
)
xt "74000,56000,77250,56000"
pts [
"74000,56000"
"77250,56000"
]
)
start &77
end &112
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 161,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 162,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,54600,78100,56000"
st "reset"
blo "74000,55800"
tm "WireNameMgr"
)
)
on &14
)
*174 (Wire
uid 1057,0
shape (OrthoPolyLine
uid 1058,0
va (VaSet
vasetType 3
)
xt "46750,74000,77250,78000"
pts [
"46750,74000"
"58000,74000"
"58000,78000"
"77250,78000"
]
)
start &93
end &142
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1061,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1062,0
va (VaSet
font "Verdana,12,0"
)
xt "70000,76600,76600,78000"
st "selSpeed"
blo "70000,77800"
tm "WireNameMgr"
)
)
on &17
)
*175 (Wire
uid 1065,0
shape (OrthoPolyLine
uid 1066,0
va (VaSet
vasetType 3
)
xt "46750,78000,77250,180000"
pts [
"46750,78000"
"56000,78000"
"56000,180000"
"77250,180000"
]
)
start &94
end &57
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1069,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1070,0
va (VaSet
font "Verdana,12,0"
)
xt "70000,178600,73400,180000"
st "selX"
blo "70000,179800"
tm "WireNameMgr"
)
)
on &18
)
*176 (Wire
uid 1073,0
shape (OrthoPolyLine
uid 1074,0
va (VaSet
vasetType 3
)
xt "46750,80000,77250,130000"
pts [
"46750,80000"
"54000,80000"
"54000,130000"
"77250,130000"
]
)
start &95
end &44
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1077,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1078,0
va (VaSet
font "Verdana,12,0"
)
xt "70000,128600,73300,130000"
st "selY"
blo "70000,129800"
tm "WireNameMgr"
)
)
on &19
)
*177 (Wire
uid 1332,0
shape (OrthoPolyLine
uid 1333,0
va (VaSet
vasetType 3
)
xt "46750,50000,77250,72000"
pts [
"46750,72000"
"58000,72000"
"58000,50000"
"77250,50000"
]
)
start &91
end &110
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1338,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1339,0
va (VaSet
font "Verdana,12,0"
)
xt "70000,48600,78000,50000"
st "selControl"
blo "70000,49800"
tm "WireNameMgr"
)
)
on &16
)
*178 (Wire
uid 1340,0
shape (OrthoPolyLine
uid 1341,0
va (VaSet
vasetType 3
)
xt "70000,48000,77250,48000"
pts [
"70000,48000"
"77250,48000"
]
)
end &109
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1346,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1347,0
va (VaSet
font "Verdana,12,0"
)
xt "70000,46600,74000,48000"
st "write"
blo "70000,47800"
tm "WireNameMgr"
)
)
on &89
)
*179 (Wire
uid 1350,0
shape (OrthoPolyLine
uid 1351,0
va (VaSet
vasetType 3
)
xt "94750,42000,109250,42000"
pts [
"94750,42000"
"109250,42000"
]
)
start &105
end &74
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1354,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1355,0
va (VaSet
font "Verdana,12,0"
)
xt "106000,40600,108900,42000"
st "run"
blo "106000,41800"
tm "WireNameMgr"
)
)
on &20
)
*180 (Wire
uid 1358,0
shape (OrthoPolyLine
uid 1359,0
va (VaSet
vasetType 3
)
xt "94750,48000,102000,48000"
pts [
"94750,48000"
"102000,48000"
]
)
start &107
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1362,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1363,0
va (VaSet
font "Verdana,12,0"
)
xt "96750,46600,107550,48000"
st "updatePattern"
blo "96750,47800"
tm "WireNameMgr"
)
)
on &21
)
*181 (Wire
uid 1472,0
shape (OrthoPolyLine
uid 1473,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "94750,50000,102000,50000"
pts [
"94750,50000"
"102000,50000"
]
)
start &114
sat 32
eat 16
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1476,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1477,0
va (VaSet
font "Verdana,12,0"
)
xt "96750,48600,105650,50000"
st "patternSize"
blo "96750,49800"
tm "WireNameMgr"
)
)
on &22
)
*182 (Wire
uid 1526,0
optionalChildren [
*183 (BdJunction
uid 1538,0
ps "OnConnectorStrategy"
shape (Circle
uid 1539,0
va (VaSet
vasetType 1
)
xt "61600,41600,62400,42400"
radius 400
)
)
*184 (BdJunction
uid 1736,0
ps "OnConnectorStrategy"
shape (Circle
uid 1737,0
va (VaSet
vasetType 1
)
xt "61600,69600,62400,70400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 1527,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "46000,42000,62000,86000"
pts [
"62000,86000"
"62000,42000"
"46000,42000"
]
)
start &84
end &79
sat 1
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1532,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1533,0
va (VaSet
font "Verdana,12,0"
)
xt "46000,40600,51000,42000"
st "dataIn"
blo "46000,41800"
tm "WireNameMgr"
)
)
on &78
)
*185 (Wire
uid 1534,0
shape (OrthoPolyLine
uid 1535,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "62000,42000,77250,42000"
pts [
"62000,42000"
"77250,42000"
]
)
start &183
end &106
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1536,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1537,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,40600,76000,42000"
st "dataIn"
blo "71000,41800"
tm "WireNameMgr"
)
)
on &78
)
*186 (Wire
uid 1583,0
optionalChildren [
*187 (BdJunction
uid 2856,0
ps "OnConnectorStrategy"
shape (Circle
uid 2857,0
va (VaSet
vasetType 1
)
xt "65600,71600,66400,72400"
radius 400
)
)
*188 (BdJunction
uid 2864,0
ps "OnConnectorStrategy"
shape (Circle
uid 2865,0
va (VaSet
vasetType 1
)
xt "65600,43600,66400,44400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 1584,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "46000,26000,66000,76000"
pts [
"66000,76000"
"66000,26000"
"46000,26000"
]
)
end &100
sat 16
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1587,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1588,0
va (VaSet
font "Verdana,12,0"
)
xt "49000,24600,55000,26000"
st "dataOut"
blo "49000,25800"
tm "WireNameMgr"
)
)
on &23
)
*189 (Wire
uid 1732,0
shape (OrthoPolyLine
uid 1733,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "62000,70000,77250,70000"
pts [
"62000,70000"
"77250,70000"
]
)
start &184
end &140
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1734,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1735,0
va (VaSet
font "Verdana,12,0"
)
xt "72250,68600,77250,70000"
st "dataIn"
blo "72250,69800"
tm "WireNameMgr"
)
)
on &78
)
*190 (Wire
uid 1738,0
shape (OrthoPolyLine
uid 1739,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "66000,72000,77250,72000"
pts [
"66000,72000"
"77250,72000"
]
)
start &187
end &141
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1740,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1741,0
va (VaSet
font "Verdana,12,0"
)
xt "71250,70600,77250,72000"
st "dataOut"
blo "71250,71800"
tm "WireNameMgr"
)
)
on &23
)
*191 (Wire
uid 1744,0
shape (OrthoPolyLine
uid 1745,0
va (VaSet
vasetType 3
)
xt "74000,84000,77250,84000"
pts [
"74000,84000"
"77250,84000"
]
)
end &144
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1750,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1751,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,82600,78100,84000"
st "reset"
blo "74000,83800"
tm "WireNameMgr"
)
)
on &14
)
*192 (Wire
uid 1752,0
shape (OrthoPolyLine
uid 1753,0
va (VaSet
vasetType 3
)
xt "74000,82000,77250,82000"
pts [
"74000,82000"
"77250,82000"
]
)
end &143
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1758,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1759,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,80600,77800,82000"
st "clock"
blo "74000,81800"
tm "WireNameMgr"
)
)
on &13
)
*193 (Wire
uid 1778,0
shape (OrthoPolyLine
uid 1779,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "94750,70000,109250,70000"
pts [
"94750,70000"
"109250,70000"
]
)
start &139
end &75
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1782,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1783,0
va (VaSet
font "Verdana,12,0"
)
xt "96000,68600,106100,70000"
st "updatePeriod"
blo "96000,69800"
tm "WireNameMgr"
)
)
on &24
)
*194 (Wire
uid 2478,0
shape (OrthoPolyLine
uid 2479,0
va (VaSet
vasetType 3
)
xt "106000,166000,109250,166000"
pts [
"106000,166000"
"109250,166000"
]
)
end &154
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2484,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2485,0
va (VaSet
font "Verdana,12,0"
)
xt "106000,164600,109800,166000"
st "clock"
blo "106000,165800"
tm "WireNameMgr"
)
)
on &13
)
*195 (Wire
uid 2486,0
shape (OrthoPolyLine
uid 2487,0
va (VaSet
vasetType 3
)
xt "106000,168000,109250,168000"
pts [
"106000,168000"
"109250,168000"
]
)
end &155
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2492,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2493,0
va (VaSet
font "Verdana,12,0"
)
xt "106000,166600,110100,168000"
st "reset"
blo "106000,167800"
tm "WireNameMgr"
)
)
on &14
)
*196 (Wire
uid 2638,0
shape (OrthoPolyLine
uid 2639,0
va (VaSet
vasetType 3
)
xt "94750,160000,109250,184000"
pts [
"94750,184000"
"102000,184000"
"102000,160000"
"109250,160000"
]
)
start &56
end &156
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2640,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2641,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,158600,109400,160000"
st "memWrX"
blo "103000,159800"
tm "WireNameMgr"
)
)
on &27
)
*197 (Wire
uid 2644,0
shape (OrthoPolyLine
uid 2645,0
va (VaSet
vasetType 3
)
xt "94750,162000,109250,186000"
pts [
"94750,186000"
"104000,186000"
"104000,162000"
"109250,162000"
]
)
start &58
end &153
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2646,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2647,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,160600,109200,162000"
st "memEnX"
blo "103000,161800"
tm "WireNameMgr"
)
)
on &28
)
*198 (Wire
uid 2648,0
shape (OrthoPolyLine
uid 2649,0
va (VaSet
vasetType 3
)
xt "70000,184000,77250,184000"
pts [
"70000,184000"
"77250,184000"
]
)
end &59
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2654,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2655,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,182600,79800,184000"
st "updatePattern"
blo "69000,183800"
tm "WireNameMgr"
)
)
on &21
)
*199 (Wire
uid 2772,0
shape (OrthoPolyLine
uid 2773,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "94750,156000,109250,156000"
pts [
"94750,156000"
"109250,156000"
]
)
start &133
end &157
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2774,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2775,0
va (VaSet
font "Verdana,12,0"
)
xt "105000,154600,109500,156000"
st "addrX"
blo "105000,155800"
tm "WireNameMgr"
)
)
on &25
)
*200 (Wire
uid 2778,0
shape (OrthoPolyLine
uid 2779,0
va (VaSet
vasetType 3
)
xt "74000,166000,77250,166000"
pts [
"74000,166000"
"77250,166000"
]
)
end &131
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2784,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2785,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,164600,78100,166000"
st "reset"
blo "74000,165800"
tm "WireNameMgr"
)
)
on &14
)
*201 (Wire
uid 2786,0
shape (OrthoPolyLine
uid 2787,0
va (VaSet
vasetType 3
)
xt "74000,164000,77250,164000"
pts [
"74000,164000"
"77250,164000"
]
)
end &130
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2792,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2793,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,162600,77800,164000"
st "clock"
blo "74000,163800"
tm "WireNameMgr"
)
)
on &13
)
*202 (Wire
uid 2844,0
shape (OrthoPolyLine
uid 2845,0
va (VaSet
vasetType 3
)
xt "72000,160000,98000,180000"
pts [
"94750,180000"
"98000,180000"
"98000,174000"
"72000,174000"
"72000,160000"
"77250,160000"
]
)
start &61
end &129
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2846,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2847,0
va (VaSet
font "Verdana,12,0"
)
xt "72000,158600,77900,160000"
st "cntIncrX"
blo "72000,159800"
tm "WireNameMgr"
)
)
on &26
)
*203 (Wire
uid 2860,0
shape (OrthoPolyLine
uid 2861,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "66000,44000,77250,44000"
pts [
"66000,44000"
"77250,44000"
]
)
start &188
end &108
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2862,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2863,0
va (VaSet
font "Verdana,12,0"
)
xt "71250,42600,77250,44000"
st "dataOut"
blo "71250,43800"
tm "WireNameMgr"
)
)
on &23
)
*204 (Wire
uid 2866,0
shape (OrthoPolyLine
uid 2867,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "70000,156000,77250,156000"
pts [
"70000,156000"
"77250,156000"
]
)
end &134
sat 16
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2872,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2873,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,154600,77900,156000"
st "patternSize"
blo "69000,155800"
tm "WireNameMgr"
)
)
on &22
)
*205 (Wire
uid 2919,0
shape (OrthoPolyLine
uid 2920,0
va (VaSet
vasetType 3
)
xt "70000,186000,77250,186000"
pts [
"77250,186000"
"70000,186000"
]
)
start &62
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2925,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2926,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,184600,78600,186000"
st "newPolynom"
blo "69000,185800"
tm "WireNameMgr"
)
)
on &15
)
*206 (Wire
uid 2996,0
shape (OrthoPolyLine
uid 2997,0
va (VaSet
vasetType 3
)
xt "74000,192000,77250,192000"
pts [
"74000,192000"
"77250,192000"
]
)
end &64
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3002,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3003,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,190600,78100,192000"
st "reset"
blo "74000,191800"
tm "WireNameMgr"
)
)
on &14
)
*207 (Wire
uid 3004,0
shape (OrthoPolyLine
uid 3005,0
va (VaSet
vasetType 3
)
xt "74000,190000,77250,190000"
pts [
"74000,190000"
"77250,190000"
]
)
end &63
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3010,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3011,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,188600,77800,190000"
st "clock"
blo "74000,189800"
tm "WireNameMgr"
)
)
on &13
)
*208 (Wire
uid 3094,0
shape (OrthoPolyLine
uid 3095,0
va (VaSet
vasetType 3
)
xt "70000,158000,77250,158000"
pts [
"70000,158000"
"77250,158000"
]
)
end &132
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3100,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3101,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,156600,79800,158000"
st "updatePattern"
blo "69000,157800"
tm "WireNameMgr"
)
)
on &21
)
*209 (Wire
uid 3146,0
shape (OrthoPolyLine
uid 3147,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "126750,154000,134000,154000"
pts [
"126750,154000"
"134000,154000"
]
)
start &152
end &73
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3150,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3151,0
va (VaSet
font "Verdana,12,0"
)
xt "128000,152600,132600,154000"
st "memX"
blo "128000,153800"
tm "WireNameMgr"
)
)
on &29
)
*210 (Wire
uid 3751,0
shape (OrthoPolyLine
uid 3752,0
va (VaSet
vasetType 3
)
xt "106000,130000,109250,130000"
pts [
"106000,130000"
"109250,130000"
]
)
end &166
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3755,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3756,0
va (VaSet
font "Verdana,12,0"
)
xt "106000,128600,110100,130000"
st "reset"
blo "106000,129800"
tm "WireNameMgr"
)
)
on &14
)
*211 (Wire
uid 3757,0
shape (OrthoPolyLine
uid 3758,0
va (VaSet
vasetType 3
)
xt "106000,128000,109250,128000"
pts [
"106000,128000"
"109250,128000"
]
)
end &165
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3761,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3762,0
va (VaSet
font "Verdana,12,0"
)
xt "106000,126600,109800,128000"
st "clock"
blo "106000,127800"
tm "WireNameMgr"
)
)
on &13
)
*212 (Wire
uid 3763,0
shape (OrthoPolyLine
uid 3764,0
va (VaSet
vasetType 3
)
xt "70000,134000,77250,134000"
pts [
"70000,134000"
"77250,134000"
]
)
end &46
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3767,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3768,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,132600,79800,134000"
st "updatePattern"
blo "69000,133800"
tm "WireNameMgr"
)
)
on &21
)
*213 (Wire
uid 3769,0
shape (OrthoPolyLine
uid 3770,0
va (VaSet
vasetType 3
)
xt "94750,124000,109250,136000"
pts [
"94750,136000"
"102000,136000"
"102000,124000"
"109250,124000"
]
)
start &45
end &164
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3771,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3772,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,122600,109100,124000"
st "memEnY"
blo "103000,123800"
tm "WireNameMgr"
)
)
on &33
)
*214 (Wire
uid 3773,0
shape (OrthoPolyLine
uid 3774,0
va (VaSet
vasetType 3
)
xt "94750,122000,109250,134000"
pts [
"94750,134000"
"100000,134000"
"100000,122000"
"109250,122000"
]
)
start &43
end &167
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3775,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3776,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,120600,109300,122000"
st "memWrY"
blo "103000,121800"
tm "WireNameMgr"
)
)
on &32
)
*215 (Wire
uid 3777,0
shape (OrthoPolyLine
uid 3778,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "94750,106000,109250,118000"
pts [
"94750,106000"
"98000,106000"
"98000,118000"
"109250,118000"
]
)
start &123
end &168
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3779,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3780,0
va (VaSet
font "Verdana,12,0"
)
xt "105000,116600,109400,118000"
st "addrY"
blo "105000,117800"
tm "WireNameMgr"
)
)
on &31
)
*216 (Wire
uid 3793,0
shape (OrthoPolyLine
uid 3794,0
va (VaSet
vasetType 3
)
xt "72000,110000,98000,130000"
pts [
"94750,130000"
"98000,130000"
"98000,124000"
"72000,124000"
"72000,110000"
"77250,110000"
]
)
start &48
end &119
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3795,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3796,0
va (VaSet
font "Verdana,12,0"
)
xt "72000,108600,77800,110000"
st "cntIncrY"
blo "72000,109800"
tm "WireNameMgr"
)
)
on &30
)
*217 (Wire
uid 3797,0
shape (OrthoPolyLine
uid 3798,0
va (VaSet
vasetType 3
)
xt "70000,136000,77250,136000"
pts [
"77250,136000"
"70000,136000"
]
)
start &49
end &149
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3801,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3802,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,134600,78600,136000"
st "newPolynom"
blo "69000,135800"
tm "WireNameMgr"
)
)
on &15
)
*218 (Wire
uid 3803,0
shape (OrthoPolyLine
uid 3804,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "70000,106000,77250,106000"
pts [
"70000,106000"
"77250,106000"
]
)
end &124
sat 16
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3807,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3808,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,104600,77900,106000"
st "patternSize"
blo "69000,105800"
tm "WireNameMgr"
)
)
on &22
)
*219 (Wire
uid 3809,0
shape (OrthoPolyLine
uid 3810,0
va (VaSet
vasetType 3
)
xt "70000,108000,77250,108000"
pts [
"70000,108000"
"77250,108000"
]
)
end &122
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3813,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3814,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,106600,79800,108000"
st "updatePattern"
blo "69000,107800"
tm "WireNameMgr"
)
)
on &21
)
*220 (Wire
uid 3815,0
shape (OrthoPolyLine
uid 3816,0
va (VaSet
vasetType 3
)
xt "74000,140000,77250,140000"
pts [
"74000,140000"
"77250,140000"
]
)
end &50
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3819,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3820,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,138600,77800,140000"
st "clock"
blo "74000,139800"
tm "WireNameMgr"
)
)
on &13
)
*221 (Wire
uid 3866,0
shape (OrthoPolyLine
uid 3867,0
va (VaSet
vasetType 3
)
xt "74000,114000,77250,114000"
pts [
"74000,114000"
"77250,114000"
]
)
end &120
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3872,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3873,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,112600,77800,114000"
st "clock"
blo "74000,113800"
tm "WireNameMgr"
)
)
on &13
)
*222 (Wire
uid 3874,0
shape (OrthoPolyLine
uid 3875,0
va (VaSet
vasetType 3
)
xt "74000,116000,77250,116000"
pts [
"74000,116000"
"77250,116000"
]
)
end &121
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3880,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3881,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,114600,78100,116000"
st "reset"
blo "74000,115800"
tm "WireNameMgr"
)
)
on &14
)
*223 (Wire
uid 3882,0
shape (OrthoPolyLine
uid 3883,0
va (VaSet
vasetType 3
)
xt "74000,142000,77250,142000"
pts [
"74000,142000"
"77250,142000"
]
)
end &51
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3888,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3889,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,140600,78100,142000"
st "reset"
blo "74000,141800"
tm "WireNameMgr"
)
)
on &14
)
*224 (Wire
uid 3907,0
shape (OrthoPolyLine
uid 3908,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "126750,116000,134000,116000"
pts [
"126750,116000"
"134000,116000"
]
)
start &163
end &72
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3911,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3912,0
va (VaSet
font "Verdana,12,0"
)
xt "128750,114600,133250,116000"
st "memY"
blo "128750,115800"
tm "WireNameMgr"
)
)
on &34
)
*225 (Wire
uid 4047,0
shape (OrthoPolyLine
uid 4048,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "135000,4000,143000,4000"
pts [
"135000,4000"
"143000,4000"
]
)
start &37
end &35
sat 2
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4051,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4052,0
va (VaSet
font "Verdana,12,0"
)
xt "138000,2600,143600,4000"
st "testOut"
blo "138000,3800"
tm "WireNameMgr"
)
)
on &36
)
*226 (Wire
uid 7907,0
shape (OrthoPolyLine
uid 7908,0
va (VaSet
vasetType 3
)
xt "70000,132000,77250,132000"
pts [
"70000,132000"
"77250,132000"
]
)
end &47
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7913,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7914,0
va (VaSet
font "Verdana,12,0"
)
xt "70000,130600,74000,132000"
st "write"
blo "70000,131800"
tm "WireNameMgr"
)
)
on &89
)
*227 (Wire
uid 7915,0
shape (OrthoPolyLine
uid 7916,0
va (VaSet
vasetType 3
)
xt "70000,182000,77250,182000"
pts [
"70000,182000"
"77250,182000"
]
)
end &60
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7921,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7922,0
va (VaSet
font "Verdana,12,0"
)
xt "70000,180600,74000,182000"
st "write"
blo "70000,181800"
tm "WireNameMgr"
)
)
on &89
)
*228 (Wire
uid 8150,0
shape (OrthoPolyLine
uid 8151,0
va (VaSet
vasetType 3
)
xt "94750,44000,109000,44000"
pts [
"94750,44000"
"109000,44000"
]
)
start &113
end &76
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 8154,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8155,0
va (VaSet
font "Verdana,12,0"
)
xt "101000,42600,111300,44000"
st "interpolateLin"
blo "101000,43800"
tm "WireNameMgr"
)
)
on &41
)
*229 (Wire
uid 13134,0
shape (OrthoPolyLine
uid 13135,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "22000,42000,30000,42000"
pts [
"22000,42000"
"30000,42000"
]
)
start &68
end &79
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 13138,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13139,0
va (VaSet
font "Verdana,12,0"
)
xt "22000,40600,25500,42000"
st "apbi"
blo "22000,41800"
tm "WireNameMgr"
)
)
on &69
)
*230 (Wire
uid 13379,0
shape (OrthoPolyLine
uid 13380,0
va (VaSet
vasetType 3
)
xt "22000,26000,30000,26000"
pts [
"30000,26000"
"22000,26000"
]
)
start &100
end &70
sat 2
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 13383,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13384,0
va (VaSet
font "Verdana,12,0"
)
xt "22000,24600,26000,26000"
st "apbo"
blo "22000,25800"
tm "WireNameMgr"
)
)
on &71
)
*231 (Wire
uid 16718,0
shape (OrthoPolyLine
uid 16719,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "26000,44000,50000,72000"
pts [
"29250,72000"
"26000,72000"
"26000,64000"
"50000,64000"
"50000,44000"
"46000,44000"
]
)
start &92
end &79
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 16722,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16723,0
va (VaSet
font "Verdana,12,0"
)
xt "48000,42600,51700,44000"
st "addr"
blo "48000,43800"
tm "WireNameMgr"
)
)
on &83
)
*232 (Wire
uid 17156,0
optionalChildren [
*233 (BdJunction
uid 18482,0
ps "OnConnectorStrategy"
shape (Circle
uid 18483,0
va (VaSet
vasetType 1
)
xt "61600,99600,62400,100400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 17157,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "62000,94000,109250,116000"
pts [
"109250,116000"
"106000,116000"
"106000,100000"
"62000,100000"
"62000,94000"
]
)
start &162
end &84
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17160,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17161,0
va (VaSet
font "Verdana,12,0"
)
xt "102000,114600,110100,116000"
st "memDataIn"
blo "102000,115800"
tm "WireNameMgr"
)
)
on &88
)
*234 (Wire
uid 17164,0
shape (OrthoPolyLine
uid 17165,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "62000,100000,109250,154000"
pts [
"109250,154000"
"106000,154000"
"106000,150000"
"62000,150000"
"62000,100000"
]
)
start &151
end &233
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17170,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17171,0
va (VaSet
font "Verdana,12,0"
)
xt "101000,152600,109100,154000"
st "memDataIn"
blo "101000,153800"
tm "WireNameMgr"
)
)
on &88
)
*235 (Wire
uid 17515,0
shape (OrthoPolyLine
uid 17516,0
va (VaSet
vasetType 3
)
xt "46000,46000,54000,46000"
pts [
"46000,46000"
"54000,46000"
]
)
start &79
sat 2
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17521,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17522,0
va (VaSet
font "Verdana,12,0"
)
xt "51000,44600,55000,46000"
st "write"
blo "51000,45800"
tm "WireNameMgr"
)
)
on &89
)
*236 (Wire
uid 18258,0
shape (OrthoPolyLine
uid 18259,0
va (VaSet
vasetType 3
)
xt "70000,76000,77250,76000"
pts [
"70000,76000"
"77250,76000"
]
)
end &145
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 18264,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18265,0
va (VaSet
font "Verdana,12,0"
)
xt "70000,74600,74000,76000"
st "write"
blo "70000,75800"
tm "WireNameMgr"
)
)
on &89
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 0
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *237 (PackageList
uid 42,0
stg "VerticalLayoutStrategy"
textVec [
*238 (Text
uid 43,0
va (VaSet
font "Verdana,8,1"
)
xt "0,0,6900,1000"
st "Package List"
blo "0,800"
)
*239 (MLText
uid 44,0
va (VaSet
)
xt "0,1000,17500,4600"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 45,0
stg "VerticalLayoutStrategy"
textVec [
*240 (Text
uid 46,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,0,30200,1000"
st "Compiler Directives"
blo "20000,800"
)
*241 (Text
uid 47,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,1000,32200,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*242 (MLText
uid 48,0
va (VaSet
isHidden 1
)
xt "20000,2000,32100,4400"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*243 (Text
uid 49,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,4000,32800,5000"
st "Post-module directives:"
blo "20000,4800"
)
*244 (MLText
uid 50,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*245 (Text
uid 51,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,5000,32400,6000"
st "End-module directives:"
blo "20000,5800"
)
*246 (MLText
uid 52,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "-8,-8,1928,1048"
viewArea "-2784,-2784,374267,202077"
cachedDiagramExtent "0,0,166900,198000"
pageSetupInfo (PageSetupInfo
ptrCmd "\\\\vmenpprint1.hevs.ch\\VS-FOLLOWME-PRN,winspool,"
fileName "ipp://ippsion.hevs.ch/ipp/PREA309_HPLJ3005DN"
toPrinter 1
colour 1
xMargin 47
yMargin 47
paperWidth 761
paperHeight 1077
windowsPaperWidth 761
windowsPaperHeight 1077
paperType "A4 (210 x 297 mm)"
windowsPaperName "A4 (210 x 297 mm)"
windowsPaperType 9
scale 50
useAdjustTo 0
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
)
hasePageBreakOrigin 1
pageBreakOrigin "0,0"
lastUid 19720,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "65535,0,0"
)
xt "200,200,3200,1400"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "Verdana,8,0"
)
xt "450,2150,1450,3150"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Verdana,10,1"
)
xt "1000,1000,4400,2200"
st "Panel0"
blo "1000,2000"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "40000,56832,65535"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*247 (Text
va (VaSet
)
xt "1700,3200,6300,4400"
st "<library>"
blo "1700,4200"
tm "BdLibraryNameMgr"
)
*248 (Text
va (VaSet
)
xt "1700,4400,5800,5600"
st "<block>"
blo "1700,5400"
tm "BlkNameMgr"
)
*249 (Text
va (VaSet
)
xt "1700,5600,2900,6800"
st "I0"
blo "1700,6600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "1700,13200,1700,13200"
)
header ""
)
elements [
]
)
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*250 (Text
va (VaSet
)
xt "1000,3500,3300,4500"
st "Library"
blo "1000,4300"
)
*251 (Text
va (VaSet
)
xt "1000,4500,7000,5500"
st "MWComponent"
blo "1000,5300"
)
*252 (Text
va (VaSet
)
xt "1000,5500,1600,6500"
st "I0"
blo "1000,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6000,1500,-6000,1500"
)
header ""
)
elements [
]
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*253 (Text
va (VaSet
)
xt "1250,3500,3550,4500"
st "Library"
blo "1250,4300"
tm "BdLibraryNameMgr"
)
*254 (Text
va (VaSet
)
xt "1250,4500,6750,5500"
st "SaComponent"
blo "1250,5300"
tm "CptNameMgr"
)
*255 (Text
va (VaSet
)
xt "1250,5500,1850,6500"
st "I0"
blo "1250,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-5750,1500,-5750,1500"
)
header ""
)
elements [
]
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*256 (Text
va (VaSet
)
xt "950,3500,3250,4500"
st "Library"
blo "950,4300"
)
*257 (Text
va (VaSet
)
xt "950,4500,7050,5500"
st "VhdlComponent"
blo "950,5300"
)
*258 (Text
va (VaSet
)
xt "950,5500,1550,6500"
st "I0"
blo "950,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6050,1500,-6050,1500"
)
header ""
)
elements [
]
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-50,0,8050,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*259 (Text
va (VaSet
)
xt "450,3500,2750,4500"
st "Library"
blo "450,4300"
)
*260 (Text
va (VaSet
)
xt "450,4500,7550,5500"
st "VerilogComponent"
blo "450,5300"
)
*261 (Text
va (VaSet
)
xt "450,5500,1050,6500"
st "I0"
blo "450,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6550,1500,-6550,1500"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*262 (Text
va (VaSet
)
xt "3400,4000,4600,5000"
st "eb1"
blo "3400,4800"
tm "HdlTextNameMgr"
)
*263 (Text
va (VaSet
)
xt "3400,5000,3800,6000"
st "1"
blo "3400,5800"
tm "HdlTextNumberMgr"
)
]
)
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,3200,1400"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
)
xt "-300,-500,300,500"
st "G"
blo "-300,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "0,0,2600,1400"
st "sig0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "0,0,3900,1400"
st "dbus0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineStyle 3
lineWidth 1
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,2600,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1000,1500,2200"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,50000"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
xt "0,0,5000,1200"
st "Auto list"
)
second (MLText
va (VaSet
)
xt "0,1000,9600,2200"
st "User defined list"
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,18500,100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1450"
)
num (Text
va (VaSet
)
xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*264 (Text
va (VaSet
font "Verdana,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*265 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,11000,100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1450"
)
num (Text
va (VaSet
)
xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*266 (Text
va (VaSet
font "Verdana,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*267 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Verdana,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Verdana,8,1"
)
xt "0,99400,7000,100400"
st "Declarations"
blo "0,100200"
)
portLabel (Text
uid 3,0
va (VaSet
font "Verdana,8,1"
)
xt "0,100400,3400,101400"
st "Ports:"
blo "0,101200"
)
preUserLabel (Text
uid 4,0
va (VaSet
font "Verdana,8,1"
)
xt "0,110200,4800,111200"
st "Pre User:"
blo "0,111000"
)
preUserText (MLText
uid 5,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,111200,25800,113200"
st "constant addressBitNb: positive := apbi.paddr'length;
constant dataBitNb : positive := apbi.pwdata'length;"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Verdana,8,1"
)
xt "0,112800,9000,113800"
st "Diagram Signals:"
blo "0,113600"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "0,99400,6000,100400"
st "Post User:"
blo "0,100200"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,99400,0,99400"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
ordering 1
suid 78,0
usingSuid 1
emptyRow *268 (LEmptyRow
)
uid 10774,0
optionalChildren [
*269 (RefLabelRowHdr
)
*270 (TitleRowHdr
)
*271 (FilterRowHdr
)
*272 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*273 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*274 (GroupColHdr
tm "GroupColHdrMgr"
)
*275 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*276 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*277 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*278 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*279 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*280 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*281 (LeafLogPort
port (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2,0
)
)
uid 10635,0
)
*282 (LeafLogPort
port (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 10
suid 7,0
)
)
uid 10645,0
)
*283 (LeafLogPort
port (LogicalPort
decl (Decl
n "newPolynom"
t "std_ulogic"
o 11
suid 10,0
)
)
uid 10651,0
)
*284 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "selControl"
t "std_ulogic"
o 24
suid 33,0
)
)
uid 10697,0
)
*285 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "selSpeed"
t "std_ulogic"
o 25
suid 35,0
)
)
uid 10701,0
)
*286 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "selX"
t "std_ulogic"
o 26
suid 36,0
)
)
uid 10703,0
)
*287 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "selY"
t "std_ulogic"
o 27
suid 37,0
)
)
uid 10705,0
)
*288 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "run"
t "std_ulogic"
o 7
suid 38,0
)
)
uid 10707,0
)
*289 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "updatePattern"
t "std_ulogic"
o 28
suid 39,0
)
)
uid 10709,0
)
*290 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "patternSize"
t "unsigned"
b "(patternAddressBitNb-1 DOWNTO 0)"
o 23
suid 40,0
)
)
uid 10711,0
)
*291 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dataOut"
t "std_logic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 18
suid 41,0
)
)
uid 10713,0
)
*292 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "updatePeriod"
t "unsigned"
b "(updatePeriodBitNb-1 DOWNTO 0)"
o 8
suid 42,0
)
)
uid 10715,0
)
*293 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "addrX"
t "unsigned"
b "(patternAddressBitNb-1 DOWNTO 0)"
o 13
suid 44,0
)
)
uid 10719,0
)
*294 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "cntIncrX"
t "std_ulogic"
o 15
suid 45,0
)
)
uid 10721,0
)
*295 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memWrX"
t "std_ulogic"
o 21
suid 46,0
)
)
uid 10723,0
)
*296 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memEnX"
t "std_ulogic"
o 19
suid 47,0
)
)
uid 10725,0
)
*297 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "memX"
t "std_ulogic_vector"
b "(signalBitNb-1 DOWNTO 0)"
o 5
suid 48,0
)
)
uid 10727,0
)
*298 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "cntIncrY"
t "std_ulogic"
o 16
suid 49,0
)
)
uid 10729,0
)
*299 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "addrY"
t "unsigned"
b "(patternAddressBitNb-1 DOWNTO 0)"
o 14
suid 50,0
)
)
uid 10731,0
)
*300 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memWrY"
t "std_ulogic"
o 22
suid 51,0
)
)
uid 10733,0
)
*301 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memEnY"
t "std_ulogic"
o 20
suid 52,0
)
)
uid 10735,0
)
*302 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "memY"
t "std_ulogic_vector"
b "(signalBitNb-1 DOWNTO 0)"
o 6
suid 53,0
)
)
uid 10737,0
)
*303 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "testOut"
t "std_ulogic_vector"
b "(1 TO testOutBitNb)"
o 4
suid 54,0
)
)
uid 10739,0
)
*304 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "interpolateLin"
t "std_ulogic"
o 9
suid 70,0
)
)
uid 10771,0
)
*305 (LeafLogPort
port (LogicalPort
decl (Decl
n "apbi"
t "apb_slv_in_type"
o 1
suid 71,0
)
)
uid 13127,0
)
*306 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "apbo"
t "apb_slv_out_type"
o 3
suid 72,0
)
)
uid 13372,0
)
*307 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 17
suid 74,0
)
)
uid 16726,0
)
*308 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 12
suid 75,0
)
)
uid 16728,0
)
*309 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memDataIn"
t "std_ulogic_vector"
b "(signalBitNb-1 DOWNTO 0)"
o 30
suid 77,0
)
)
uid 17172,0
)
*310 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "write"
t "std_ulogic"
o 29
suid 78,0
)
)
uid 17556,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 10787,0
optionalChildren [
*311 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *312 (MRCItem
litem &268
pos 30
dimension 20
)
uid 10789,0
optionalChildren [
*313 (MRCItem
litem &269
pos 0
dimension 20
uid 10790,0
)
*314 (MRCItem
litem &270
pos 1
dimension 23
uid 10791,0
)
*315 (MRCItem
litem &271
pos 2
hidden 1
dimension 20
uid 10792,0
)
*316 (MRCItem
litem &281
pos 1
dimension 20
uid 10636,0
)
*317 (MRCItem
litem &282
pos 9
dimension 20
uid 10646,0
)
*318 (MRCItem
litem &283
pos 10
dimension 20
uid 10652,0
)
*319 (MRCItem
litem &284
pos 12
dimension 20
uid 10698,0
)
*320 (MRCItem
litem &285
pos 13
dimension 20
uid 10702,0
)
*321 (MRCItem
litem &286
pos 14
dimension 20
uid 10704,0
)
*322 (MRCItem
litem &287
pos 15
dimension 20
uid 10706,0
)
*323 (MRCItem
litem &288
pos 4
dimension 20
uid 10708,0
)
*324 (MRCItem
litem &289
pos 16
dimension 20
uid 10710,0
)
*325 (MRCItem
litem &290
pos 17
dimension 20
uid 10712,0
)
*326 (MRCItem
litem &291
pos 11
dimension 20
uid 10714,0
)
*327 (MRCItem
litem &292
pos 5
dimension 20
uid 10716,0
)
*328 (MRCItem
litem &293
pos 18
dimension 20
uid 10720,0
)
*329 (MRCItem
litem &294
pos 19
dimension 20
uid 10722,0
)
*330 (MRCItem
litem &295
pos 20
dimension 20
uid 10724,0
)
*331 (MRCItem
litem &296
pos 21
dimension 20
uid 10726,0
)
*332 (MRCItem
litem &297
pos 6
dimension 20
uid 10728,0
)
*333 (MRCItem
litem &298
pos 22
dimension 20
uid 10730,0
)
*334 (MRCItem
litem &299
pos 23
dimension 20
uid 10732,0
)
*335 (MRCItem
litem &300
pos 24
dimension 20
uid 10734,0
)
*336 (MRCItem
litem &301
pos 25
dimension 20
uid 10736,0
)
*337 (MRCItem
litem &302
pos 7
dimension 20
uid 10738,0
)
*338 (MRCItem
litem &303
pos 3
dimension 20
uid 10740,0
)
*339 (MRCItem
litem &304
pos 8
dimension 20
uid 10772,0
)
*340 (MRCItem
litem &305
pos 0
dimension 20
uid 13126,0
)
*341 (MRCItem
litem &306
pos 2
dimension 20
uid 13371,0
)
*342 (MRCItem
litem &307
pos 26
dimension 20
uid 16727,0
)
*343 (MRCItem
litem &308
pos 27
dimension 20
uid 16729,0
)
*344 (MRCItem
litem &309
pos 28
dimension 20
uid 17173,0
)
*345 (MRCItem
litem &310
pos 29
dimension 20
uid 17557,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 10793,0
optionalChildren [
*346 (MRCItem
litem &272
pos 0
dimension 20
uid 10794,0
)
*347 (MRCItem
litem &274
pos 1
dimension 50
uid 10795,0
)
*348 (MRCItem
litem &275
pos 2
dimension 100
uid 10796,0
)
*349 (MRCItem
litem &276
pos 3
dimension 50
uid 10797,0
)
*350 (MRCItem
litem &277
pos 4
dimension 100
uid 10798,0
)
*351 (MRCItem
litem &278
pos 5
dimension 100
uid 10799,0
)
*352 (MRCItem
litem &279
pos 6
dimension 50
uid 10800,0
)
*353 (MRCItem
litem &280
pos 7
dimension 80
uid 10801,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 10788,0
vaOverrides [
]
)
]
)
uid 10773,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *354 (LEmptyRow
)
uid 10803,0
optionalChildren [
*355 (RefLabelRowHdr
)
*356 (TitleRowHdr
)
*357 (FilterRowHdr
)
*358 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*359 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*360 (GroupColHdr
tm "GroupColHdrMgr"
)
*361 (NameColHdr
tm "GenericNameColHdrMgr"
)
*362 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*363 (InitColHdr
tm "GenericValueColHdrMgr"
)
*364 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*365 (EolColHdr
tm "GenericEolColHdrMgr"
)
*366 (LogGeneric
generic (GiElement
name "testOutBitNb"
type "positive"
value "16"
)
uid 12900,0
)
*367 (LogGeneric
generic (GiElement
name "pindex"
type "natural"
value ""
)
uid 13874,0
)
*368 (LogGeneric
generic (GiElement
name "paddr"
type "positive"
value ""
)
uid 14113,0
)
*369 (LogGeneric
generic (GiElement
name "pmask"
type "positive"
value "16#FFF#"
)
uid 14352,0
)
*370 (LogGeneric
generic (GiElement
name "updatePeriodBitNb"
type "positive"
value "16"
)
uid 15331,0
)
*371 (LogGeneric
generic (GiElement
name "signalBitNb"
type "positive"
value "16"
)
uid 16243,0
)
*372 (LogGeneric
generic (GiElement
name "patternAddressBitNb"
type "positive"
value "8"
)
uid 17007,0
)
]
)
pdm (PhysicalDM
uid 10815,0
optionalChildren [
*373 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *374 (MRCItem
litem &354
pos 7
dimension 20
)
uid 10817,0
optionalChildren [
*375 (MRCItem
litem &355
pos 0
dimension 20
uid 10818,0
)
*376 (MRCItem
litem &356
pos 1
dimension 23
uid 10819,0
)
*377 (MRCItem
litem &357
pos 2
hidden 1
dimension 20
uid 10820,0
)
*378 (MRCItem
litem &366
pos 6
dimension 20
uid 12899,0
)
*379 (MRCItem
litem &367
pos 0
dimension 20
uid 13873,0
)
*380 (MRCItem
litem &368
pos 1
dimension 20
uid 14112,0
)
*381 (MRCItem
litem &369
pos 2
dimension 20
uid 14351,0
)
*382 (MRCItem
litem &370
pos 3
dimension 20
uid 15330,0
)
*383 (MRCItem
litem &371
pos 4
dimension 20
uid 16242,0
)
*384 (MRCItem
litem &372
pos 5
dimension 20
uid 17006,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 10821,0
optionalChildren [
*385 (MRCItem
litem &358
pos 0
dimension 20
uid 10822,0
)
*386 (MRCItem
litem &360
pos 1
dimension 50
uid 10823,0
)
*387 (MRCItem
litem &361
pos 2
dimension 100
uid 10824,0
)
*388 (MRCItem
litem &362
pos 3
dimension 100
uid 10825,0
)
*389 (MRCItem
litem &363
pos 4
dimension 50
uid 10826,0
)
*390 (MRCItem
litem &364
pos 5
dimension 50
uid 10827,0
)
*391 (MRCItem
litem &365
pos 6
dimension 80
uid 10828,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 10816,0
vaOverrides [
]
)
]
)
uid 10802,0
type 1
)
activeModelName "BlockDiag"
)