1896 lines
23 KiB
Plaintext
1896 lines
23 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "27.1"
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appVersion "2019.2 (Build 5)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 12,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 53,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
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*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*12 (InitColHdr
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tm "InitColHdrMgr"
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)
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*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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*14 (LogPort
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port (LogicalPort
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decl (Decl
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n "selSinCos_n"
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t "std_ulogic"
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o 4
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suid 1,0
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)
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)
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uid 109,0
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)
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*15 (LogPort
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port (LogicalPort
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 2
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suid 2,0
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)
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)
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uid 111,0
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)
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*16 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "spare"
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t "std_ulogic_vector"
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b "(1 TO 17)"
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o 8
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suid 3,0
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)
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)
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uid 113,0
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)
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*17 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "yOut"
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t "std_ulogic"
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o 10
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suid 5,0
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)
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)
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uid 117,0
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)
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*18 (LogPort
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port (LogicalPort
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decl (Decl
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n "reset_N"
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t "std_ulogic"
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o 3
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suid 6,0
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)
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)
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uid 119,0
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)
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*19 (LogPort
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port (LogicalPort
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m 1
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|
decl (Decl
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n "LED1"
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t "std_ulogic"
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o 5
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suid 8,0
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)
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)
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uid 123,0
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)
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*20 (LogPort
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port (LogicalPort
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m 1
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|
decl (Decl
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n "LED2"
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|
t "std_ulogic"
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o 6
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suid 9,0
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)
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)
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uid 125,0
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)
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*21 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "xOut"
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t "std_ulogic"
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o 9
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suid 10,0
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)
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)
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uid 127,0
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)
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*22 (LogPort
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port (LogicalPort
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decl (Decl
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n "RxD"
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t "std_ulogic"
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o 1
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suid 11,0
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)
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)
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uid 340,0
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)
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*23 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "TxD"
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t "std_ulogic"
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o 7
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suid 12,0
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)
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)
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uid 342,0
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)
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]
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)
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pdm (PhysicalDM
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displayShortBounds 1
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editShortBounds 1
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uid 66,0
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optionalChildren [
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*24 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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emptyMRCItem *25 (MRCItem
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litem &1
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pos 3
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dimension 20
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)
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uid 68,0
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optionalChildren [
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*26 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 69,0
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)
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*27 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 70,0
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)
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*28 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 71,0
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)
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*29 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 108,0
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)
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*30 (MRCItem
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litem &15
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pos 1
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dimension 20
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uid 110,0
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)
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*31 (MRCItem
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litem &16
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pos 2
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dimension 20
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uid 112,0
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)
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*32 (MRCItem
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litem &17
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pos 3
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dimension 20
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uid 116,0
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)
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*33 (MRCItem
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litem &18
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pos 4
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dimension 20
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uid 118,0
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)
|
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*34 (MRCItem
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litem &19
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pos 5
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dimension 20
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uid 122,0
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)
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*35 (MRCItem
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litem &20
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pos 6
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dimension 20
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|
uid 124,0
|
|
)
|
|
*36 (MRCItem
|
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litem &21
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pos 7
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|
dimension 20
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uid 126,0
|
|
)
|
|
*37 (MRCItem
|
|
litem &22
|
|
pos 8
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dimension 20
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|
uid 339,0
|
|
)
|
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*38 (MRCItem
|
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litem &23
|
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pos 9
|
|
dimension 20
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|
uid 341,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
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textAngle 90
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)
|
|
uid 72,0
|
|
optionalChildren [
|
|
*39 (MRCItem
|
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litem &5
|
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pos 0
|
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dimension 20
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uid 73,0
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|
)
|
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*40 (MRCItem
|
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litem &7
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pos 1
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dimension 50
|
|
uid 74,0
|
|
)
|
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*41 (MRCItem
|
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litem &8
|
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pos 2
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dimension 100
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|
uid 75,0
|
|
)
|
|
*42 (MRCItem
|
|
litem &9
|
|
pos 3
|
|
dimension 50
|
|
uid 76,0
|
|
)
|
|
*43 (MRCItem
|
|
litem &10
|
|
pos 4
|
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dimension 100
|
|
uid 77,0
|
|
)
|
|
*44 (MRCItem
|
|
litem &11
|
|
pos 5
|
|
dimension 100
|
|
uid 78,0
|
|
)
|
|
*45 (MRCItem
|
|
litem &12
|
|
pos 6
|
|
dimension 50
|
|
uid 79,0
|
|
)
|
|
*46 (MRCItem
|
|
litem &13
|
|
pos 7
|
|
dimension 80
|
|
uid 80,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 67,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 52,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *47 (LEmptyRow
|
|
)
|
|
uid 82,0
|
|
optionalChildren [
|
|
*48 (RefLabelRowHdr
|
|
)
|
|
*49 (TitleRowHdr
|
|
)
|
|
*50 (FilterRowHdr
|
|
)
|
|
*51 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*52 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*53 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*54 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*55 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*56 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*57 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*58 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 94,0
|
|
optionalChildren [
|
|
*59 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *60 (MRCItem
|
|
litem &47
|
|
pos 3
|
|
dimension 20
|
|
)
|
|
uid 96,0
|
|
optionalChildren [
|
|
*61 (MRCItem
|
|
litem &48
|
|
pos 0
|
|
dimension 20
|
|
uid 97,0
|
|
)
|
|
*62 (MRCItem
|
|
litem &49
|
|
pos 1
|
|
dimension 23
|
|
uid 98,0
|
|
)
|
|
*63 (MRCItem
|
|
litem &50
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 99,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 100,0
|
|
optionalChildren [
|
|
*64 (MRCItem
|
|
litem &51
|
|
pos 0
|
|
dimension 20
|
|
uid 101,0
|
|
)
|
|
*65 (MRCItem
|
|
litem &53
|
|
pos 1
|
|
dimension 50
|
|
uid 102,0
|
|
)
|
|
*66 (MRCItem
|
|
litem &54
|
|
pos 2
|
|
dimension 100
|
|
uid 103,0
|
|
)
|
|
*67 (MRCItem
|
|
litem &55
|
|
pos 3
|
|
dimension 100
|
|
uid 104,0
|
|
)
|
|
*68 (MRCItem
|
|
litem &56
|
|
pos 4
|
|
dimension 50
|
|
uid 105,0
|
|
)
|
|
*69 (MRCItem
|
|
litem &57
|
|
pos 5
|
|
dimension 50
|
|
uid 106,0
|
|
)
|
|
*70 (MRCItem
|
|
litem &58
|
|
pos 6
|
|
dimension 80
|
|
uid 107,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 95,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 81,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\@so@c_ebs3\\symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\@so@c_ebs3\\symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\@so@c_ebs3"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\SoC_ebs3"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "08.05.2023"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "lun."
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "lundi"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "08"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "SoC_ebs3"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "08.05.2023"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "10:21:25"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "Board"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Concatenation"
|
|
value "$HDS_PROJECT_DIR/../Board/concat"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/Board"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "05"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "SoC_ebs3"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "mai"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "mai"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\@so@c_ebs3\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\SoC_ebs3\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "10:21:25"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "SoC_ebs3"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2023"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "23"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
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uid 51,0
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optionalChildren [
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uid 8,0
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optionalChildren [
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uid 128,0
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ps "OnEdgeStrategy"
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fg "0,65535,0"
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tm "CptPortNameMgr"
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st "selSinCos_n : IN std_ulogic ;
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thePort (LogicalPort
|
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decl (Decl
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n "selSinCos_n"
|
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t "std_ulogic"
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suid 1,0
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uid 133,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 134,0
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va (VaSet
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xt "14250,7625,15000,8375"
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tg (CPTG
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uid 135,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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font "Verdana,12,0"
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st "clock"
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blo "16000,8500"
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tm "CptPortNameMgr"
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font "Courier New,8,0"
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st "clock : IN std_ulogic ;
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thePort (LogicalPort
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decl (Decl
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n "clock"
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t "std_ulogic"
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*74 (CptPort
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ps "OnEdgeStrategy"
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shape (Triangle
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ps "CptPortTextPlaceStrategy"
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st "spare : (1:17)"
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ju 2
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blo "43000,7500"
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tm "CptPortNameMgr"
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va (VaSet
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font "Courier New,8,0"
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thePort (LogicalPort
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m 1
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decl (Decl
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n "spare"
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t "std_ulogic_vector"
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b "(1 TO 17)"
|
|
o 8
|
|
suid 3,0
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)
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)
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*75 (CptPort
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uid 148,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 149,0
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ro 90
|
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va (VaSet
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vasetType 1
|
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fg "0,65535,0"
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)
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xt "44000,7625,44750,8375"
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tg (CPTG
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uid 150,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 151,0
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va (VaSet
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font "Verdana,12,0"
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xt "39200,7300,43000,8700"
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st "yOut"
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ju 2
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blo "43000,8500"
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tm "CptPortNameMgr"
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)
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dt (MLText
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uid 152,0
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va (VaSet
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font "Courier New,8,0"
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)
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xt "44000,9600,61500,10400"
|
|
st "yOut : OUT std_ulogic
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "yOut"
|
|
t "std_ulogic"
|
|
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|
suid 5,0
|
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)
|
|
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|
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)
|
|
*76 (CptPort
|
|
uid 153,0
|
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 154,0
|
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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xt "14250,9625,15000,10375"
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tg (CPTG
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uid 155,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 156,0
|
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va (VaSet
|
|
font "Verdana,12,0"
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)
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xt "16000,9300,21800,10700"
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st "reset_N"
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|
blo "16000,10500"
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tm "CptPortNameMgr"
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|
)
|
|
dt (MLText
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uid 157,0
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va (VaSet
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font "Courier New,8,0"
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)
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xt "44000,4000,62500,4800"
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st "reset_N : IN std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset_N"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 6,0
|
|
)
|
|
)
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)
|
|
*77 (CptPort
|
|
uid 163,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 164,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
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fg "0,65535,0"
|
|
)
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xt "44000,9625,44750,10375"
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)
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tg (CPTG
|
|
uid 165,0
|
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 166,0
|
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va (VaSet
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font "Verdana,12,0"
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)
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xt "39000,9300,43000,10700"
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|
st "LED1"
|
|
ju 2
|
|
blo "43000,10500"
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tm "CptPortNameMgr"
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|
)
|
|
)
|
|
dt (MLText
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uid 167,0
|
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va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,5600,62500,6400"
|
|
st "LED1 : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "LED1"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 8,0
|
|
)
|
|
)
|
|
)
|
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*78 (CptPort
|
|
uid 168,0
|
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 169,0
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ro 90
|
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
|
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xt "44000,10625,44750,11375"
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)
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tg (CPTG
|
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uid 170,0
|
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 171,0
|
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va (VaSet
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font "Verdana,12,0"
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)
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xt "39000,10300,43000,11700"
|
|
st "LED2"
|
|
ju 2
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|
blo "43000,11500"
|
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tm "CptPortNameMgr"
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)
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)
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dt (MLText
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uid 172,0
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va (VaSet
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font "Courier New,8,0"
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)
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xt "44000,6400,62500,7200"
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|
st "LED2 : OUT std_ulogic ;
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|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
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n "LED2"
|
|
t "std_ulogic"
|
|
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|
|
suid 9,0
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)
|
|
)
|
|
)
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*79 (CptPort
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uid 173,0
|
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 174,0
|
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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tg (CPTG
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uid 175,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 176,0
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va (VaSet
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font "Verdana,12,0"
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)
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st "xOut"
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ju 2
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|
blo "43000,12500"
|
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tm "CptPortNameMgr"
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)
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)
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dt (MLText
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uid 177,0
|
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va (VaSet
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font "Courier New,8,0"
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)
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xt "44000,8800,62500,9600"
|
|
st "xOut : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "xOut"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 10,0
|
|
)
|
|
)
|
|
)
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*80 (CptPort
|
|
uid 343,0
|
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 344,0
|
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ro 90
|
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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)
|
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tg (CPTG
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uid 345,0
|
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 346,0
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va (VaSet
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font "Verdana,12,0"
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)
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st "RxD"
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blo "16000,11500"
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tm "CptPortNameMgr"
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|
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)
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dt (MLText
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uid 347,0
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va (VaSet
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font "Courier New,8,0"
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)
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xt "44000,2400,62500,3200"
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st "RxD : IN std_ulogic ;
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|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "RxD"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 11,0
|
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)
|
|
)
|
|
)
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|
*81 (CptPort
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uid 348,0
|
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ps "OnEdgeStrategy"
|
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shape (Triangle
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uid 349,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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|
xt "44000,12625,44750,13375"
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)
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tg (CPTG
|
|
uid 350,0
|
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 351,0
|
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va (VaSet
|
|
font "Verdana,12,0"
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)
|
|
xt "39900,12300,43000,13700"
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|
st "TxD"
|
|
ju 2
|
|
blo "43000,13500"
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tm "CptPortNameMgr"
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)
|
|
)
|
|
dt (MLText
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|
uid 352,0
|
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va (VaSet
|
|
font "Courier New,8,0"
|
|
)
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|
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|
st "TxD : OUT std_ulogic ;
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|
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|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
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n "TxD"
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|
suid 12,0
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va (VaSet
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)
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gi *82 (GenericInterface
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matrix (Matrix
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text (MLText
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header "Generic Declarations"
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showHdrWhenContentsEmpty 1
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)
|
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elements [
|
|
]
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portInstanceVisAsIs 1
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portInstanceVis (PortSigDisplay
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sIVOD 1
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portVis (PortSigDisplay
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sIVOD 1
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uid 16,0
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uid 18,0
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shape (Rectangle
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uid 19,0
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sl 0
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va (VaSet
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|
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text (MLText
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