109 lines
3.2 KiB
Plaintext
109 lines
3.2 KiB
Plaintext
--
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-- VHDL Architecture SplineInterpolator_test.sineGen_tb.struct
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--
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- at - 14:41:39 28.04.2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.ALL;
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LIBRARY SplineInterpolator;
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LIBRARY SplineInterpolator_test;
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ARCHITECTURE struct OF sineGen_tb IS
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-- Architecture declarations
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constant signalBitNb: positive := 16;
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constant phaseBitNb: positive := 10;
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constant clockFrequency: real := 60.0E6;
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--constant clockFrequency: real := 66.0E6;
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-- Internal signal declarations
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SIGNAL clock : std_ulogic;
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SIGNAL reset : std_ulogic;
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SIGNAL sawtooth : unsigned(signalBitNb-1 DOWNTO 0);
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SIGNAL sine : unsigned(signalBitNb-1 DOWNTO 0);
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SIGNAL square : unsigned(signalBitNb-1 DOWNTO 0);
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SIGNAL step : unsigned(phaseBitNb-1 DOWNTO 0);
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SIGNAL triangle : unsigned(signalBitNb-1 DOWNTO 0);
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-- Component Declarations
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COMPONENT sineGen
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GENERIC (
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signalBitNb : positive := 16;
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phaseBitNb : positive := 10
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);
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PORT (
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clock : IN std_ulogic ;
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reset : IN std_ulogic ;
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step : IN unsigned (phaseBitNb-1 DOWNTO 0);
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sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0);
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sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
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square : OUT unsigned (signalBitNb-1 DOWNTO 0);
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triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT sineGen_tester
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GENERIC (
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signalBitNb : positive := 16;
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phaseBitNb : positive := 10;
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clockFrequency : real := 60.0E6
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);
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PORT (
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sawtooth : IN unsigned (signalBitNb-1 DOWNTO 0);
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sine : IN unsigned (signalBitNb-1 DOWNTO 0);
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square : IN unsigned (signalBitNb-1 DOWNTO 0);
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triangle : IN unsigned (signalBitNb-1 DOWNTO 0);
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clock : OUT std_ulogic ;
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reset : OUT std_ulogic ;
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step : OUT unsigned (phaseBitNb-1 DOWNTO 0)
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);
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END COMPONENT;
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-- Optional embedded configurations
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-- pragma synthesis_off
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FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen;
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FOR ALL : sineGen_tester USE ENTITY SplineInterpolator_test.sineGen_tester;
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-- pragma synthesis_on
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BEGIN
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-- Instance port mappings.
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I_DUT : sineGen
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GENERIC MAP (
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signalBitNb => signalBitNb,
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phaseBitNb => phaseBitNb
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)
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PORT MAP (
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clock => clock,
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reset => reset,
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step => step,
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sawtooth => sawtooth,
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sine => sine,
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square => square,
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triangle => triangle
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);
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I_tb : sineGen_tester
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GENERIC MAP (
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signalBitNb => signalBitNb,
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phaseBitNb => phaseBitNb,
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clockFrequency => clockFrequency
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)
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PORT MAP (
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sawtooth => sawtooth,
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sine => sine,
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square => square,
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triangle => triangle,
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clock => clock,
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reset => reset,
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step => step
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);
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END struct;
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