57 lines
2.2 KiB
VHDL
57 lines
2.2 KiB
VHDL
ARCHITECTURE test OF toggler_tester IS
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constant clockFrequency : real := 66.0E6;
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constant clockPeriod : time := 1.0/clockFrequency * 1 sec;
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signal clock_int : std_ulogic := '1';
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset <= '1', '0' after 3*clockPeriod;
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clock_int <= not clock_int after clockPeriod/2;
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clock <= transport clock_int after clockPeriod*9/10;
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------------------------------------------------------------------------------
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-- input signal
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process
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begin
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input <= '0';
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wait for 10*clockPeriod;
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-- transition 0 to 1
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input <= '1',
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'0' after 1*clockPeriod,
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'1' after 3*clockPeriod,
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'0' after 5*clockPeriod,
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'1' after 6*clockPeriod,
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'0' after 8*clockPeriod,
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'1' after 10*clockPeriod;
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wait for 50*clockPeriod;
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-- transition 1 to 0
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input <= '0',
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'1' after 1*clockPeriod,
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'0' after 3*clockPeriod,
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'1' after 5*clockPeriod,
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'0' after 6*clockPeriod,
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'1' after 8*clockPeriod,
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'0' after 10*clockPeriod;
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wait for 50*clockPeriod;
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-- short 1 pulse
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input <= '1',
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'0' after 1*clockPeriod,
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'1' after 3*clockPeriod,
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'0' after 5*clockPeriod,
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'1' after 6*clockPeriod,
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'0' after 8*clockPeriod;
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wait for 50*clockPeriod;
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-- further toggle commands
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input <= '1', '0' after clockPeriod;
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wait for 50*clockPeriod;
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input <= '1', '0' after clockPeriod;
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wait for 50*clockPeriod;
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-- short 1 pulse
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-- end of simulation
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wait;
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end process;
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END ARCHITECTURE test;
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