142 lines
5.2 KiB
VHDL
142 lines
5.2 KiB
VHDL
--
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-- VHDL Architecture Common_test.debounce_tester.test
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--
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-- Created:
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-- by - remy.borgeat.UNKNOWN (WE10993)
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-- at - 15:30:08 12.01.2024
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--
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-- using Mentor Graphics HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY std;
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USE std.textio.ALL;
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LIBRARY ieee;
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USE ieee.std_logic_textio.ALL;
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USE ieee.math_real.all;
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LIBRARY Common_test;
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USE Common_test.testutils.all;
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ARCHITECTURE test OF debounce_tester IS
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constant clockPeriod : time := 1.0/g_clockFrequency * 1 sec;
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signal clock_int : std_ulogic := '1';
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constant DELAY: positive := integer(ceil(((real(g_debounceTime / 1 ps) / 1.0e12) * g_clockFrequency) / real(g_minConsecutiveStateCount))) - 1;
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signal testInfo : string(1 to 40) := (others => ' ');
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset <= '1', '0' after 3*clockPeriod;
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clock_int <= not clock_int after clockPeriod/2;
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clock <= transport clock_int after clockPeriod*9/10;
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------------------------------------------------------------------------------
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-- input signal
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process
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begin
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-- startup
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testInfo <= pad("Init", testInfo'length);
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input <= '0';
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wait until reset = '0';
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wait until clock'event and clock = '1';
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assert (debounced = not g_activeState)
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report "Startup value should be " & to_string(not g_activeState)
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severity failure;
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assert (debounced = g_activeState)
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report "Value OK"
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severity note;
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-- transition 0 to 1
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testInfo <= pad("0 to 1", testInfo'length);
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input <= '1';
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wait for (g_minConsecutiveStateCount/2) * DELAY * clockPeriod;
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assert (debounced = not g_activeState)
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report "Value should be " & to_string(not g_activeState)
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severity failure;
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assert (debounced = g_activeState)
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report "Value OK"
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severity note;
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wait for ((g_minConsecutiveStateCount/2) + 1) * DELAY * clockPeriod;
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assert (debounced = g_activeState)
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report "Value should be " & to_string(g_activeState)
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severity failure;
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assert (debounced = not g_activeState)
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report "Value OK"
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severity note;
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wait for 100*clockPeriod;
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-- transition 1 to 0
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testInfo <= pad("1 to 0", testInfo'length);
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input <= '0';
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wait for (g_minConsecutiveStateCount/2) * DELAY * clockPeriod;
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assert (debounced = g_activeState)
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report "Value should be " & to_string(g_activeState)
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severity failure;
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assert (debounced = not g_activeState)
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report "Value OK"
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severity note;
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wait for ((g_minConsecutiveStateCount/2) + 1) * DELAY * clockPeriod;
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assert (debounced = not g_activeState)
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report "Value should be " & to_string(not g_activeState)
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severity failure;
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assert (debounced = g_activeState)
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report "Value OK"
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severity note;
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wait for 100*clockPeriod;
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-- 0 w. glitches
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testInfo <= pad("0 glitches", testInfo'length);
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input <= '0',
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'1' after (g_minConsecutiveStateCount/4) * DELAY * clockPeriod,
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'0' after (g_minConsecutiveStateCount/2) * DELAY * clockPeriod,
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'1' after ((g_minConsecutiveStateCount/4)*3) * DELAY * clockPeriod,
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'0' after (g_minConsecutiveStateCount) * DELAY * clockPeriod;
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wait for 2 * (g_minConsecutiveStateCount) * DELAY * clockPeriod;
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assert (debounced = not g_activeState)
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report "Value should be " & to_string(not g_activeState)
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severity failure;
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assert (debounced = g_activeState)
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report "Value OK"
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severity note;
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testInfo <= pad("Back to 1", testInfo'length);
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input <= '1';
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wait for g_minConsecutiveStateCount * DELAY * clockPeriod;
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assert (debounced = g_activeState)
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report "Value should be " & to_string(g_activeState)
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severity failure;
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assert (debounced = not g_activeState)
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report "Value OK"
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severity note;
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-- 1 w. glitches
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testInfo <= pad("1 glitches", testInfo'length);
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input <= '1',
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'0' after (g_minConsecutiveStateCount/4) * DELAY * clockPeriod,
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'1' after (g_minConsecutiveStateCount/2) * DELAY * clockPeriod,
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'0' after ((g_minConsecutiveStateCount/4)*3) * DELAY * clockPeriod,
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'1' after (g_minConsecutiveStateCount) * DELAY * clockPeriod;
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wait for 2 * (g_minConsecutiveStateCount) * DELAY * clockPeriod;
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assert (debounced = g_activeState)
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report "Value should be " & to_string(g_activeState)
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severity failure;
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assert (debounced = not g_activeState)
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report "Value OK"
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severity note;
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-- end of simulation
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testInfo <= pad("End", testInfo'length);
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wait for 10*clockPeriod;
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assert false
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report "End of simulation"
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severity failure;
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wait;
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end process;
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END ARCHITECTURE test;
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