2117 lines
26 KiB
Plaintext
2117 lines
26 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "NUMERIC_STD"
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)
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(DmPackageRef
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library "AhbLite"
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unitName "ahbLite"
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)
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]
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libraryRefs [
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"ieee"
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"AhbLite"
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]
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)
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version "27.1"
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appVersion "2019.2 (Build 5)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 30,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 53,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
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*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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|
*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*12 (InitColHdr
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tm "InitColHdrMgr"
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)
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*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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*14 (LogPort
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port (LogicalPort
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 1
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suid 19,0
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)
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)
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uid 432,0
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)
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*15 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "hAddr"
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t "unsigned"
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b "( ahbAddressBitNb-1 DOWNTO 0 )"
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o 6
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suid 20,0
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)
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)
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uid 434,0
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)
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*16 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "hClk"
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t "std_uLogic"
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o 7
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suid 21,0
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)
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)
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uid 436,0
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)
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*17 (LogPort
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port (LogicalPort
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decl (Decl
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n "hRData"
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t "std_ulogic_vector"
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b "(ahbDataBitNb-1 DOWNTO 0)"
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o 2
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suid 22,0
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)
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)
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uid 438,0
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)
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*18 (LogPort
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port (LogicalPort
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decl (Decl
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n "hReady"
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t "std_uLogic"
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o 3
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suid 23,0
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)
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)
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uid 440,0
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)
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*19 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "hReset_n"
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t "std_uLogic"
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o 8
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suid 24,0
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)
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)
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uid 442,0
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)
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*20 (LogPort
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port (LogicalPort
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|
decl (Decl
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n "hResp"
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t "std_uLogic"
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o 4
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suid 25,0
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)
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)
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uid 444,0
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)
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*21 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "hSel"
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t "std_uLogic"
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o 9
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suid 26,0
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)
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)
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uid 446,0
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)
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*22 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "hTrans"
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t "std_ulogic_vector"
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b "(ahbTransBitNb-1 DOWNTO 0)"
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o 10
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suid 27,0
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)
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)
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uid 448,0
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)
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*23 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "hWData"
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t "std_ulogic_vector"
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b "(ahbDataBitNb-1 DOWNTO 0)"
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o 11
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suid 28,0
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)
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)
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uid 450,0
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)
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*24 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "hWrite"
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t "std_uLogic"
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o 12
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suid 29,0
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)
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)
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uid 452,0
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)
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*25 (LogPort
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|
port (LogicalPort
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|
decl (Decl
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n "reset"
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|
t "std_ulogic"
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|
o 5
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suid 30,0
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)
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)
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uid 454,0
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)
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]
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)
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pdm (PhysicalDM
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|
displayShortBounds 1
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editShortBounds 1
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uid 66,0
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optionalChildren [
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*26 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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|
cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
|
|
cellVa (MVa
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|
cellColor "65535,65535,65535"
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|
fontColor "0,0,0"
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font "Tahoma,10,0"
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)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
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|
fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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emptyMRCItem *27 (MRCItem
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litem &1
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pos 12
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dimension 20
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)
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uid 68,0
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|
optionalChildren [
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*28 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 69,0
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)
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*29 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 70,0
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)
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*30 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 71,0
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)
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*31 (MRCItem
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litem &14
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pos 0
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dimension 20
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|
uid 433,0
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)
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|
*32 (MRCItem
|
|
litem &15
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pos 1
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dimension 20
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uid 435,0
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)
|
|
*33 (MRCItem
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litem &16
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pos 2
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dimension 20
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uid 437,0
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)
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*34 (MRCItem
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litem &17
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pos 3
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dimension 20
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uid 439,0
|
|
)
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|
*35 (MRCItem
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litem &18
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pos 4
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dimension 20
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uid 441,0
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)
|
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*36 (MRCItem
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litem &19
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pos 5
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dimension 20
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uid 443,0
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)
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*37 (MRCItem
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litem &20
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pos 6
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dimension 20
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uid 445,0
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)
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*38 (MRCItem
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litem &21
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pos 7
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dimension 20
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uid 447,0
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)
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*39 (MRCItem
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litem &22
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pos 8
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dimension 20
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uid 449,0
|
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)
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*40 (MRCItem
|
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litem &23
|
|
pos 9
|
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dimension 20
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uid 451,0
|
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)
|
|
*41 (MRCItem
|
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litem &24
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pos 10
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dimension 20
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uid 453,0
|
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)
|
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*42 (MRCItem
|
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litem &25
|
|
pos 11
|
|
dimension 20
|
|
uid 455,0
|
|
)
|
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]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
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)
|
|
uid 72,0
|
|
optionalChildren [
|
|
*43 (MRCItem
|
|
litem &5
|
|
pos 0
|
|
dimension 20
|
|
uid 73,0
|
|
)
|
|
*44 (MRCItem
|
|
litem &7
|
|
pos 1
|
|
dimension 50
|
|
uid 74,0
|
|
)
|
|
*45 (MRCItem
|
|
litem &8
|
|
pos 2
|
|
dimension 100
|
|
uid 75,0
|
|
)
|
|
*46 (MRCItem
|
|
litem &9
|
|
pos 3
|
|
dimension 50
|
|
uid 76,0
|
|
)
|
|
*47 (MRCItem
|
|
litem &10
|
|
pos 4
|
|
dimension 100
|
|
uid 77,0
|
|
)
|
|
*48 (MRCItem
|
|
litem &11
|
|
pos 5
|
|
dimension 100
|
|
uid 78,0
|
|
)
|
|
*49 (MRCItem
|
|
litem &12
|
|
pos 6
|
|
dimension 50
|
|
uid 79,0
|
|
)
|
|
*50 (MRCItem
|
|
litem &13
|
|
pos 7
|
|
dimension 80
|
|
uid 80,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 67,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 52,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *51 (LEmptyRow
|
|
)
|
|
uid 82,0
|
|
optionalChildren [
|
|
*52 (RefLabelRowHdr
|
|
)
|
|
*53 (TitleRowHdr
|
|
)
|
|
*54 (FilterRowHdr
|
|
)
|
|
*55 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*56 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*57 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*58 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*59 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*60 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*61 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*62 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*63 (LogGeneric
|
|
generic (GiElement
|
|
name "driverVerbosity"
|
|
type "integer"
|
|
value ""
|
|
)
|
|
uid 525,0
|
|
)
|
|
*64 (LogGeneric
|
|
generic (GiElement
|
|
name "monitorVerbosity"
|
|
type "integer"
|
|
value ""
|
|
)
|
|
uid 527,0
|
|
)
|
|
*65 (LogGeneric
|
|
generic (GiElement
|
|
name "driverFileSpec"
|
|
type "string"
|
|
value ""
|
|
)
|
|
uid 529,0
|
|
)
|
|
*66 (LogGeneric
|
|
generic (GiElement
|
|
name "monitorFileSpec"
|
|
type "string"
|
|
value ""
|
|
)
|
|
uid 531,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 94,0
|
|
optionalChildren [
|
|
*67 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *68 (MRCItem
|
|
litem &51
|
|
pos 4
|
|
dimension 20
|
|
)
|
|
uid 96,0
|
|
optionalChildren [
|
|
*69 (MRCItem
|
|
litem &52
|
|
pos 0
|
|
dimension 20
|
|
uid 97,0
|
|
)
|
|
*70 (MRCItem
|
|
litem &53
|
|
pos 1
|
|
dimension 23
|
|
uid 98,0
|
|
)
|
|
*71 (MRCItem
|
|
litem &54
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 99,0
|
|
)
|
|
*72 (MRCItem
|
|
litem &63
|
|
pos 0
|
|
dimension 20
|
|
uid 526,0
|
|
)
|
|
*73 (MRCItem
|
|
litem &64
|
|
pos 2
|
|
dimension 20
|
|
uid 528,0
|
|
)
|
|
*74 (MRCItem
|
|
litem &65
|
|
pos 1
|
|
dimension 20
|
|
uid 530,0
|
|
)
|
|
*75 (MRCItem
|
|
litem &66
|
|
pos 3
|
|
dimension 20
|
|
uid 532,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 100,0
|
|
optionalChildren [
|
|
*76 (MRCItem
|
|
litem &55
|
|
pos 0
|
|
dimension 20
|
|
uid 101,0
|
|
)
|
|
*77 (MRCItem
|
|
litem &57
|
|
pos 1
|
|
dimension 50
|
|
uid 102,0
|
|
)
|
|
*78 (MRCItem
|
|
litem &58
|
|
pos 2
|
|
dimension 100
|
|
uid 103,0
|
|
)
|
|
*79 (MRCItem
|
|
litem &59
|
|
pos 3
|
|
dimension 100
|
|
uid 104,0
|
|
)
|
|
*80 (MRCItem
|
|
litem &60
|
|
pos 4
|
|
dimension 50
|
|
uid 105,0
|
|
)
|
|
*81 (MRCItem
|
|
litem &61
|
|
pos 5
|
|
dimension 50
|
|
uid 106,0
|
|
)
|
|
*82 (MRCItem
|
|
litem &62
|
|
pos 6
|
|
dimension 80
|
|
uid 107,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 95,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 81,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\uvm@ahb@agent@hw\\symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\uvm@ahb@agent@hw\\symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\uvm@ahb@agent@hw"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\uvmAhbAgentHw"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "02/17/2020"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Mon"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Monday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "17"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "uvmAhbAgentHw"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "zas"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "02/17/2020"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "ZELL"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "17:08:42"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "ZELL"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "AhbLiteComponents_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/AhbLiteComponents_test"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "02"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "uvmAhbAgentHw"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Feb"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "February"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\uvm@ahb@agent@hw\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\uvmAhbAgentHw\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HDS_LIBS_DIR\\NanoBlaze\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_SCRATCH_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME\\win32"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "17:08:42"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "uvmAhbAgentHw"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "zas"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2020"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "20"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 51,0
|
|
optionalChildren [
|
|
*83 (SymbolBody
|
|
uid 8,0
|
|
optionalChildren [
|
|
*84 (CptPort
|
|
uid 372,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 373,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "37250,26625,38000,27375"
|
|
)
|
|
tg (CPTG
|
|
uid 374,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 375,0
|
|
va (VaSet
|
|
)
|
|
xt "39000,26400,42400,27600"
|
|
st "clock"
|
|
blo "39000,27400"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 376,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,9400,17000,10200"
|
|
st "clock : IN std_ulogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 19,0
|
|
)
|
|
)
|
|
)
|
|
*85 (CptPort
|
|
uid 377,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 378,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "54000,8625,54750,9375"
|
|
)
|
|
tg (CPTG
|
|
uid 379,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 380,0
|
|
va (VaSet
|
|
)
|
|
xt "49300,8400,53000,9600"
|
|
st "hAddr"
|
|
ju 2
|
|
blo "53000,9400"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 381,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,13400,31500,14200"
|
|
st "hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 ) ;"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hAddr"
|
|
t "unsigned"
|
|
b "( ahbAddressBitNb-1 DOWNTO 0 )"
|
|
o 6
|
|
suid 20,0
|
|
)
|
|
)
|
|
)
|
|
*86 (CptPort
|
|
uid 382,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 383,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "54000,26625,54750,27375"
|
|
)
|
|
tg (CPTG
|
|
uid 384,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 385,0
|
|
va (VaSet
|
|
)
|
|
xt "50000,26400,53000,27600"
|
|
st "hClk"
|
|
ju 2
|
|
blo "53000,27400"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 386,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,14200,17000,15000"
|
|
st "hClk : OUT std_uLogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hClk"
|
|
t "std_uLogic"
|
|
o 7
|
|
suid 21,0
|
|
)
|
|
)
|
|
)
|
|
*87 (CptPort
|
|
uid 387,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 388,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "54000,18625,54750,19375"
|
|
)
|
|
tg (CPTG
|
|
uid 389,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 390,0
|
|
va (VaSet
|
|
)
|
|
xt "48600,18400,53000,19600"
|
|
st "hRData"
|
|
ju 2
|
|
blo "53000,19400"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 391,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,10200,33500,11000"
|
|
st "hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hRData"
|
|
t "std_ulogic_vector"
|
|
b "(ahbDataBitNb-1 DOWNTO 0)"
|
|
o 2
|
|
suid 22,0
|
|
)
|
|
)
|
|
)
|
|
*88 (CptPort
|
|
uid 392,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 393,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "54000,20625,54750,21375"
|
|
)
|
|
tg (CPTG
|
|
uid 394,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 395,0
|
|
va (VaSet
|
|
)
|
|
xt "48600,20400,53000,21600"
|
|
st "hReady"
|
|
ju 2
|
|
blo "53000,21400"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 396,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,11000,17000,11800"
|
|
st "hReady : IN std_uLogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hReady"
|
|
t "std_uLogic"
|
|
o 3
|
|
suid 23,0
|
|
)
|
|
)
|
|
)
|
|
*89 (CptPort
|
|
uid 397,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 398,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "54000,28625,54750,29375"
|
|
)
|
|
tg (CPTG
|
|
uid 399,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 400,0
|
|
va (VaSet
|
|
)
|
|
xt "47600,28400,53000,29600"
|
|
st "hReset_n"
|
|
ju 2
|
|
blo "53000,29400"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 401,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,15000,17000,15800"
|
|
st "hReset_n : OUT std_uLogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hReset_n"
|
|
t "std_uLogic"
|
|
o 8
|
|
suid 24,0
|
|
)
|
|
)
|
|
)
|
|
*90 (CptPort
|
|
uid 402,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 403,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "54000,22625,54750,23375"
|
|
)
|
|
tg (CPTG
|
|
uid 404,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 405,0
|
|
va (VaSet
|
|
)
|
|
xt "49200,22400,53000,23600"
|
|
st "hResp"
|
|
ju 2
|
|
blo "53000,23400"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 406,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,11800,17000,12600"
|
|
st "hResp : IN std_uLogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hResp"
|
|
t "std_uLogic"
|
|
o 4
|
|
suid 25,0
|
|
)
|
|
)
|
|
)
|
|
*91 (CptPort
|
|
uid 407,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 408,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "54000,16625,54750,17375"
|
|
)
|
|
tg (CPTG
|
|
uid 409,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 410,0
|
|
va (VaSet
|
|
)
|
|
xt "50100,16400,53000,17600"
|
|
st "hSel"
|
|
ju 2
|
|
blo "53000,17400"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 411,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,15800,17000,16600"
|
|
st "hSel : OUT std_uLogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hSel"
|
|
t "std_uLogic"
|
|
o 9
|
|
suid 26,0
|
|
)
|
|
)
|
|
)
|
|
*92 (CptPort
|
|
uid 412,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 413,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "54000,12625,54750,13375"
|
|
)
|
|
tg (CPTG
|
|
uid 414,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 415,0
|
|
va (VaSet
|
|
)
|
|
xt "48800,12400,53000,13600"
|
|
st "hTrans"
|
|
ju 2
|
|
blo "53000,13400"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 416,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,16600,34000,17400"
|
|
st "hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0) ;"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hTrans"
|
|
t "std_ulogic_vector"
|
|
b "(ahbTransBitNb-1 DOWNTO 0)"
|
|
o 10
|
|
suid 27,0
|
|
)
|
|
)
|
|
)
|
|
*93 (CptPort
|
|
uid 417,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 418,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "54000,10625,54750,11375"
|
|
)
|
|
tg (CPTG
|
|
uid 419,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 420,0
|
|
va (VaSet
|
|
)
|
|
xt "48400,10400,53000,11600"
|
|
st "hWData"
|
|
ju 2
|
|
blo "53000,11400"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
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blo "1000,1800"
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tm "PanelText"
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)
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)
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)
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parentGraphicsRef (HdmGraphicsRef
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libraryName ""
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entityName ""
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viewName ""
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)
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defaultSymbolBody (SymbolBody
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shape (Rectangle
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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lineColor "0,32896,0"
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lineWidth 2
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)
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xt "15000,6000,33000,26000"
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)
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biTextGroup (BiTextGroup
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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first (Text
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va (VaSet
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font "Arial,8,1"
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)
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xt "22200,15000,25800,16000"
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st "<library>"
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blo "22200,15800"
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)
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second (Text
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va (VaSet
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font "Arial,8,1"
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)
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xt "22200,16000,24800,17000"
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st "<cell>"
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blo "22200,16800"
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)
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)
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gi *111 (GenericInterface
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ps "CenterOffsetStrategy"
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matrix (Matrix
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text (MLText
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va (VaSet
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font "Courier New,8,0"
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)
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xt "0,12000,11500,12800"
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st "Generic Declarations"
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)
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header "Generic Declarations"
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showHdrWhenContentsEmpty 1
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)
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elements [
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]
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)
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portInstanceVisAsIs 1
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portInstanceVis (PortSigDisplay
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sIVOD 1
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)
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portVis (PortSigDisplay
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sIVOD 1
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)
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)
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defaultCptPort (CptPort
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ps "OnEdgeStrategy"
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shape (Triangle
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "0,0,750,750"
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)
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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va (VaSet
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font "Verdana,12,0"
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)
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xt "0,750,2900,2150"
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st "In0"
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blo "0,1950"
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tm "CptPortNameMgr"
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)
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)
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dt (MLText
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va (VaSet
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font "Courier New,8,0"
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)
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)
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thePort (LogicalPort
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lang 11
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decl (Decl
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n "In0"
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b "(15 DOWNTO 0)"
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o 0
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)
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)
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)
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defaultCptPortBuffer (CptPort
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ps "OnEdgeStrategy"
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shape (Diamond
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va (VaSet
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bg "0,0,0"
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)
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xt "0,0,750,750"
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)
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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va (VaSet
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font "Verdana,12,0"
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)
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xt "0,750,5300,2150"
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st "Buffer0"
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blo "0,1950"
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tm "CptPortNameMgr"
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)
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dt (MLText
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va (VaSet
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font "Courier New,8,0"
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)
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)
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thePort (LogicalPort
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lang 11
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m 3
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decl (Decl
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n "Buffer0"
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t "unsigned"
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b "(15 DOWNTO 0)"
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o 0
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)
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)
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)
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DeclarativeBlock *112 (SymDeclBlock
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uid 1,0
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stg "SymDeclLayoutStrategy"
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declLabel (Text
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uid 2,0
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va (VaSet
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font "Arial,8,1"
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)
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xt "-2000,7400,3400,8400"
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st "Declarations"
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blo "-2000,8200"
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)
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portLabel (Text
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uid 3,0
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va (VaSet
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font "Arial,8,1"
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)
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xt "-2000,8400,700,9400"
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st "Ports:"
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blo "-2000,9200"
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)
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externalLabel (Text
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uid 4,0
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va (VaSet
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font "Arial,8,1"
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)
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xt "-2000,19000,400,20000"
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st "User:"
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blo "-2000,19800"
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)
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internalLabel (Text
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uid 6,0
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va (VaSet
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isHidden 1
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font "Arial,8,1"
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)
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xt "-2000,7400,3800,8400"
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st "Internal User:"
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blo "-2000,8200"
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)
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externalText (MLText
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uid 5,0
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va (VaSet
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font "Courier New,8,0"
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)
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xt "0,20000,0,20000"
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tm "SyDeclarativeTextMgr"
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)
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internalText (MLText
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uid 7,0
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va (VaSet
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isHidden 1
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font "Courier New,8,0"
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)
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xt "-2000,7400,-2000,7400"
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tm "SyDeclarativeTextMgr"
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)
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)
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lastUid 624,0
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okToSyncOnLoad 1
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OkToSyncGenericsOnLoad 1
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activeModelName "Symbol"
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)
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