32 lines
912 B
Plaintext
32 lines
912 B
Plaintext
-- VHDL Entity SplineInterpolator.interpolatorShiftRegister.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:00:24 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY interpolatorShiftRegister IS
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GENERIC(
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signalBitNb : positive := 16
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);
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PORT(
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clock : IN std_ulogic;
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reset : IN std_ulogic;
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shiftSamples : IN std_ulogic;
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sampleIn : IN signed (signalBitNb-1 DOWNTO 0);
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sample1 : OUT signed (signalBitNb-1 DOWNTO 0);
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sample2 : OUT signed (signalBitNb-1 DOWNTO 0);
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sample3 : OUT signed (signalBitNb-1 DOWNTO 0);
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sample4 : OUT signed (signalBitNb-1 DOWNTO 0)
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);
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-- Declarations
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END interpolatorShiftRegister ;
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