41 lines
1.1 KiB
VHDL
41 lines
1.1 KiB
VHDL
ARCHITECTURE masterVersion OF interpolatorShiftRegister IS
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-- signal sample4_int: signed(sampleIn'range);
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-- signal sample3_int: signed(sampleIn'range);
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-- signal sample2_int: signed(sampleIn'range);
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-- signal sample1_int: signed(sampleIn'range);
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type samplesArray is array(3 downto 0) of signed(sampleIn'range);
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signal samples: samplesArray;
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begin
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shiftThem: process(reset, clock)
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begin
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if reset = '1' then
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samples <= (others=>(others=>'0'));
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-- sample1_int <= (others => '0');
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-- sample2_int <= (others => '0');
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-- sample3_int <= (others => '0');
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-- sample4_int <= (others => '0');
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elsif rising_edge(clock) then
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if shiftSamples = '1' then
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-- sample1_int <= sample2_int;
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-- sample2_int <= sample3_int;
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-- sample3_int <= sample4_int;
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-- sample4_int <= sampleIn;
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samples(0) <= samples(1);
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samples(1) <= samples(2);
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samples(2) <= samples(3);
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samples(3) <= sampleIn;
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end if;
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end if;
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end process shiftThem;
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sample4 <= samples(3);
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sample3 <= samples(2);
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sample2 <= samples(1);
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sample1 <= samples(0);
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END ARCHITECTURE masterVersion;
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