57 lines
2.0 KiB
VHDL
57 lines
2.0 KiB
VHDL
ARCHITECTURE masterVersion OF interpolatorCalculatePolynom IS
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constant additionalBitNb: positive := 1;
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constant internalsBitNb: positive := signalBitNb + 3*oversamplingBitNb + 1
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+ additionalBitNb;
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signal x: signed(internalsBitNb-1 downto 0);
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signal u: signed(internalsBitNb-1 downto 0);
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signal v: signed(internalsBitNb-1 downto 0);
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signal w: signed(internalsBitNb-1 downto 0);
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BEGIN
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iterativePolynom: process(reset, clock)
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begin
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if reset = '1' then
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x <= (others => '0');
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u <= (others => '0');
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v <= (others => '0');
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w <= (others => '0');
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sampleOut <= (others => '0');
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elsif rising_edge(clock) then
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if en = '1' then
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if restartPolynom = '1' then
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x <= shift_left(resize(2*d, x'length), 3*oversamplingBitNb);
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u <= resize(a, u'length)
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+ shift_left(resize(b, u'length), oversamplingBitNb)
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+ shift_left(resize(c, u'length), 2*oversamplingBitNb);
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v <= resize(6*a, v'length)
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+ shift_left(resize(2*b, v'length), oversamplingBitNb);
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w <= resize(6*a, w'length);
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sampleOut <= resize(d, sampleOut'length);
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else
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x <= x + u;
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u <= u + v;
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v <= v + w;
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sampleOut <= resize(
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shift_right(x, 3*oversamplingBitNb+1), sampleOut'length
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);
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-- limit overflow
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if x(x'high downto x'high-additionalBitNb) = "01" then
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sampleOut <= not shift_left(
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resize("10", sampleOut'length), sampleOut'length-2
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);
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end if;
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-- limit underflow
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if x(x'high downto x'high-additionalBitNb) = "10" then
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sampleOut <= shift_left(
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resize("10", sampleOut'length), sampleOut'length-2
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);
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end if;
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end if;
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end if;
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end if;
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end process iterativePolynom;
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END ARCHITECTURE masterVersion;
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