4190 lines
50 KiB
Plaintext
4190 lines
50 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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|
instances [
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(Instance
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name "I_tester"
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duLibraryName "SystemOnChip_test"
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duName "beamerSoc_tester"
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elements [
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|
(GiElement
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|
name "ioNb"
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|
type "positive"
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|
value "ioNb"
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|
)
|
|
(GiElement
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|
name "signalBitNb"
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|
type "positive"
|
|
value "signalBitNb"
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|
)
|
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(GiElement
|
|
name "clockFrequency"
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|
type "real"
|
|
value "clockFrequency"
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|
)
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|
]
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mwi 0
|
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uid 1616,0
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)
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(Instance
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name "I_filt"
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duLibraryName "WaveformGenerator"
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duName "lowpass"
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elements [
|
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(GiElement
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name "signalBitNb"
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type "positive"
|
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value "signalBitNb"
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)
|
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(GiElement
|
|
name "shiftBitNb"
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type "positive"
|
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value "lowpassShiftBitNb"
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)
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]
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mwi 0
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uid 2852,0
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|
)
|
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(Instance
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|
name "I_DUT"
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duLibraryName "SystemOnChip"
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duName "beamerSoc"
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|
elements [
|
|
(GiElement
|
|
name "ioNb"
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|
type "positive"
|
|
value "ioNb"
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|
)
|
|
(GiElement
|
|
name "testOutBitNb"
|
|
type "positive"
|
|
value "testOutBitNb"
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|
)
|
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(GiElement
|
|
name "patternAddressBitNb"
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type "positive"
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value "patternAddressBitNb"
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)
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]
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mwi 0
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uid 3413,0
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)
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]
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embeddedInstances [
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(EmbeddedInstance
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name "eb1"
|
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number "1"
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)
|
|
(EmbeddedInstance
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|
name "eb3"
|
|
number "3"
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)
|
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]
|
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libraryRefs [
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"ieee"
|
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]
|
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)
|
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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model (BlockDiag
|
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VExpander (VariableExpander
|
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vvMap [
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|
(vvPair
|
|
variable " "
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|
value " "
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|
)
|
|
(vvPair
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|
variable "HDLDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@soc_tb\\struct.bd.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@soc_tb\\struct.bd.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
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|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@soc_tb"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamerSoc_tb"
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|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "ven."
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "vendredi"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "beamerSoc_tb"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
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|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "struct"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "15:06:16"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "SystemOnChip_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSim"
|
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/SystemOnChip_test"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "04"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "beamerSoc_tb"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "avr."
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "avril"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@soc_tb\\struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamerSoc_tb\\struct.bd"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
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|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
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|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "bd"
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|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "struct"
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|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "struct"
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)
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|
(vvPair
|
|
variable "time"
|
|
value "15:06:16"
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|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "beamerSoc_tb"
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|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "axel.amand"
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)
|
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(vvPair
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|
variable "version"
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|
value "2019.2 (Build 5)"
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)
|
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(vvPair
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|
variable "view"
|
|
value "struct"
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|
)
|
|
(vvPair
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|
variable "year"
|
|
value "2023"
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|
)
|
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(vvPair
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variable "yy"
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|
value "23"
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)
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]
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)
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thePort (LogicalPort
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tg (CPTG
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uid 2871,0
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uid 2872,0
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va (VaSet
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uid 2873,0
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ps "OnEdgeStrategy"
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tg (CPTG
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uid 2876,0
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va (VaSet
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|
|
xt "70000,13400,75800,14600"
|
|
st "lowpassIn"
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|
blo "70000,14400"
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)
|
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)
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|
thePort (LogicalPort
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decl (Decl
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|
n "lowpassIn"
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|
t "unsigned"
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|
b "(signalBitNb-1 DOWNTO 0)"
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o 4
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)
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)
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)
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shape (Rectangle
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uid 2853,0
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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bg "0,65535,0"
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lineWidth 2
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xt "69000,10000,85000,22000"
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)
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oxt "32000,10000,48000,22000"
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ttg (MlTextGroup
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uid 2854,0
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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textVec [
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uid 2855,0
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va (VaSet
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font "Verdana,9,1"
|
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)
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xt "69600,21800,81100,23000"
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st "WaveformGenerator"
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|
blo "69600,22800"
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tm "BdLibraryNameMgr"
|
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)
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*41 (Text
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uid 2856,0
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va (VaSet
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font "Verdana,9,1"
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)
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xt "69600,23000,74200,24200"
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st "lowpass"
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blo "69600,24000"
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tm "CptNameMgr"
|
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)
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*42 (Text
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uid 2857,0
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va (VaSet
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font "Verdana,9,1"
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)
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xt "69600,24200,72900,25400"
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st "I_filt"
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|
blo "69600,25200"
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tm "InstanceNameMgr"
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)
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]
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)
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ga (GenericAssociation
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uid 2858,0
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ps "EdgeToEdgeStrategy"
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matrix (Matrix
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uid 2859,0
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text (MLText
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uid 2860,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "69000,25600,89800,27600"
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st "signalBitNb = signalBitNb ( positive )
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shiftBitNb = lowpassShiftBitNb ( positive ) "
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header ""
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elements [
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(GiElement
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type "positive"
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value "signalBitNb"
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)
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(GiElement
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name "shiftBitNb"
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type "positive"
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value "lowpassShiftBitNb"
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)
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)
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ordering 1
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portVis (PortSigDisplay
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sTC 0
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)
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archFileType "UNKNOWN"
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)
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uid 2901,0
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decl (Decl
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n "lowpassInY"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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o 8
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suid 30,0
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)
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declText (MLText
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uid 2902,0
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va (VaSet
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)
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xt "2000,27000,35000,28200"
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st "SIGNAL lowpassInY : unsigned(signalBitNb-1 DOWNTO 0)
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"
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)
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)
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*44 (Net
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uid 2903,0
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decl (Decl
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n "lowpassOutY"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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o 9
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suid 31,0
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)
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declText (MLText
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uid 2904,0
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va (VaSet
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)
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xt "2000,28200,35500,29400"
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st "SIGNAL lowpassOutY : unsigned(signalBitNb-1 DOWNTO 0)
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)
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)
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*45 (SaComponent
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uid 3413,0
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optionalChildren [
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*46 (CptPort
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uid 3369,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 3370,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "36250,45625,37000,46375"
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)
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tg (CPTG
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|
uid 3371,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 3372,0
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va (VaSet
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)
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xt "38000,45400,41400,46600"
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st "clock"
|
|
blo "38000,46400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
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n "clock"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 1,0
|
|
)
|
|
)
|
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)
|
|
*47 (CptPort
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|
uid 3373,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 3374,0
|
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
|
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)
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|
xt "53000,41625,53750,42375"
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)
|
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tg (CPTG
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|
uid 3375,0
|
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 3376,0
|
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va (VaSet
|
|
)
|
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xt "49001,41400,52001,42600"
|
|
st "outX"
|
|
ju 2
|
|
blo "52001,42400"
|
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)
|
|
)
|
|
thePort (LogicalPort
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|
m 1
|
|
decl (Decl
|
|
n "outX"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*48 (CptPort
|
|
uid 3377,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
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|
uid 3378,0
|
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ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "53000,43625,53750,44375"
|
|
)
|
|
tg (CPTG
|
|
uid 3379,0
|
|
ps "CptPortTextPlaceStrategy"
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|
stg "RightVerticalLayoutStrategy"
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f (Text
|
|
uid 3380,0
|
|
va (VaSet
|
|
)
|
|
xt "49001,43400,52001,44600"
|
|
st "outY"
|
|
ju 2
|
|
blo "52001,44400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "outY"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 5,0
|
|
)
|
|
)
|
|
)
|
|
*49 (CptPort
|
|
uid 3381,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 3382,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "53000,45625,53750,46375"
|
|
)
|
|
tg (CPTG
|
|
uid 3383,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 3384,0
|
|
va (VaSet
|
|
)
|
|
xt "46201,45400,52001,46600"
|
|
st "selSinCos"
|
|
ju 2
|
|
blo "52001,46400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "selSinCos"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 13,0
|
|
)
|
|
)
|
|
)
|
|
*50 (CptPort
|
|
uid 3385,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
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uid 3386,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "36250,47625,37000,48375"
|
|
)
|
|
tg (CPTG
|
|
uid 3387,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 3388,0
|
|
va (VaSet
|
|
)
|
|
xt "38000,47400,41300,48600"
|
|
st "reset"
|
|
blo "38000,48400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 2017,0
|
|
)
|
|
)
|
|
)
|
|
*51 (CptPort
|
|
uid 3389,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 3390,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "36250,33625,37000,34375"
|
|
)
|
|
tg (CPTG
|
|
uid 3391,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 3392,0
|
|
va (VaSet
|
|
)
|
|
xt "38000,33400,40800,34600"
|
|
st "TxD"
|
|
blo "38000,34400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "TxD"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 2018,0
|
|
)
|
|
)
|
|
)
|
|
*52 (CptPort
|
|
uid 3393,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 3394,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "36250,35625,37000,36375"
|
|
)
|
|
tg (CPTG
|
|
uid 3395,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 3396,0
|
|
va (VaSet
|
|
)
|
|
xt "38000,35400,40800,36600"
|
|
st "RxD"
|
|
blo "38000,36400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "RxD"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 2019,0
|
|
)
|
|
)
|
|
)
|
|
*53 (CptPort
|
|
uid 3397,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 3398,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "53000,33625,53750,34375"
|
|
)
|
|
tg (CPTG
|
|
uid 3399,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 3400,0
|
|
va (VaSet
|
|
)
|
|
xt "49100,33400,52000,34600"
|
|
st "ioEn"
|
|
ju 2
|
|
blo "52000,34400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "ioEn"
|
|
t "std_ulogic_vector"
|
|
b "(ioNb-1 DOWNTO 0)"
|
|
o 8
|
|
suid 2020,0
|
|
)
|
|
)
|
|
)
|
|
*54 (CptPort
|
|
uid 3401,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 3402,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "53000,35625,53750,36375"
|
|
)
|
|
tg (CPTG
|
|
uid 3403,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 3404,0
|
|
va (VaSet
|
|
)
|
|
xt "48500,35400,52000,36600"
|
|
st "ioOut"
|
|
ju 2
|
|
blo "52000,36400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "ioOut"
|
|
t "std_ulogic_vector"
|
|
b "(ioNb-1 DOWNTO 0)"
|
|
o 9
|
|
suid 2021,0
|
|
)
|
|
)
|
|
)
|
|
*55 (CptPort
|
|
uid 3405,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 3406,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "53000,37625,53750,38375"
|
|
)
|
|
tg (CPTG
|
|
uid 3407,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 3408,0
|
|
va (VaSet
|
|
)
|
|
xt "49300,37400,52000,38600"
|
|
st "ioIn"
|
|
ju 2
|
|
blo "52000,38400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "ioIn"
|
|
t "std_ulogic_vector"
|
|
b "(ioNb-1 DOWNTO 0)"
|
|
o 10
|
|
suid 2022,0
|
|
)
|
|
)
|
|
)
|
|
*56 (CptPort
|
|
uid 3409,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 3410,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "44625,29250,45375,30000"
|
|
)
|
|
tg (CPTG
|
|
uid 3411,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 3412,0
|
|
va (VaSet
|
|
)
|
|
xt "43000,31000,47600,32200"
|
|
st "testOut"
|
|
ju 2
|
|
blo "47600,32000"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "testOut"
|
|
t "std_ulogic_vector"
|
|
b "(1 TO testOutBitNb)"
|
|
o 11
|
|
suid 2024,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 3414,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
bg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "37000,30000,53000,50000"
|
|
)
|
|
oxt "36000,10000,52000,30000"
|
|
ttg (MlTextGroup
|
|
uid 3415,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*57 (Text
|
|
uid 3416,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "37600,49800,46000,51000"
|
|
st "SystemOnChip"
|
|
blo "37600,50800"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*58 (Text
|
|
uid 3417,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "37600,51000,43600,52200"
|
|
st "beamerSoc"
|
|
blo "37600,52000"
|
|
tm "CptNameMgr"
|
|
)
|
|
*59 (Text
|
|
uid 3418,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "37600,52200,41300,53400"
|
|
st "I_DUT"
|
|
blo "37600,53200"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 3419,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 3420,0
|
|
text (MLText
|
|
uid 3421,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "37000,53600,62800,56600"
|
|
st "ioNb = ioNb ( positive )
|
|
testOutBitNb = testOutBitNb ( positive )
|
|
patternAddressBitNb = patternAddressBitNb ( positive ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "ioNb"
|
|
type "positive"
|
|
value "ioNb"
|
|
)
|
|
(GiElement
|
|
name "testOutBitNb"
|
|
type "positive"
|
|
value "testOutBitNb"
|
|
)
|
|
(GiElement
|
|
name "patternAddressBitNb"
|
|
type "positive"
|
|
value "patternAddressBitNb"
|
|
)
|
|
]
|
|
)
|
|
ordering 1
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*60 (Wire
|
|
uid 2466,0
|
|
shape (OrthoPolyLine
|
|
uid 2467,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "35000,48000,36250,58000"
|
|
pts [
|
|
"36250,48000"
|
|
"35000,48000"
|
|
"35000,58000"
|
|
]
|
|
)
|
|
start &50
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2470,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2471,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "31250,46600,35350,48000"
|
|
st "reset"
|
|
blo "31250,47800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &16
|
|
)
|
|
*61 (Wire
|
|
uid 2474,0
|
|
shape (OrthoPolyLine
|
|
uid 2475,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "33000,46000,36250,58000"
|
|
pts [
|
|
"36250,46000"
|
|
"33000,46000"
|
|
"33000,58000"
|
|
]
|
|
)
|
|
start &46
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2478,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2479,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "31250,44600,35050,46000"
|
|
st "clock"
|
|
blo "31250,45800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &17
|
|
)
|
|
*62 (Wire
|
|
uid 2482,0
|
|
shape (OrthoPolyLine
|
|
uid 2483,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "29000,36000,36250,58000"
|
|
pts [
|
|
"36250,36000"
|
|
"29000,36000"
|
|
"29000,58000"
|
|
]
|
|
)
|
|
start &52
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2486,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2487,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "32250,34600,35450,36000"
|
|
st "RxD"
|
|
blo "32250,35800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &18
|
|
)
|
|
*63 (Wire
|
|
uid 2490,0
|
|
shape (OrthoPolyLine
|
|
uid 2491,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "27000,34000,36250,58000"
|
|
pts [
|
|
"36250,34000"
|
|
"27000,34000"
|
|
"27000,58000"
|
|
]
|
|
)
|
|
start &51
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2494,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2495,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "32250,32600,35350,34000"
|
|
st "TxD"
|
|
blo "32250,33800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &19
|
|
)
|
|
*64 (Wire
|
|
uid 2498,0
|
|
shape (OrthoPolyLine
|
|
uid 2499,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "53750,46000,57000,58000"
|
|
pts [
|
|
"53750,46000"
|
|
"57000,46000"
|
|
"57000,58000"
|
|
]
|
|
)
|
|
start &49
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2502,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2503,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "55750,44600,62650,46000"
|
|
st "selSinCos"
|
|
blo "55750,45800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &20
|
|
)
|
|
*65 (Wire
|
|
uid 2506,0
|
|
optionalChildren [
|
|
*66 (BdJunction
|
|
uid 2911,0
|
|
ps "OnConnectorStrategy"
|
|
shape (Circle
|
|
uid 2912,0
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "58600,43600,59400,44400"
|
|
radius 400
|
|
)
|
|
)
|
|
]
|
|
shape (OrthoPolyLine
|
|
uid 2507,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "53750,44000,59000,58000"
|
|
pts [
|
|
"53750,44000"
|
|
"59000,44000"
|
|
"59000,58000"
|
|
]
|
|
)
|
|
start &48
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2510,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2511,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "55750,42600,59350,44000"
|
|
st "outY"
|
|
blo "55750,43800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &21
|
|
)
|
|
*67 (Wire
|
|
uid 2514,0
|
|
shape (OrthoPolyLine
|
|
uid 2515,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "53750,42000,61000,58000"
|
|
pts [
|
|
"53750,42000"
|
|
"61000,42000"
|
|
"61000,58000"
|
|
]
|
|
)
|
|
start &47
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2518,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2519,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "55750,40600,59450,42000"
|
|
st "outX"
|
|
blo "55750,41800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &22
|
|
)
|
|
*68 (Wire
|
|
uid 2552,0
|
|
shape (OrthoPolyLine
|
|
uid 2553,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "53750,36000,69000,36000"
|
|
pts [
|
|
"53750,36000"
|
|
"69000,36000"
|
|
]
|
|
)
|
|
start &54
|
|
end &23
|
|
sat 32
|
|
eat 1
|
|
sty 1
|
|
stc 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2558,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2559,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "55750,34600,59950,36000"
|
|
st "ioOut"
|
|
blo "55750,35800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &29
|
|
)
|
|
*69 (Wire
|
|
uid 2560,0
|
|
shape (OrthoPolyLine
|
|
uid 2561,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "53750,34000,69000,34000"
|
|
pts [
|
|
"53750,34000"
|
|
"69000,34000"
|
|
]
|
|
)
|
|
start &53
|
|
end &23
|
|
sat 32
|
|
eat 1
|
|
sty 1
|
|
stc 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2566,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2567,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "55750,32600,59250,34000"
|
|
st "ioEn"
|
|
blo "55750,33800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &30
|
|
)
|
|
*70 (Wire
|
|
uid 2568,0
|
|
shape (OrthoPolyLine
|
|
uid 2569,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "85000,34000,89000,58000"
|
|
pts [
|
|
"85000,34000"
|
|
"89000,34000"
|
|
"89000,58000"
|
|
]
|
|
)
|
|
start &23
|
|
end &12
|
|
sat 4
|
|
eat 4
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2574,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2575,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "87000,32600,88900,34000"
|
|
st "io"
|
|
blo "87000,33800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &27
|
|
)
|
|
*71 (Wire
|
|
uid 2576,0
|
|
shape (OrthoPolyLine
|
|
uid 2577,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "53750,38000,69000,38000"
|
|
pts [
|
|
"53750,38000"
|
|
"69000,38000"
|
|
]
|
|
)
|
|
start &55
|
|
end &23
|
|
sat 32
|
|
eat 2
|
|
sty 1
|
|
stc 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2582,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2583,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "55750,36600,58950,38000"
|
|
st "ioIn"
|
|
blo "55750,37800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &28
|
|
)
|
|
*72 (Wire
|
|
uid 2877,0
|
|
shape (OrthoPolyLine
|
|
uid 2878,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "61000,14000,68250,14000"
|
|
pts [
|
|
"68250,14000"
|
|
"61000,14000"
|
|
]
|
|
)
|
|
start &39
|
|
end &31
|
|
ss 0
|
|
sat 32
|
|
eat 2
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2881,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2882,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "63000,12600,71800,14000"
|
|
st "lowpassInY"
|
|
blo "63000,13800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &43
|
|
)
|
|
*73 (Wire
|
|
uid 2883,0
|
|
shape (OrthoPolyLine
|
|
uid 2884,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "65000,18000,68250,18000"
|
|
pts [
|
|
"65000,18000"
|
|
"68250,18000"
|
|
]
|
|
)
|
|
end &36
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2887,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2888,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "65000,16600,68800,18000"
|
|
st "clock"
|
|
blo "65000,17800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &17
|
|
)
|
|
*74 (Wire
|
|
uid 2889,0
|
|
shape (OrthoPolyLine
|
|
uid 2890,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "65000,20000,68250,20000"
|
|
pts [
|
|
"65000,20000"
|
|
"68250,20000"
|
|
]
|
|
)
|
|
end &38
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2893,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2894,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "65000,18600,69100,20000"
|
|
st "reset"
|
|
blo "65000,19800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &16
|
|
)
|
|
*75 (Wire
|
|
uid 2895,0
|
|
shape (OrthoPolyLine
|
|
uid 2896,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "85750,14000,93000,58000"
|
|
pts [
|
|
"85750,14000"
|
|
"93000,14000"
|
|
"93000,58000"
|
|
]
|
|
)
|
|
start &37
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2899,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2900,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "87750,12600,97550,14000"
|
|
st "lowpassOutY"
|
|
blo "87750,13800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &44
|
|
)
|
|
*76 (Wire
|
|
uid 2905,0
|
|
shape (OrthoPolyLine
|
|
uid 2906,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "53000,16000,59000,44000"
|
|
pts [
|
|
"59000,44000"
|
|
"59000,20000"
|
|
"53000,20000"
|
|
"53000,16000"
|
|
]
|
|
)
|
|
start &66
|
|
end &31
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2909,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2910,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "54000,18600,57600,20000"
|
|
st "outY"
|
|
blo "54000,19800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &21
|
|
)
|
|
]
|
|
bg "65535,65535,65535"
|
|
grid (Grid
|
|
origin "0,0"
|
|
isVisible 0
|
|
isActive 1
|
|
xSpacing 1000
|
|
xySpacing 1000
|
|
xShown 1
|
|
yShown 1
|
|
color "26368,26368,26368"
|
|
)
|
|
packageList *77 (PackageList
|
|
uid 142,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*78 (Text
|
|
uid 143,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,0,6900,1000"
|
|
st "Package List"
|
|
blo "0,800"
|
|
)
|
|
*79 (MLText
|
|
uid 144,0
|
|
va (VaSet
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|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoBuffer (PortIoBuffer
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultSignal (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,2600,1400"
|
|
st "sig0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBus (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,3900,1400"
|
|
st "dbus0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineStyle 3
|
|
lineWidth 1
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,2600,1000"
|
|
st "bundle0"
|
|
blo "0,800"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,1500,2200"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,50000"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,0,5000,1200"
|
|
st "Auto list"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,9600,2200"
|
|
st "User defined list"
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,18500,100"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*104 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*105 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,11000,100"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*106 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*107 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,7200,7000,8200"
|
|
st "Declarations"
|
|
blo "0,8000"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,8200,3400,9200"
|
|
st "Ports:"
|
|
blo "0,9000"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,9200,4800,10200"
|
|
st "Pre User:"
|
|
blo "0,10000"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,10200,22200,18200"
|
|
st "constant ioNb: positive := 8;
|
|
constant testOutBitNb: positive := 16;
|
|
constant patternAddressBitNb: positive := 9;
|
|
|
|
constant signalBitNb: positive := 16;
|
|
constant lowpassShiftBitNb: positive := 8;
|
|
constant clockFrequency : real := 60.0E6;
|
|
--constant clockFrequency : real := 66.0E6;"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,18200,9000,19200"
|
|
st "Diagram Signals:"
|
|
blo "0,19000"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,7200,6000,8200"
|
|
st "Post User:"
|
|
blo "0,8000"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,7200,0,7200"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 31,0
|
|
usingSuid 1
|
|
emptyRow *108 (LEmptyRow
|
|
)
|
|
uid 1321,0
|
|
optionalChildren [
|
|
*109 (RefLabelRowHdr
|
|
)
|
|
*110 (TitleRowHdr
|
|
)
|
|
*111 (FilterRowHdr
|
|
)
|
|
*112 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*113 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*114 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*115 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*116 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*117 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*118 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*119 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*120 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*121 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 12
|
|
suid 18,0
|
|
)
|
|
)
|
|
uid 2528,0
|
|
)
|
|
*122 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 19,0
|
|
)
|
|
)
|
|
uid 2530,0
|
|
)
|
|
*123 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "RxD"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 20,0
|
|
)
|
|
)
|
|
uid 2532,0
|
|
)
|
|
*124 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "TxD"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 21,0
|
|
)
|
|
)
|
|
uid 2534,0
|
|
)
|
|
*125 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "selSinCos"
|
|
t "std_ulogic"
|
|
o 13
|
|
suid 22,0
|
|
)
|
|
)
|
|
uid 2536,0
|
|
)
|
|
*126 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "outY"
|
|
t "std_ulogic"
|
|
o 11
|
|
suid 23,0
|
|
)
|
|
)
|
|
uid 2538,0
|
|
)
|
|
*127 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "outX"
|
|
t "std_ulogic"
|
|
o 10
|
|
suid 24,0
|
|
)
|
|
)
|
|
uid 2540,0
|
|
)
|
|
*128 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "io"
|
|
t "std_logic_vector"
|
|
b "(ioNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 26,0
|
|
)
|
|
)
|
|
uid 2592,0
|
|
)
|
|
*129 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "ioIn"
|
|
t "std_ulogic_vector"
|
|
b "(ioNb-1 DOWNTO 0)"
|
|
o 6
|
|
suid 27,0
|
|
)
|
|
)
|
|
uid 2594,0
|
|
)
|
|
*130 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "ioOut"
|
|
t "std_ulogic_vector"
|
|
b "(ioNb-1 DOWNTO 0)"
|
|
o 7
|
|
suid 28,0
|
|
)
|
|
)
|
|
uid 2596,0
|
|
)
|
|
*131 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "ioEn"
|
|
t "std_ulogic_vector"
|
|
b "(ioNb-1 DOWNTO 0)"
|
|
o 5
|
|
suid 29,0
|
|
)
|
|
)
|
|
uid 2598,0
|
|
)
|
|
*132 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "lowpassInY"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 8
|
|
suid 30,0
|
|
)
|
|
)
|
|
uid 2913,0
|
|
)
|
|
*133 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "lowpassOutY"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 9
|
|
suid 31,0
|
|
)
|
|
)
|
|
uid 2915,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 1334,0
|
|
optionalChildren [
|
|
*134 (Sheet
|
|
sheetRow (SheetRow
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|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
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font "Tahoma,10,0"
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|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
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|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
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)
|
|
groupVa (MVa
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|
cellColor "39936,56832,65280"
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|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
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|
)
|
|
emptyMRCItem *135 (MRCItem
|
|
litem &108
|
|
pos 13
|
|
dimension 20
|
|
)
|
|
uid 1336,0
|
|
optionalChildren [
|
|
*136 (MRCItem
|
|
litem &109
|
|
pos 0
|
|
dimension 20
|
|
uid 1337,0
|
|
)
|
|
*137 (MRCItem
|
|
litem &110
|
|
pos 1
|
|
dimension 23
|
|
uid 1338,0
|
|
)
|
|
*138 (MRCItem
|
|
litem &111
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 1339,0
|
|
)
|
|
*139 (MRCItem
|
|
litem &121
|
|
pos 0
|
|
dimension 20
|
|
uid 2529,0
|
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)
|
|
*140 (MRCItem
|
|
litem &122
|
|
pos 1
|
|
dimension 20
|
|
uid 2531,0
|
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)
|
|
*141 (MRCItem
|
|
litem &123
|
|
pos 2
|
|
dimension 20
|
|
uid 2533,0
|
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)
|
|
*142 (MRCItem
|
|
litem &124
|
|
pos 3
|
|
dimension 20
|
|
uid 2535,0
|
|
)
|
|
*143 (MRCItem
|
|
litem &125
|
|
pos 4
|
|
dimension 20
|
|
uid 2537,0
|
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)
|
|
*144 (MRCItem
|
|
litem &126
|
|
pos 5
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|
dimension 20
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|
uid 2539,0
|
|
)
|
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*145 (MRCItem
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|
litem &127
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|
pos 6
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dimension 20
|
|
uid 2541,0
|
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)
|
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*146 (MRCItem
|
|
litem &128
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|
pos 7
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|
dimension 20
|
|
uid 2593,0
|
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)
|
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*147 (MRCItem
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|
litem &129
|
|
pos 8
|
|
dimension 20
|
|
uid 2595,0
|
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)
|
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*148 (MRCItem
|
|
litem &130
|
|
pos 9
|
|
dimension 20
|
|
uid 2597,0
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)
|
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*149 (MRCItem
|
|
litem &131
|
|
pos 10
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dimension 20
|
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uid 2599,0
|
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)
|
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*150 (MRCItem
|
|
litem &132
|
|
pos 11
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dimension 20
|
|
uid 2914,0
|
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)
|
|
*151 (MRCItem
|
|
litem &133
|
|
pos 12
|
|
dimension 20
|
|
uid 2916,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
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|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
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|
textAngle 90
|
|
)
|
|
uid 1340,0
|
|
optionalChildren [
|
|
*152 (MRCItem
|
|
litem &112
|
|
pos 0
|
|
dimension 20
|
|
uid 1341,0
|
|
)
|
|
*153 (MRCItem
|
|
litem &114
|
|
pos 1
|
|
dimension 50
|
|
uid 1342,0
|
|
)
|
|
*154 (MRCItem
|
|
litem &115
|
|
pos 2
|
|
dimension 100
|
|
uid 1343,0
|
|
)
|
|
*155 (MRCItem
|
|
litem &116
|
|
pos 3
|
|
dimension 50
|
|
uid 1344,0
|
|
)
|
|
*156 (MRCItem
|
|
litem &117
|
|
pos 4
|
|
dimension 100
|
|
uid 1345,0
|
|
)
|
|
*157 (MRCItem
|
|
litem &118
|
|
pos 5
|
|
dimension 100
|
|
uid 1346,0
|
|
)
|
|
*158 (MRCItem
|
|
litem &119
|
|
pos 6
|
|
dimension 50
|
|
uid 1347,0
|
|
)
|
|
*159 (MRCItem
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|
litem &120
|
|
pos 7
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dimension 80
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uid 1348,0
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)
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]
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)
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fixedCol 4
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fixedRow 2
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name "Ports"
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|
uid 1335,0
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vaOverrides [
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]
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|
)
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]
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)
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uid 1320,0
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)
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genericsCommonDM (CommonDM
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ldm (LogicalDM
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|
emptyRow *160 (LEmptyRow
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)
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uid 1350,0
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optionalChildren [
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*161 (RefLabelRowHdr
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)
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*162 (TitleRowHdr
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)
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*163 (FilterRowHdr
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)
|
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*164 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
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)
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*165 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
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)
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*166 (GroupColHdr
|
|
tm "GroupColHdrMgr"
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)
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*167 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
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)
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*168 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
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)
|
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*169 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*170 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*171 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
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)
|
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pdm (PhysicalDM
|
|
uid 1362,0
|
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optionalChildren [
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*172 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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emptyMRCItem *173 (MRCItem
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litem &160
|
|
pos 0
|
|
dimension 20
|
|
)
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uid 1364,0
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optionalChildren [
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*174 (MRCItem
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litem &161
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pos 0
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|
dimension 20
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uid 1365,0
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)
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*175 (MRCItem
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|
litem &162
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|
pos 1
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|
dimension 23
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uid 1366,0
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)
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*176 (MRCItem
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litem &163
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pos 2
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hidden 1
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|
dimension 20
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uid 1367,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 1368,0
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optionalChildren [
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*177 (MRCItem
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litem &164
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pos 0
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dimension 20
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uid 1369,0
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)
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*178 (MRCItem
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litem &166
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pos 1
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|
dimension 50
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uid 1370,0
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)
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*179 (MRCItem
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litem &167
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pos 2
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dimension 100
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uid 1371,0
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)
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*180 (MRCItem
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litem &168
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|
pos 3
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|
dimension 100
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|
uid 1372,0
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)
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*181 (MRCItem
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|
litem &169
|
|
pos 4
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|
dimension 50
|
|
uid 1373,0
|
|
)
|
|
*182 (MRCItem
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|
litem &170
|
|
pos 5
|
|
dimension 50
|
|
uid 1374,0
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)
|
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*183 (MRCItem
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|
litem &171
|
|
pos 6
|
|
dimension 80
|
|
uid 1375,0
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)
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|
]
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|
)
|
|
fixedCol 3
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|
fixedRow 2
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|
name "Ports"
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|
uid 1363,0
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vaOverrides [
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]
|
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)
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|
]
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)
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uid 1349,0
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|
type 1
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|
)
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|
activeModelName "BlockDiag"
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)
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