25 lines
797 B
VHDL
25 lines
797 B
VHDL
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ARCHITECTURE rtl OF mainDecoder IS
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signal lvec_controls : std_ulogic_vector(10 downto 0);
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BEGIN
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process(op)
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begin
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case op is
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when "0000011" => lvec_controls <= "10010010000"; -- lw
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when "0100011" => lvec_controls <= "00111000000"; -- sw
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when "0110011" => lvec_controls <= "1--00000100"; -- R-type
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when "1100011" => lvec_controls <= "01000001010"; -- beq
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when "0010011" => lvec_controls <= "10010000100"; -- I-type ALU
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when "1101111" => lvec_controls <= "11100100001"; -- jal
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when others => lvec_controls <= "-----------"; -- not valid
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end case;
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end process;
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(regwrite, immSrc(1), immSrc(0), ALUSrc, memWrite, resultSrc(1), resultSrc(0),
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branch, ALUOp(1), ALUOp(0), jump) <= lvec_controls after g_tDec;
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END ARCHITECTURE rtl;
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