2893 lines
35 KiB
Plaintext
2893 lines
35 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "24.1"
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appVersion "2009.2 (Build 10)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 26,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 221,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
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|
*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*12 (InitColHdr
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tm "InitColHdrMgr"
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)
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*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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*14 (LogPort
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port (LogicalPort
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decl (Decl
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n "branchCond"
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t "std_ulogic_vector"
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b "( branchCondBitNb-1 DOWNTO 0 )"
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o 1
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suid 1,0
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)
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)
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uid 171,0
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)
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*15 (LogPort
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port (LogicalPort
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|
m 1
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decl (Decl
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n "cIn"
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t "std_ulogic"
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o 10
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suid 2,0
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)
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)
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uid 173,0
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)
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*16 (LogPort
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port (LogicalPort
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 3
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suid 3,0
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)
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)
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uid 175,0
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)
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*17 (LogPort
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port (LogicalPort
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decl (Decl
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n "cOut"
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t "std_ulogic"
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o 2
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suid 4,0
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)
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)
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uid 177,0
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)
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*18 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "prevPC"
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t "std_ulogic"
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o 11
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suid 5,0
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)
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)
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uid 179,0
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)
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*19 (LogPort
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port (LogicalPort
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|
decl (Decl
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n "en"
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t "std_ulogic"
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o 4
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suid 6,0
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)
|
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)
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|
uid 181,0
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)
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*20 (LogPort
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|
port (LogicalPort
|
|
m 1
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|
decl (Decl
|
|
n "incPC"
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|
t "std_ulogic"
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|
o 12
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suid 7,0
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)
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)
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uid 183,0
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)
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*21 (LogPort
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|
port (LogicalPort
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|
m 1
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decl (Decl
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n "instrDataSel"
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t "std_ulogic"
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o 13
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suid 8,0
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)
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)
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uid 185,0
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)
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*22 (LogPort
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port (LogicalPort
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decl (Decl
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n "int"
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t "std_uLogic"
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o 5
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suid 9,0
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)
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)
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uid 187,0
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)
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*23 (LogPort
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|
port (LogicalPort
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|
m 1
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|
decl (Decl
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|
n "intAck"
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t "std_ulogic"
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o 14
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suid 10,0
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)
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)
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uid 189,0
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)
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*24 (LogPort
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|
port (LogicalPort
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|
decl (Decl
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|
n "intCode"
|
|
t "std_ulogic_vector"
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|
b "( intCodeBitNb-1 DOWNTO 0 )"
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o 6
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suid 11,0
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)
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)
|
|
uid 191,0
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)
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|
*25 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "loadInstrAddress"
|
|
t "std_ulogic"
|
|
o 15
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suid 12,0
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)
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)
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|
uid 193,0
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)
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|
*26 (LogPort
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|
port (LogicalPort
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|
m 1
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|
decl (Decl
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|
n "loadStoredPC"
|
|
t "std_ulogic"
|
|
o 16
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suid 13,0
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)
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)
|
|
uid 195,0
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)
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|
*27 (LogPort
|
|
port (LogicalPort
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|
decl (Decl
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|
n "opCode"
|
|
t "std_ulogic_vector"
|
|
b "(opCodeBitNb-1 DOWNTO 0)"
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o 7
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suid 14,0
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)
|
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)
|
|
uid 197,0
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|
)
|
|
*28 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "portInSel"
|
|
t "std_ulogic"
|
|
o 17
|
|
suid 15,0
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)
|
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)
|
|
uid 199,0
|
|
)
|
|
*29 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "readStrobe"
|
|
t "std_uLogic"
|
|
o 18
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suid 16,0
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)
|
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)
|
|
uid 201,0
|
|
)
|
|
*30 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "registerFileSel"
|
|
t "std_ulogic"
|
|
o 20
|
|
suid 17,0
|
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)
|
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)
|
|
uid 203,0
|
|
)
|
|
*31 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 8
|
|
suid 18,0
|
|
)
|
|
)
|
|
uid 205,0
|
|
)
|
|
*32 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "scratchpadSel"
|
|
t "std_ulogic"
|
|
o 21
|
|
suid 19,0
|
|
)
|
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)
|
|
uid 207,0
|
|
)
|
|
*33 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "scratchpadWrite"
|
|
t "std_ulogic"
|
|
o 22
|
|
suid 20,0
|
|
)
|
|
)
|
|
uid 209,0
|
|
)
|
|
*34 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "storePC"
|
|
t "std_ulogic"
|
|
o 23
|
|
suid 21,0
|
|
)
|
|
)
|
|
uid 211,0
|
|
)
|
|
*35 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "writeStrobe"
|
|
t "std_uLogic"
|
|
o 24
|
|
suid 23,0
|
|
)
|
|
)
|
|
uid 215,0
|
|
)
|
|
*36 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "zero"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 24,0
|
|
)
|
|
)
|
|
uid 217,0
|
|
)
|
|
*37 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "regWrite"
|
|
t "std_ulogic"
|
|
o 19
|
|
suid 25,0
|
|
)
|
|
)
|
|
uid 331,0
|
|
)
|
|
*38 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "twoRegInstr"
|
|
t "std_ulogic"
|
|
o 25
|
|
suid 26,0
|
|
)
|
|
)
|
|
uid 432,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 234,0
|
|
optionalChildren [
|
|
*39 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *40 (MRCItem
|
|
litem &1
|
|
pos 25
|
|
dimension 20
|
|
)
|
|
uid 236,0
|
|
optionalChildren [
|
|
*41 (MRCItem
|
|
litem &2
|
|
pos 0
|
|
dimension 20
|
|
uid 237,0
|
|
)
|
|
*42 (MRCItem
|
|
litem &3
|
|
pos 1
|
|
dimension 23
|
|
uid 238,0
|
|
)
|
|
*43 (MRCItem
|
|
litem &4
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 239,0
|
|
)
|
|
*44 (MRCItem
|
|
litem &14
|
|
pos 0
|
|
dimension 20
|
|
uid 172,0
|
|
)
|
|
*45 (MRCItem
|
|
litem &15
|
|
pos 1
|
|
dimension 20
|
|
uid 174,0
|
|
)
|
|
*46 (MRCItem
|
|
litem &16
|
|
pos 2
|
|
dimension 20
|
|
uid 176,0
|
|
)
|
|
*47 (MRCItem
|
|
litem &17
|
|
pos 3
|
|
dimension 20
|
|
uid 178,0
|
|
)
|
|
*48 (MRCItem
|
|
litem &18
|
|
pos 4
|
|
dimension 20
|
|
uid 180,0
|
|
)
|
|
*49 (MRCItem
|
|
litem &19
|
|
pos 5
|
|
dimension 20
|
|
uid 182,0
|
|
)
|
|
*50 (MRCItem
|
|
litem &20
|
|
pos 6
|
|
dimension 20
|
|
uid 184,0
|
|
)
|
|
*51 (MRCItem
|
|
litem &21
|
|
pos 7
|
|
dimension 20
|
|
uid 186,0
|
|
)
|
|
*52 (MRCItem
|
|
litem &22
|
|
pos 8
|
|
dimension 20
|
|
uid 188,0
|
|
)
|
|
*53 (MRCItem
|
|
litem &23
|
|
pos 9
|
|
dimension 20
|
|
uid 190,0
|
|
)
|
|
*54 (MRCItem
|
|
litem &24
|
|
pos 10
|
|
dimension 20
|
|
uid 192,0
|
|
)
|
|
*55 (MRCItem
|
|
litem &25
|
|
pos 11
|
|
dimension 20
|
|
uid 194,0
|
|
)
|
|
*56 (MRCItem
|
|
litem &26
|
|
pos 12
|
|
dimension 20
|
|
uid 196,0
|
|
)
|
|
*57 (MRCItem
|
|
litem &27
|
|
pos 13
|
|
dimension 20
|
|
uid 198,0
|
|
)
|
|
*58 (MRCItem
|
|
litem &28
|
|
pos 14
|
|
dimension 20
|
|
uid 200,0
|
|
)
|
|
*59 (MRCItem
|
|
litem &29
|
|
pos 15
|
|
dimension 20
|
|
uid 202,0
|
|
)
|
|
*60 (MRCItem
|
|
litem &30
|
|
pos 16
|
|
dimension 20
|
|
uid 204,0
|
|
)
|
|
*61 (MRCItem
|
|
litem &31
|
|
pos 17
|
|
dimension 20
|
|
uid 206,0
|
|
)
|
|
*62 (MRCItem
|
|
litem &32
|
|
pos 18
|
|
dimension 20
|
|
uid 208,0
|
|
)
|
|
*63 (MRCItem
|
|
litem &33
|
|
pos 19
|
|
dimension 20
|
|
uid 210,0
|
|
)
|
|
*64 (MRCItem
|
|
litem &34
|
|
pos 20
|
|
dimension 20
|
|
uid 212,0
|
|
)
|
|
*65 (MRCItem
|
|
litem &35
|
|
pos 21
|
|
dimension 20
|
|
uid 216,0
|
|
)
|
|
*66 (MRCItem
|
|
litem &36
|
|
pos 22
|
|
dimension 20
|
|
uid 218,0
|
|
)
|
|
*67 (MRCItem
|
|
litem &37
|
|
pos 23
|
|
dimension 20
|
|
uid 332,0
|
|
)
|
|
*68 (MRCItem
|
|
litem &38
|
|
pos 24
|
|
dimension 20
|
|
uid 433,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 240,0
|
|
optionalChildren [
|
|
*69 (MRCItem
|
|
litem &5
|
|
pos 0
|
|
dimension 20
|
|
uid 241,0
|
|
)
|
|
*70 (MRCItem
|
|
litem &7
|
|
pos 1
|
|
dimension 50
|
|
uid 242,0
|
|
)
|
|
*71 (MRCItem
|
|
litem &8
|
|
pos 2
|
|
dimension 100
|
|
uid 243,0
|
|
)
|
|
*72 (MRCItem
|
|
litem &9
|
|
pos 3
|
|
dimension 50
|
|
uid 244,0
|
|
)
|
|
*73 (MRCItem
|
|
litem &10
|
|
pos 4
|
|
dimension 100
|
|
uid 245,0
|
|
)
|
|
*74 (MRCItem
|
|
litem &11
|
|
pos 5
|
|
dimension 100
|
|
uid 246,0
|
|
)
|
|
*75 (MRCItem
|
|
litem &12
|
|
pos 6
|
|
dimension 50
|
|
uid 247,0
|
|
)
|
|
*76 (MRCItem
|
|
litem &13
|
|
pos 7
|
|
dimension 80
|
|
uid 248,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 235,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 220,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *77 (LEmptyRow
|
|
)
|
|
uid 250,0
|
|
optionalChildren [
|
|
*78 (RefLabelRowHdr
|
|
)
|
|
*79 (TitleRowHdr
|
|
)
|
|
*80 (FilterRowHdr
|
|
)
|
|
*81 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*82 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*83 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*84 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*85 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*86 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*87 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*88 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*89 (LogGeneric
|
|
generic (GiElement
|
|
name "intCodeBitNb"
|
|
type "positive"
|
|
value "5"
|
|
)
|
|
uid 299,0
|
|
)
|
|
*90 (LogGeneric
|
|
generic (GiElement
|
|
name "branchCondBitNb"
|
|
type "positive"
|
|
value "3"
|
|
)
|
|
uid 301,0
|
|
)
|
|
*91 (LogGeneric
|
|
generic (GiElement
|
|
name "opCodeBitNb"
|
|
type "positive"
|
|
value "5"
|
|
)
|
|
uid 356,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 262,0
|
|
optionalChildren [
|
|
*92 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *93 (MRCItem
|
|
litem &77
|
|
pos 3
|
|
dimension 20
|
|
)
|
|
uid 264,0
|
|
optionalChildren [
|
|
*94 (MRCItem
|
|
litem &78
|
|
pos 0
|
|
dimension 20
|
|
uid 265,0
|
|
)
|
|
*95 (MRCItem
|
|
litem &79
|
|
pos 1
|
|
dimension 23
|
|
uid 266,0
|
|
)
|
|
*96 (MRCItem
|
|
litem &80
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 267,0
|
|
)
|
|
*97 (MRCItem
|
|
litem &89
|
|
pos 0
|
|
dimension 20
|
|
uid 300,0
|
|
)
|
|
*98 (MRCItem
|
|
litem &90
|
|
pos 1
|
|
dimension 20
|
|
uid 302,0
|
|
)
|
|
*99 (MRCItem
|
|
litem &91
|
|
pos 2
|
|
dimension 20
|
|
uid 357,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 268,0
|
|
optionalChildren [
|
|
*100 (MRCItem
|
|
litem &81
|
|
pos 0
|
|
dimension 20
|
|
uid 269,0
|
|
)
|
|
*101 (MRCItem
|
|
litem &83
|
|
pos 1
|
|
dimension 50
|
|
uid 270,0
|
|
)
|
|
*102 (MRCItem
|
|
litem &84
|
|
pos 2
|
|
dimension 100
|
|
uid 271,0
|
|
)
|
|
*103 (MRCItem
|
|
litem &85
|
|
pos 3
|
|
dimension 100
|
|
uid 272,0
|
|
)
|
|
*104 (MRCItem
|
|
litem &86
|
|
pos 4
|
|
dimension 50
|
|
uid 273,0
|
|
)
|
|
*105 (MRCItem
|
|
litem &87
|
|
pos 5
|
|
dimension 50
|
|
uid 274,0
|
|
)
|
|
*106 (MRCItem
|
|
litem &88
|
|
pos 6
|
|
dimension 80
|
|
uid 275,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 263,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 249,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds\\controller\\symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds\\controller\\symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "boardTester"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds\\controller"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds\\controller"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "16.09.2010"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "jeu."
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "jeudi"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "16"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "controller"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE3195"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "NanoBlaze"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_HdsLintPlugin"
|
|
value "$HDS_PROJECT_DIR/../NanoBlaze/designcheck"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "D:/Labs/ElN/NanoBlaze/NanoBlaze/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "09"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "controller"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "sept."
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "septembre"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds\\controller\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds\\controller\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "D:\\Labs\\ElN\\BoardTester\\Board\\ise"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "C:\\EDA\\Modelsim\\win32"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "15:59:43"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "controller"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "cof"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2009.2 (Build 10)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2010"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "10"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "VhdlLangMgr"
|
|
uid 219,0
|
|
optionalChildren [
|
|
*107 (SymbolBody
|
|
uid 8,0
|
|
optionalChildren [
|
|
*108 (CptPort
|
|
uid 51,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 52,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62000,57625,62750,58375"
|
|
)
|
|
tg (CPTG
|
|
uid 53,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 54,0
|
|
va (VaSet
|
|
)
|
|
xt "56100,57500,61000,58500"
|
|
st "branchCond"
|
|
ju 2
|
|
blo "61000,58300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 55,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,11800,40000,12600"
|
|
st "branchCond : IN std_ulogic_vector ( branchCondBitNb-1 DOWNTO 0 ) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "branchCond"
|
|
t "std_ulogic_vector"
|
|
b "( branchCondBitNb-1 DOWNTO 0 )"
|
|
o 1
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*109 (CptPort
|
|
uid 56,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 57,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62000,95625,62750,96375"
|
|
)
|
|
tg (CPTG
|
|
uid 58,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 59,0
|
|
va (VaSet
|
|
)
|
|
xt "59600,95500,61000,96500"
|
|
st "cIn"
|
|
ju 2
|
|
blo "61000,96300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 60,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,19800,21000,20600"
|
|
st "cIn : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "cIn"
|
|
t "std_ulogic"
|
|
o 10
|
|
suid 2,0
|
|
)
|
|
)
|
|
)
|
|
*110 (CptPort
|
|
uid 61,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 62,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "45250,122625,46000,123375"
|
|
)
|
|
tg (CPTG
|
|
uid 63,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 64,0
|
|
va (VaSet
|
|
)
|
|
xt "47000,122500,49100,123500"
|
|
st "clock"
|
|
blo "47000,123300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 65,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,13400,21000,14200"
|
|
st "clock : IN std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*111 (CptPort
|
|
uid 66,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 67,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62000,97625,62750,98375"
|
|
)
|
|
tg (CPTG
|
|
uid 68,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 69,0
|
|
va (VaSet
|
|
)
|
|
xt "59000,97500,61000,98500"
|
|
st "cOut"
|
|
ju 2
|
|
blo "61000,98300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 70,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,12600,21000,13400"
|
|
st "cOut : IN std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "cOut"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
*112 (CptPort
|
|
uid 71,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 72,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62000,9625,62750,10375"
|
|
)
|
|
tg (CPTG
|
|
uid 73,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 74,0
|
|
va (VaSet
|
|
)
|
|
xt "58100,9500,61000,10500"
|
|
st "prevPC"
|
|
ju 2
|
|
blo "61000,10300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 75,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,25400,21000,26200"
|
|
st "prevPC : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "prevPC"
|
|
t "std_ulogic"
|
|
o 11
|
|
suid 5,0
|
|
)
|
|
)
|
|
)
|
|
*113 (CptPort
|
|
uid 76,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 77,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "45250,120625,46000,121375"
|
|
)
|
|
tg (CPTG
|
|
uid 78,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 79,0
|
|
va (VaSet
|
|
)
|
|
xt "47000,120500,48200,121500"
|
|
st "en"
|
|
blo "47000,121300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 80,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,14200,21000,15000"
|
|
st "en : IN std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "en"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 6,0
|
|
)
|
|
)
|
|
)
|
|
*114 (CptPort
|
|
uid 81,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 82,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62000,31625,62750,32375"
|
|
)
|
|
tg (CPTG
|
|
uid 83,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 84,0
|
|
va (VaSet
|
|
)
|
|
xt "58500,31500,61000,32500"
|
|
st "incPC"
|
|
ju 2
|
|
blo "61000,32300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 85,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,20600,21000,21400"
|
|
st "incPC : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "incPC"
|
|
t "std_ulogic"
|
|
o 12
|
|
suid 7,0
|
|
)
|
|
)
|
|
)
|
|
*115 (CptPort
|
|
uid 86,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 87,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62000,85625,62750,86375"
|
|
)
|
|
tg (CPTG
|
|
uid 88,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 89,0
|
|
va (VaSet
|
|
)
|
|
xt "56000,85500,61000,86500"
|
|
st "instrDataSel"
|
|
ju 2
|
|
blo "61000,86300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 90,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,21400,21000,22200"
|
|
st "instrDataSel : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "instrDataSel"
|
|
t "std_ulogic"
|
|
o 13
|
|
suid 8,0
|
|
)
|
|
)
|
|
)
|
|
*116 (CptPort
|
|
uid 91,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 92,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "45250,9625,46000,10375"
|
|
)
|
|
tg (CPTG
|
|
uid 93,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 94,0
|
|
va (VaSet
|
|
)
|
|
xt "47000,9500,48200,10500"
|
|
st "int"
|
|
blo "47000,10300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 95,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,15000,21000,15800"
|
|
st "int : IN std_uLogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "int"
|
|
t "std_uLogic"
|
|
o 5
|
|
suid 9,0
|
|
)
|
|
)
|
|
)
|
|
*117 (CptPort
|
|
uid 96,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 97,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "45250,11625,46000,12375"
|
|
)
|
|
tg (CPTG
|
|
uid 98,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 99,0
|
|
va (VaSet
|
|
)
|
|
xt "47000,11500,49400,12500"
|
|
st "intAck"
|
|
blo "47000,12300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 100,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,22200,21000,23000"
|
|
st "intAck : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "intAck"
|
|
t "std_ulogic"
|
|
o 14
|
|
suid 10,0
|
|
)
|
|
)
|
|
)
|
|
*118 (CptPort
|
|
uid 101,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 102,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62000,55625,62750,56375"
|
|
)
|
|
tg (CPTG
|
|
uid 103,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 104,0
|
|
va (VaSet
|
|
)
|
|
xt "58000,55500,61000,56500"
|
|
st "intCode"
|
|
ju 2
|
|
blo "61000,56300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 105,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,15800,38500,16600"
|
|
st "intCode : IN std_ulogic_vector ( intCodeBitNb-1 DOWNTO 0 ) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "intCode"
|
|
t "std_ulogic_vector"
|
|
b "( intCodeBitNb-1 DOWNTO 0 )"
|
|
o 6
|
|
suid 11,0
|
|
)
|
|
)
|
|
)
|
|
*119 (CptPort
|
|
uid 106,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 107,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62000,33625,62750,34375"
|
|
)
|
|
tg (CPTG
|
|
uid 108,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 109,0
|
|
va (VaSet
|
|
)
|
|
xt "54500,33500,61000,34500"
|
|
st "loadInstrAddress"
|
|
ju 2
|
|
blo "61000,34300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 110,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,23000,21000,23800"
|
|
st "loadInstrAddress : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "loadInstrAddress"
|
|
t "std_ulogic"
|
|
o 15
|
|
suid 12,0
|
|
)
|
|
)
|
|
)
|
|
*120 (CptPort
|
|
uid 111,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 112,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62000,35625,62750,36375"
|
|
)
|
|
tg (CPTG
|
|
uid 113,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 114,0
|
|
va (VaSet
|
|
)
|
|
xt "55500,35500,61000,36500"
|
|
st "loadStoredPC"
|
|
ju 2
|
|
blo "61000,36300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 115,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,23800,21000,24600"
|
|
st "loadStoredPC : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "loadStoredPC"
|
|
t "std_ulogic"
|
|
o 16
|
|
suid 13,0
|
|
)
|
|
)
|
|
)
|
|
*121 (CptPort
|
|
uid 116,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 117,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62000,61625,62750,62375"
|
|
)
|
|
tg (CPTG
|
|
uid 118,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 119,0
|
|
va (VaSet
|
|
)
|
|
xt "58000,61500,61000,62500"
|
|
st "opCode"
|
|
ju 2
|
|
blo "61000,62300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 120,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,16600,37000,17400"
|
|
st "opCode : IN std_ulogic_vector (opCodeBitNb-1 DOWNTO 0) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "opCode"
|
|
t "std_ulogic_vector"
|
|
b "(opCodeBitNb-1 DOWNTO 0)"
|
|
o 7
|
|
suid 14,0
|
|
)
|
|
)
|
|
)
|
|
*122 (CptPort
|
|
uid 121,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 122,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62000,87625,62750,88375"
|
|
)
|
|
tg (CPTG
|
|
uid 123,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 124,0
|
|
va (VaSet
|
|
)
|
|
xt "57600,87500,61000,88500"
|
|
st "portInSel"
|
|
ju 2
|
|
blo "61000,88300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 125,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,24600,21000,25400"
|
|
st "portInSel : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "portInSel"
|
|
t "std_ulogic"
|
|
o 17
|
|
suid 15,0
|
|
)
|
|
)
|
|
)
|
|
*123 (CptPort
|
|
uid 126,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 127,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62000,73625,62750,74375"
|
|
)
|
|
tg (CPTG
|
|
uid 128,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 129,0
|
|
va (VaSet
|
|
)
|
|
xt "56500,73500,61000,74500"
|
|
st "readStrobe"
|
|
ju 2
|
|
blo "61000,74300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 130,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,26200,21000,27000"
|
|
st "readStrobe : OUT std_uLogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "readStrobe"
|
|
t "std_uLogic"
|
|
o 18
|
|
suid 16,0
|
|
)
|
|
)
|
|
)
|
|
*124 (CptPort
|
|
uid 131,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 132,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62000,83625,62750,84375"
|
|
)
|
|
tg (CPTG
|
|
uid 133,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 134,0
|
|
va (VaSet
|
|
)
|
|
xt "55100,83500,61000,84500"
|
|
st "registerFileSel"
|
|
ju 2
|
|
blo "61000,84300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 135,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,27800,21000,28600"
|
|
st "registerFileSel : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "registerFileSel"
|
|
t "std_ulogic"
|
|
o 20
|
|
suid 17,0
|
|
)
|
|
)
|
|
)
|
|
*125 (CptPort
|
|
uid 136,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 137,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "45250,124625,46000,125375"
|
|
)
|
|
tg (CPTG
|
|
uid 138,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 139,0
|
|
va (VaSet
|
|
)
|
|
xt "47000,124500,49100,125500"
|
|
st "reset"
|
|
blo "47000,125300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 140,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,17400,21000,18200"
|
|
st "reset : IN std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 8
|
|
suid 18,0
|
|
)
|
|
)
|
|
)
|
|
*126 (CptPort
|
|
uid 141,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 142,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62000,89625,62750,90375"
|
|
)
|
|
tg (CPTG
|
|
uid 143,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 144,0
|
|
va (VaSet
|
|
)
|
|
xt "55400,89500,61000,90500"
|
|
st "scratchpadSel"
|
|
ju 2
|
|
blo "61000,90300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 145,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,28600,21000,29400"
|
|
st "scratchpadSel : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "scratchpadSel"
|
|
t "std_ulogic"
|
|
o 21
|
|
suid 19,0
|
|
)
|
|
)
|
|
)
|
|
*127 (CptPort
|
|
uid 146,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 147,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62000,119625,62750,120375"
|
|
)
|
|
tg (CPTG
|
|
uid 148,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 149,0
|
|
va (VaSet
|
|
)
|
|
xt "54700,119500,61000,120500"
|
|
st "scratchpadWrite"
|
|
ju 2
|
|
blo "61000,120300"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 150,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,29400,21000,30200"
|
|
st "scratchpadWrite : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "scratchpadWrite"
|
|
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