237 lines
8.5 KiB
VHDL
237 lines
8.5 KiB
VHDL
ARCHITECTURE RTL OF controller IS
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signal en1, enInt: std_ulogic;
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constant opCodeLength : integer := 5;
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subtype opCodeType is std_ulogic_vector(opCodeLength-1 downto 0);
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constant opLoad : opCodeType := "00000";
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constant opInput : opCodeType := "00010";
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constant opFetch : opCodeType := "00011";
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constant opAnd : opCodeType := "00101";
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constant opOr : opCodeType := "00110";
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constant opXor : opCodeType := "00111";
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constant opTest : opCodeType := "01001";
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constant opComp : opCodeType := "01010";
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constant opAdd : opCodeType := "01100";
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constant opAddCy : opCodeType := "01101";
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constant opSub : opCodeType := "01110";
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constant opSubCy : opCodeType := "01111";
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constant opShRot : opCodeType := "10000";
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constant opRet : opCodeType := "10101";
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constant opOutput: opCodeType := "10110";
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constant opStore : opCodeType := "10111";
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constant opCall : opCodeType := "11000";
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constant opJump : opCodeType := "11010";
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constant opIntF : opCodeType := "11110";
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constant branchConditionLength : integer := 3;
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subtype branchConditionType is std_ulogic_vector(branchConditionLength-1 downto 0);
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constant brAw : branchConditionType := "000";
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constant brZ : branchConditionType := "100";
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constant brNZ : branchConditionType := "101";
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constant brC : branchConditionType := "110";
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constant brNC : branchConditionType := "111";
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signal aluOpSel: std_ulogic;
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signal regWriteEn: std_ulogic;
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signal flagsEn, flagsEnable: std_ulogic;
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signal carrySaved: std_ulogic;
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signal zeroSaved: std_ulogic;
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signal branchEnable1, branchEnable: std_ulogic;
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signal discardOpCode: std_ulogic;
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signal updateIntFlag: std_ulogic;
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BEGIN
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------------------------------------------------------------------------------
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-- Enable signal
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buildEnable: process(reset, clock)
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begin
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if reset = '1' then
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en1 <= '0';
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elsif rising_edge(clock) then
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en1 <= '1';
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end if;
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end process buildEnable;
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enInt <= en1 and en; -- don't enable very first instruction twice
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------------------------------------------------------------------------------
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-- ALU controls
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selectdataSource: process(opCode)
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begin
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aluOpSel <= '0';
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portInSel <= '0';
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scratchpadSel <= '0';
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case opCode(opCodeLength-1 downto 0) is
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when opLoad => aluOpSel <= '1';
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when opInput => portInSel <= '1';
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when opFetch => scratchpadSel <= '1';
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when opAnd => aluOpSel <= '1';
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when opOr => aluOpSel <= '1';
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when opXor => aluOpSel <= '1';
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when opTest => aluOpSel <= '1';
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when opComp => aluOpSel <= '1';
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when opAdd => aluOpSel <= '1';
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when opAddCy => aluOpSel <= '1';
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when opSub => aluOpSel <= '1';
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when opSubCy => aluOpSel <= '1';
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when opShRot => aluOpSel <= '1';
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when others => aluOpSel <= '-';
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portInSel <= '-';
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scratchpadSel <= '-';
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end case;
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end process selectdataSource;
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registerFileSel <= aluOpSel and twoRegInstr;
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instrDataSel <= aluOpSel and (not twoRegInstr);
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regWriteEn <= enInt and (not discardOpCode);
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regWriteTable: process(opCode, regWriteEn)
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begin
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case opCode(opCodeLength-1 downto 0) is
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when opLoad => regWrite <= regWriteEn;
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when opInput => regWrite <= regWriteEn;
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when opFetch => regWrite <= regWriteEn;
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when opAnd => regWrite <= regWriteEn;
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when opOr => regWrite <= regWriteEn;
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when opXor => regWrite <= regWriteEn;
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when opAdd => regWrite <= regWriteEn;
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when opAddCy => regWrite <= regWriteEn;
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when opSub => regWrite <= regWriteEn;
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when opSubCy => regWrite <= regWriteEn;
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when opShRot => regWrite <= regWriteEn;
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when others => regWrite <= '0';
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end case;
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end process regWriteTable;
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------------------------------------------------------------------------------
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-- I/O controls
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readStrobe <= enInt when (opCode = opInput) and (discardOpCode = '0')
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else '0';
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writeStrobe <= enInt when (opCode = opOutput) and (discardOpCode = '0')
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else '0';
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------------------------------------------------------------------------------
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-- scratchpad controls
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scratchpadWrite <= '1' when opCode = opStore else '0';
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------------------------------------------------------------------------------
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-- Carry logic
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flagsEn <= enInt and (not branchEnable);
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flagsEnableTable: process(opCode, flagsEn)
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begin
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case opCode(opCodeLength-1 downto 0) is
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when opAnd => flagsEnable <= flagsEn;
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when opOr => flagsEnable <= flagsEn;
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when opXor => flagsEnable <= flagsEn;
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when opTest => flagsEnable <= flagsEn;
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when opComp => flagsEnable <= flagsEn;
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when opAdd => flagsEnable <= flagsEn;
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when opAddCy => flagsEnable <= flagsEn;
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when opSub => flagsEnable <= flagsEn;
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when opSubCy => flagsEnable <= flagsEn;
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when opShRot => flagsEnable <= flagsEn;
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when others => flagsEnable <= '0';
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end case;
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end process flagsEnableTable;
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saveCarries: process(reset, clock)
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begin
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if reset = '1' then
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carrySaved <= '0';
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zeroSaved <= '0';
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elsif rising_edge(clock) then
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if flagsEnable = '1' then
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carrySaved <= cOut;
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zeroSaved <= zero;
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end if;
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end if;
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end process saveCarries;
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cIn <= carrySaved;
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------------------------------------------------------------------------------
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-- Program counter controls
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checkBranchCondition: process(branchCond, zeroSaved, carrySaved)
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begin
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case branchCond(branchConditionLength-1 downto 0) is
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when brAw => branchEnable1 <= '1';
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when brZ => branchEnable1 <= zeroSaved;
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when brNZ => branchEnable1 <= not zeroSaved;
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when brC => branchEnable1 <= carrySaved;
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when brNC => branchEnable1 <= not carrySaved;
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when others => branchEnable1 <= '-';
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end case;
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end process checkBranchCondition;
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branchEnableTable: process(opCode, branchEnable1, discardOpCode)
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begin
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if discardOpCode = '0' then
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case opCode(opCodeLength-1 downto 0) is
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when opRet => branchEnable <= branchEnable1;
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when opCall => branchEnable <= branchEnable1;
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when opJump => branchEnable <= branchEnable1;
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when others => branchEnable <= '0';
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end case;
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else
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branchEnable <= '0';
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end if;
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end process branchEnableTable;
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progCounterControlTable: process(opCode, enInt, branchEnable)
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begin
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incPC <= enInt;
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loadInstrAddress <= '0';
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loadStoredPC <= '0';
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case opCode(opCodeLength-1 downto 0) is
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when opRet => incPC <= not branchEnable;
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loadStoredPC <= enInt and branchEnable;
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when opCall => incPC <= not branchEnable;
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loadInstrAddress <= enInt and branchEnable;
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when opJump => incPC <= not branchEnable;
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loadInstrAddress <= enInt and branchEnable;
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when others => null;
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end case;
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end process progCounterControlTable;
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-- If a branch condition is met, the next operation has to be discarded.
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-- This is due to the synchronous operation of the program ROM: the
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-- instructions are provided one clock period after the program counter.
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-- so while the branch operation is processed, the next instruction is
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-- already being fetched.
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delayBranchEnable: process(reset, clock)
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begin
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if reset = '1' then
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discardOpCode <= '0';
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elsif rising_edge(clock) then
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discardOpCode <= branchEnable;
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end if;
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end process delayBranchEnable;
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------------------------------------------------------------------------------
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-- Stack pointer controls
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pcStackControlTable: process(discardOpCode, opCode, enInt)
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begin
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storePC <= '0';
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prevPC <= '0';
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if discardOpCode = '0' then
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case opCode(opCodeLength-1 downto 0) is
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when opRet => prevPC <= enInt;
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when opCall => storePC <= enInt;
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when others => null;
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end case;
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end if;
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end process pcStackControlTable;
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------------------------------------------------------------------------------
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-- interrupt control
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updateIntFlag <= '1' when opCode = opIntF else '0';
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END ARCHITECTURE RTL;
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