2004 lines
25 KiB
Plaintext
2004 lines
25 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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ordering 1
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suid 2011,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 204,0
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optionalChildren [
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*2 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "interpolateLinear"
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t "std_ulogic"
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o 9
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suid 9,0
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)
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)
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uid 205,0
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)
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*3 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "updatePattern"
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t "std_ulogic"
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o 3
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suid 3,0
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)
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)
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uid 206,0
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)
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*4 (LogPort
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port (LogicalPort
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 7
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suid 7,0
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)
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)
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uid 207,0
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)
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*5 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "run"
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t "std_ulogic"
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o 1
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suid 1,0
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)
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)
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uid 208,0
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)
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*6 (LogPort
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port (LogicalPort
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decl (Decl
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n "dataIn"
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t "std_ulogic_vector"
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b "(dataBitNb-1 DOWNTO 0)"
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o 2
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suid 2,0
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)
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)
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uid 209,0
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)
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*7 (LogPort
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port (LogicalPort
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decl (Decl
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n "en"
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t "std_ulogic"
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o 6
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suid 6,0
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)
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)
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uid 210,0
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)
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*8 (LogPort
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port (LogicalPort
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decl (Decl
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n "reset"
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t "std_ulogic"
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o 8
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suid 8,0
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)
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)
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uid 211,0
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)
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*9 (LogPort
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port (LogicalPort
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decl (Decl
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n "write"
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t "std_ulogic"
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o 5
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suid 5,0
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)
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)
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uid 212,0
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)
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*10 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "dataOut"
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t "std_logic_vector"
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b "(dataBitNb-1 DOWNTO 0)"
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o 4
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suid 4,0
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)
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)
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uid 213,0
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)
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*11 (RefLabelRowHdr
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)
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*12 (TitleRowHdr
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)
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*13 (FilterRowHdr
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)
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*14 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*15 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*16 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*17 (NameColHdr
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tm "NameColHdrMgr"
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)
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*18 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*19 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*20 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*21 (InitColHdr
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tm "InitColHdrMgr"
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)
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*22 (EolColHdr
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tm "EolColHdrMgr"
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)
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*23 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "patternSize"
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t "unsigned"
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b "(patternSizeBitNb-1 downto 0)"
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o 10
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suid 2011,0
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)
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)
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uid 253,0
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)
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]
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)
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pdm (PhysicalDM
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uid 214,0
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optionalChildren [
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*24 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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emptyMRCItem *25 (MRCItem
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litem &1
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pos 10
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dimension 20
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)
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uid 141,0
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optionalChildren [
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*26 (MRCItem
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litem &11
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pos 0
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dimension 20
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uid 144,0
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)
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*27 (MRCItem
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litem &12
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pos 1
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dimension 23
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uid 146,0
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)
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*28 (MRCItem
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litem &13
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pos 2
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hidden 1
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dimension 20
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uid 148,0
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)
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*29 (MRCItem
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litem &2
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pos 8
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dimension 20
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uid 167,0
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)
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*30 (MRCItem
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litem &3
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pos 2
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dimension 20
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uid 168,0
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)
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*31 (MRCItem
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litem &4
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pos 6
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dimension 20
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uid 169,0
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)
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*32 (MRCItem
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litem &5
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pos 0
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dimension 20
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uid 170,0
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)
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*33 (MRCItem
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litem &6
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pos 1
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dimension 20
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uid 171,0
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)
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*34 (MRCItem
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litem &7
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pos 5
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dimension 20
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uid 172,0
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)
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*35 (MRCItem
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litem &8
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pos 7
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dimension 20
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uid 173,0
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)
|
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*36 (MRCItem
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litem &9
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pos 4
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dimension 20
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uid 174,0
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)
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*37 (MRCItem
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litem &10
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pos 3
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dimension 20
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uid 175,0
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)
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*38 (MRCItem
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litem &23
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pos 9
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dimension 20
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uid 254,0
|
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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textAngle 90
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)
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uid 142,0
|
|
optionalChildren [
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*39 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 150,0
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)
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*40 (MRCItem
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litem &16
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pos 1
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dimension 50
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uid 154,0
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)
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*41 (MRCItem
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litem &17
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pos 2
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dimension 100
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uid 156,0
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)
|
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*42 (MRCItem
|
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litem &18
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pos 3
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dimension 50
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uid 158,0
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)
|
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*43 (MRCItem
|
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litem &19
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pos 4
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dimension 100
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uid 160,0
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)
|
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*44 (MRCItem
|
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litem &20
|
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pos 5
|
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dimension 100
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uid 162,0
|
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)
|
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*45 (MRCItem
|
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litem &21
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pos 6
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dimension 50
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uid 164,0
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)
|
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*46 (MRCItem
|
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litem &22
|
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pos 7
|
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dimension 80
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uid 166,0
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)
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]
|
|
)
|
|
fixedCol 4
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fixedRow 2
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name "Ports"
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uid 140,0
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vaOverrides [
|
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]
|
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)
|
|
]
|
|
)
|
|
uid 203,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *47 (LEmptyRow
|
|
)
|
|
uid 216,0
|
|
optionalChildren [
|
|
*48 (RefLabelRowHdr
|
|
)
|
|
*49 (TitleRowHdr
|
|
)
|
|
*50 (FilterRowHdr
|
|
)
|
|
*51 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*52 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*53 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*54 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*55 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*56 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*57 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*58 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*59 (LogGeneric
|
|
generic (GiElement
|
|
name "dataBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
uid 201,0
|
|
)
|
|
*60 (LogGeneric
|
|
generic (GiElement
|
|
name "patternSizeBitNb"
|
|
type "positive"
|
|
value "8"
|
|
)
|
|
uid 255,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 217,0
|
|
optionalChildren [
|
|
*61 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *62 (MRCItem
|
|
litem &47
|
|
pos 2
|
|
dimension 20
|
|
)
|
|
uid 177,0
|
|
optionalChildren [
|
|
*63 (MRCItem
|
|
litem &48
|
|
pos 0
|
|
dimension 20
|
|
uid 180,0
|
|
)
|
|
*64 (MRCItem
|
|
litem &49
|
|
pos 1
|
|
dimension 23
|
|
uid 182,0
|
|
)
|
|
*65 (MRCItem
|
|
litem &50
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 184,0
|
|
)
|
|
*66 (MRCItem
|
|
litem &59
|
|
pos 0
|
|
dimension 20
|
|
uid 202,0
|
|
)
|
|
*67 (MRCItem
|
|
litem &60
|
|
pos 1
|
|
dimension 20
|
|
uid 256,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 178,0
|
|
optionalChildren [
|
|
*68 (MRCItem
|
|
litem &51
|
|
pos 0
|
|
dimension 20
|
|
uid 186,0
|
|
)
|
|
*69 (MRCItem
|
|
litem &53
|
|
pos 1
|
|
dimension 50
|
|
uid 190,0
|
|
)
|
|
*70 (MRCItem
|
|
litem &54
|
|
pos 2
|
|
dimension 100
|
|
uid 192,0
|
|
)
|
|
*71 (MRCItem
|
|
litem &55
|
|
pos 3
|
|
dimension 100
|
|
uid 194,0
|
|
)
|
|
*72 (MRCItem
|
|
litem &56
|
|
pos 4
|
|
dimension 50
|
|
uid 196,0
|
|
)
|
|
*73 (MRCItem
|
|
litem &57
|
|
pos 5
|
|
dimension 50
|
|
uid 198,0
|
|
)
|
|
*74 (MRCItem
|
|
litem &58
|
|
pos 6
|
|
dimension 80
|
|
uid 200,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 176,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 215,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
|
)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/periph@control@reg/symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/periph@control@reg/symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/periph@control@reg"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/periphControlReg"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "03/13/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "13"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "periphControlReg"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "03/13/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "14:40:20"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "SystemOnChip"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Generic_1_file"
|
|
value "U:\\SEm_curves\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSim"
|
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/SystemOnChip"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_SpyGlass"
|
|
value "U:\\SEm_curves\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "03"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "periphControlReg"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Mar"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "March"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/periph@control@reg/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/periphControlReg/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "systemOnChip"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "14:40:20"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "periphControlReg"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 51,0
|
|
optionalChildren [
|
|
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|
|
uid 8,0
|
|
optionalChildren [
|
|
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|
|
uid 57,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 82,0
|
|
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|
va (VaSet
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|
vasetType 1
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|
fg "0,65535,0"
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|
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|
|
xt "54000,12625,54750,13375"
|
|
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|
|
tg (CPTG
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|
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ps "CptPortTextPlaceStrategy"
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blo "53000,13100"
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tm "CptPortNameMgr"
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st "run : OUT std_ulogic ;"
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|
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|
|
m 1
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|
decl (Decl
|
|
n "run"
|
|
t "std_ulogic"
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|
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|
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)
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uid 83,0
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ps "OnEdgeStrategy"
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va (VaSet
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vasetType 1
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xt "37250,12625,38000,13375"
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tg (CPTG
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uid 85,0
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ps "CptPortTextPlaceStrategy"
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tm "CptPortNameMgr"
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thePort (LogicalPort
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decl (Decl
|
|
n "dataIn"
|
|
t "std_ulogic_vector"
|
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b "(dataBitNb-1 DOWNTO 0)"
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|
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|
|
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)
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*78 (CptPort
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uid 89,0
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ps "OnEdgeStrategy"
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va (VaSet
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vasetType 1
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blo "53000,19100"
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tm "CptPortNameMgr"
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st "updatePattern : OUT std_ulogic ;"
|
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)
|
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thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "updatePattern"
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|
t "std_ulogic"
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|
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|
|
suid 3,0
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)
|
|
)
|
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)
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*79 (CptPort
|
|
uid 109,0
|
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ps "OnEdgeStrategy"
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uid 119,0
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va (VaSet
|
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vasetType 1
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fg "0,65535,0"
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)
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tg (CPTG
|
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uid 111,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 112,0
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va (VaSet
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font "courier,9,0"
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)
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st "dataOut"
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blo "39000,15100"
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tm "CptPortNameMgr"
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dt (MLText
|
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uid 113,0
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va (VaSet
|
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font "courier,8,0"
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st "dataOut : OUT std_logic_vector (dataBitNb-1 DOWNTO 0) ;"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "dataOut"
|
|
t "std_logic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 4,0
|
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)
|
|
)
|
|
)
|
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*80 (CptPort
|
|
uid 114,0
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ps "OnEdgeStrategy"
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uid 115,0
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va (VaSet
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vasetType 1
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tg (CPTG
|
|
uid 116,0
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ps "CptPortTextPlaceStrategy"
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uid 117,0
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va (VaSet
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font "courier,9,0"
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tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
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font "courier,8,0"
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)
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thePort (LogicalPort
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decl (Decl
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n "write"
|
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t "std_ulogic"
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suid 5,0
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*81 (CptPort
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uid 120,0
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ps "OnEdgeStrategy"
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tg (CPTG
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uid 122,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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tm "CptPortNameMgr"
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uid 124,0
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va (VaSet
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font "courier,8,0"
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st "en : IN std_ulogic ;"
|
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)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "en"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 6,0
|
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)
|
|
)
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)
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*82 (CptPort
|
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uid 125,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 126,0
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va (VaSet
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vasetType 1
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tg (CPTG
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uid 127,0
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ps "CptPortTextPlaceStrategy"
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f (Text
|
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uid 128,0
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va (VaSet
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font "courier,9,0"
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xt "39000,24400,41500,25300"
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st "clock"
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blo "39000,25100"
|
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tm "CptPortNameMgr"
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)
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)
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dt (MLText
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uid 129,0
|
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va (VaSet
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font "courier,8,0"
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st "clock : IN std_ulogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 7
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|
suid 7,0
|
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)
|
|
)
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)
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*83 (CptPort
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uid 130,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 131,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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)
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tg (CPTG
|
|
uid 132,0
|
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 133,0
|
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va (VaSet
|
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font "courier,9,0"
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xt "39000,26400,41500,27300"
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st "reset"
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|
blo "39000,27100"
|
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tm "CptPortNameMgr"
|
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)
|
|
)
|
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dt (MLText
|
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uid 134,0
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va (VaSet
|
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font "courier,8,0"
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)
|
|
xt "2000,17100,22500,18000"
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|
st "reset : IN std_ulogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 8
|
|
suid 8,0
|
|
)
|
|
)
|
|
)
|
|
*84 (CptPort
|
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uid 135,0
|
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ps "OnEdgeStrategy"
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uid 136,0
|
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ro 90
|
|
va (VaSet
|
|
vasetType 1
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fg "0,65535,0"
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)
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)
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tg (CPTG
|
|
uid 137,0
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stg "RightVerticalLayoutStrategy"
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f (Text
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va (VaSet
|
|
font "courier,9,0"
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)
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st "interpolateLinear"
|
|
ju 2
|
|
blo "53000,15100"
|
|
tm "CptPortNameMgr"
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)
|
|
)
|
|
dt (MLText
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uid 139,0
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va (VaSet
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font "courier,8,0"
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)
|
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xt "2000,18000,22500,18900"
|
|
st "interpolateLinear : OUT std_ulogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
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decl (Decl
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n "interpolateLinear"
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|
t "std_ulogic"
|
|
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|
|
suid 9,0
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)
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)
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)
|
|
*85 (CptPort
|
|
uid 248,0
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uid 249,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
|
|
)
|
|
xt "54000,20625,54750,21375"
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|
)
|
|
tg (CPTG
|
|
uid 250,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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|
uid 251,0
|
|
va (VaSet
|
|
font "courier,9,0"
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|
)
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xt "47000,20400,53000,21300"
|
|
st "patternSize"
|
|
ju 2
|
|
blo "53000,21100"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 252,0
|
|
va (VaSet
|
|
font "courier,8,0"
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)
|
|
xt "2000,18900,35000,19800"
|
|
st "patternSize : OUT unsigned (patternSizeBitNb-1 downto 0)"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "patternSize"
|
|
t "unsigned"
|
|
b "(patternSizeBitNb-1 downto 0)"
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|
o 10
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|
suid 2011,0
|
|
)
|
|
)
|
|
)
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|
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shape (Rectangle
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vasetType 1
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fg "0,65535,0"
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bg "0,65535,0"
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lineColor "0,32896,0"
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lineWidth 2
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xt "38000,9000,54000,29000"
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|
)
|
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oxt "15000,6000,35000,26000"
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|
|
)
|
|
xt "0,750,3500,1650"
|
|
st "Buffer0"
|
|
blo "0,1450"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 3
|
|
decl (Decl
|
|
n "Buffer0"
|
|
t "std_logic_vector"
|
|
b "(15 DOWNTO 0)"
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
DeclarativeBlock *103 (SymDeclBlock
|
|
uid 1,0
|
|
stg "SymDeclLayoutStrategy"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "courier,8,1"
|
|
)
|
|
xt "0,9000,6500,9900"
|
|
st "Declarations"
|
|
blo "0,9700"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "courier,8,1"
|
|
)
|
|
xt "0,9900,3000,10800"
|
|
st "Ports:"
|
|
blo "0,10600"
|
|
)
|
|
externalLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "courier,8,1"
|
|
)
|
|
xt "0,19800,2500,20700"
|
|
st "User:"
|
|
blo "0,20500"
|
|
)
|
|
internalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "courier,8,1"
|
|
)
|
|
xt "0,9000,7500,9900"
|
|
st "Internal User:"
|
|
blo "0,9700"
|
|
)
|
|
externalText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,20700,2000,20700"
|
|
tm "SyDeclarativeTextMgr"
|
|
)
|
|
internalText (MLText
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "courier,8,0"
|
|
)
|
|
xt "0,9000,0,9000"
|
|
tm "SyDeclarativeTextMgr"
|
|
)
|
|
)
|
|
lastUid 325,0
|
|
activeModelName "Symbol"
|
|
)
|