SEm-Labos/06-07-08-09-SystemOnChip/SystemOnChip/hds/ahb@beamer@operator/struct.bd

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xt "19000,155100,45900,156100"
st "SIGNAL sampleX4            : signed(signalBitNb-1 DOWNTO 0)"
)
)
*26 (Net
uid 556,0
decl (Decl
n "aX"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 12
suid 18,0
)
declText (MLText
uid 557,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,139800,44500,140800"
st "SIGNAL aX                  : signed(coeffBitNb-1 DOWNTO 0)"
)
)
*27 (Net
uid 558,0
decl (Decl
n "bX"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 14
suid 19,0
)
declText (MLText
uid 559,0
va (VaSet
font "Verdana,8,0"
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xt "19000,141600,44500,142600"
st "SIGNAL bX                  : signed(coeffBitNb-1 DOWNTO 0)"
)
)
*28 (Net
uid 560,0
decl (Decl
n "cX"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 16
suid 20,0
)
declText (MLText
uid 561,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,143400,44400,144400"
st "SIGNAL cX                  : signed(coeffBitNb-1 DOWNTO 0)"
)
)
*29 (Net
uid 562,0
decl (Decl
n "dX"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 19
suid 21,0
)
declText (MLText
uid 563,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,146100,44500,147100"
st "SIGNAL dX                  : signed(coeffBitNb-1 DOWNTO 0)"
)
)
*30 (Net
uid 865,0
decl (Decl
n "samplesY"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 36
suid 22,0
)
declText (MLText
uid 866,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,161400,45800,162400"
st "SIGNAL samplesY            : signed(signalBitNb-1 DOWNTO 0)"
)
)
*31 (Net
uid 867,0
decl (Decl
n "sampleY1"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 31
suid 23,0
)
declText (MLText
uid 868,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,156900,45900,157900"
st "SIGNAL sampleY1            : signed(signalBitNb-1 DOWNTO 0)"
)
)
*32 (Net
uid 869,0
decl (Decl
n "sampleY2"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 32
suid 24,0
)
declText (MLText
uid 870,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,157800,45900,158800"
st "SIGNAL sampleY2            : signed(signalBitNb-1 DOWNTO 0)"
)
)
*33 (Net
uid 871,0
decl (Decl
n "sampleY3"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 33
suid 25,0
)
declText (MLText
uid 872,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,158700,45900,159700"
st "SIGNAL sampleY3            : signed(signalBitNb-1 DOWNTO 0)"
)
)
*34 (Net
uid 873,0
decl (Decl
n "sampleY4"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 34
suid 26,0
)
declText (MLText
uid 874,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,159600,45900,160600"
st "SIGNAL sampleY4            : signed(signalBitNb-1 DOWNTO 0)"
)
)
*35 (Net
uid 875,0
decl (Decl
n "aY"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 13
suid 27,0
)
declText (MLText
uid 876,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,140700,44500,141700"
st "SIGNAL aY                  : signed(coeffBitNb-1 DOWNTO 0)"
)
)
*36 (Net
uid 877,0
decl (Decl
n "bY"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 15
suid 28,0
)
declText (MLText
uid 878,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,142500,44500,143500"
st "SIGNAL bY                  : signed(coeffBitNb-1 DOWNTO 0)"
)
)
*37 (Net
uid 879,0
decl (Decl
n "cY"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 17
suid 29,0
)
declText (MLText
uid 880,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,144300,44400,145300"
st "SIGNAL cY                  : signed(coeffBitNb-1 DOWNTO 0)"
)
)
*38 (Net
uid 881,0
decl (Decl
n "dY"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 20
suid 30,0
)
declText (MLText
uid 882,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,147000,44500,148000"
st "SIGNAL dY                  : signed(coeffBitNb-1 DOWNTO 0)"
)
)
*39 (Net
uid 883,0
decl (Decl
n "sampleY"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 30
suid 31,0
)
declText (MLText
uid 884,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,156000,45700,157000"
st "SIGNAL sampleY             : signed(signalBitNb-1 DOWNTO 0)"
)
)
*40 (Net
uid 885,0
decl (Decl
n "unsignedY"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 40
suid 32,0
)
declText (MLText
uid 886,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,165000,46800,166000"
st "SIGNAL unsignedY           : unsigned(signalBitNb-1 DOWNTO 0)"
)
)
*41 (Net
uid 1348,0
decl (Decl
n "run"
t "std_ulogic"
o 2
suid 38,0
)
declText (MLText
uid 1349,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,123600,31600,124600"
st "run                 : std_ulogic"
)
)
*42 (Net
uid 1776,0
decl (Decl
n "updatePeriod"
t "unsigned"
b "(updatePeriodBitNb-1 DOWNTO 0)"
o 8
suid 42,0
)
declText (MLText
uid 1777,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,129000,46900,130000"
st "updatePeriod        : unsigned(updatePeriodBitNb-1 DOWNTO 0)"
)
)
*43 (Net
uid 1993,0
decl (Decl
n "interpolationEnable"
t "std_ulogic"
o 23
suid 43,0
)
declText (MLText
uid 1994,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,149700,36400,150700"
st "SIGNAL interpolationEnable : std_ulogic"
)
)
*44 (HdlText
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optionalChildren [
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uid 3140,0
commentText (CommentText
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shape (Rectangle
uid 3142,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
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xt "132000,152000,146000,156000"
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oxt "0,0,18000,5000"
text (MLText
uid 3143,0
va (VaSet
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xt "132200,152200,144900,155800"
st "
samplesX <= cosine when selSinCos = '1'
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"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4000
visibleWidth 14000
)
)
)
]
shape (Rectangle
uid 3136,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
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xt "131000,150000,147000,158000"
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oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 3137,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*46 (Text
uid 3138,0
va (VaSet
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xt "131400,158000,134000,159200"
st "eb2"
blo "131400,159000"
tm "HdlTextNameMgr"
)
*47 (Text
uid 3139,0
va (VaSet
)
xt "131400,159000,132800,160200"
st "2"
blo "131400,160000"
tm "HdlTextNumberMgr"
)
]
)
)
*48 (Net
uid 3152,0
decl (Decl
n "memX"
t "std_ulogic_vector"
b "(signalBitNb-1 DOWNTO 0)"
o 9
suid 48,0
)
declText (MLText
uid 3153,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,129900,47000,130900"
st "memX                : std_ulogic_vector(signalBitNb-1 DOWNTO 0)"
)
)
*49 (HdlText
uid 3896,0
optionalChildren [
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uid 3901,0
commentText (CommentText
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shape (Rectangle
uid 3903,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
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xt "132000,115000,146000,119000"
)
oxt "0,0,18000,5000"
text (MLText
uid 3904,0
va (VaSet
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xt "132200,115200,144900,118800"
st "
samplesY <= sine when selSinCos = '1'
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"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4000
visibleWidth 14000
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)
)
]
shape (Rectangle
uid 3897,0
va (VaSet
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fg "65535,65535,32768"
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xt "131000,113000,147000,121000"
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oxt "0,0,8000,10000"
ttg (MlTextGroup
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ps "CenterOffsetStrategy"
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*51 (Text
uid 3899,0
va (VaSet
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xt "131400,121000,134000,122200"
st "eb1"
blo "131400,122000"
tm "HdlTextNameMgr"
)
*52 (Text
uid 3900,0
va (VaSet
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xt "131400,122000,132800,123200"
st "1"
blo "131400,123000"
tm "HdlTextNumberMgr"
)
]
)
)
*53 (Net
uid 3913,0
decl (Decl
n "memY"
t "std_ulogic_vector"
b "(signalBitNb-1 DOWNTO 0)"
o 10
suid 53,0
)
declText (MLText
uid 3914,0
va (VaSet
font "Verdana,8,0"
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xt "19000,130800,47000,131800"
st "memY                : std_ulogic_vector(signalBitNb-1 DOWNTO 0)"
)
)
*54 (HdlText
uid 4719,0
optionalChildren [
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commentText (CommentText
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ps "CenterOffsetStrategy"
shape (Rectangle
uid 4726,0
va (VaSet
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fg "65535,65535,65535"
lineStyle 2
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xt "64000,141000,78000,143000"
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oxt "0,0,18000,5000"
text (MLText
uid 4727,0
va (VaSet
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xt "64200,141200,78000,142400"
st "
step <= to_unsigned(1, step'length);
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tm "HdlTextMgr"
wrapOption 3
visibleHeight 2000
visibleWidth 14000
)
)
)
]
shape (Rectangle
uid 4720,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
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xt "63000,140000,79000,144000"
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oxt "0,0,8000,10000"
ttg (MlTextGroup
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ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
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uid 4722,0
va (VaSet
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xt "63400,144000,66000,145200"
st "eb4"
blo "63400,145000"
tm "HdlTextNameMgr"
)
*57 (Text
uid 4723,0
va (VaSet
)
xt "63400,145000,64800,146200"
st "4"
blo "63400,146000"
tm "HdlTextNumberMgr"
)
]
)
)
*58 (Net
uid 4800,0
decl (Decl
n "phase"
t "unsigned"
b "(phaseBitNb-1 DOWNTO 0)"
o 24
suid 57,0
)
declText (MLText
uid 4801,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,150600,46400,151600"
st "SIGNAL phase               : unsigned(phaseBitNb-1 DOWNTO 0)"
)
)
*59 (Net
uid 4802,0
decl (Decl
n "step"
t "unsigned"
b "(phaseBitNb-1 DOWNTO 0)"
o 38
suid 58,0
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declText (MLText
uid 4803,0
va (VaSet
font "Verdana,8,0"
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xt "19000,163200,46000,164200"
st "SIGNAL step                : unsigned(phaseBitNb-1 DOWNTO 0)"
)
)
*60 (Net
uid 4858,0
decl (Decl
n "sine"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 37
suid 59,0
)
declText (MLText
uid 4859,0
va (VaSet
font "Verdana,8,0"
)
xt "19000,162300,44800,163300"
st "SIGNAL sine                : signed(signalBitNb-1 DOWNTO 0)"
)
)
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uid 5080,0
shape (CompositeShape
uid 5081,0
va (VaSet
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fg "0,0,32768"
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optionalChildren [
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uid 5082,0
sl 0
ro 270
xt "89000,108625,90500,109375"
)
(Line
uid 5083,0
sl 0
ro 270
xt "90500,109000,91000,109000"
pts [
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"91000,109000"
]
)
]
)
tg (WTG
uid 5084,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5085,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "81100,108300,88000,109700"
st "selSinCos"
ju 2
blo "88000,109500"
tm "WireNameMgr"
)
)
)
*62 (HdlText
uid 5244,0
optionalChildren [
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uid 5249,0
commentText (CommentText
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ps "CenterOffsetStrategy"
shape (Rectangle
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va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
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xt "99000,104000,115000,114000"
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oxt "0,0,18000,5000"
text (MLText
uid 5252,0
va (VaSet
)
xt "99200,104200,114600,113800"
st "
interpolationEnable <= '1' when selSinCos = '1'
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interpolateLinear <= '0' when selSinCos = '1'
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--interpolateLinear <= interpolateLin;

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 10000
visibleWidth 16000
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)
)
]
shape (Rectangle
uid 5245,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "99000,103000,115000,115000"
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oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 5246,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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uid 5247,0
va (VaSet
)
xt "99400,115000,102000,116200"
st "eb5"
blo "99400,116000"
tm "HdlTextNameMgr"
)
*65 (Text
uid 5248,0
va (VaSet
)
xt "99400,116000,100800,117200"
st "5"
blo "99400,117000"
tm "HdlTextNumberMgr"
)
]
)
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*66 (Net
uid 5261,0
decl (Decl
n "interpolationEn"
t "std_ulogic"
o 22
suid 60,0
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declText (MLText
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va (VaSet
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xt "19000,148800,35900,149800"
st "SIGNAL interpolationEn     : std_ulogic"
)
)
*67 (Net
uid 5936,0
decl (Decl
n "cosine"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 18
suid 61,0
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declText (MLText
uid 5937,0
va (VaSet
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xt "19000,145200,45100,146200"
st "SIGNAL cosine              : signed(signalBitNb-1 DOWNTO 0)"
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*68 (Net
uid 6503,0
decl (Decl
n "selSinCos"
t "std_ulogic"
o 6
suid 62,0
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declText (MLText
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va (VaSet
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xt "19000,127200,32300,128200"
st "selSinCos           : std_ulogic"
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uid 8148,0
decl (Decl
n "interpolateLinear"
t "std_ulogic"
o 21
suid 69,0
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declText (MLText
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va (VaSet
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xt "19000,147900,36000,148900"
st "SIGNAL interpolateLinear   : std_ulogic"
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uid 9646,0
decl (Decl
n "interpolateLin"
t "std_ulogic"
o 7
suid 70,0
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declText (MLText
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va (VaSet
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xt "19000,128100,32400,129100"
st "interpolateLin      : std_ulogic"
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)
*71 (PortIoIn
uid 15558,0
shape (CompositeShape
uid 15559,0
va (VaSet
vasetType 1
fg "0,0,32768"
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optionalChildren [
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uid 15560,0
sl 0
ro 270
xt "49000,112625,50500,113375"
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(Line
uid 15561,0
sl 0
ro 270
xt "50500,113000,51000,113000"
pts [
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"51000,113000"
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)
]
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tg (WTG
uid 15562,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15563,0
va (VaSet
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font "Verdana,12,0"
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xt "44200,112500,48000,113900"
st "clock"
ju 2
blo "48000,113700"
tm "WireNameMgr"
)
)
)
*72 (PortIoIn
uid 15570,0
shape (CompositeShape
uid 15571,0
va (VaSet
vasetType 1
fg "0,0,32768"
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optionalChildren [
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uid 15572,0
sl 0
ro 270
xt "89000,110625,90500,111375"
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(Line
uid 15573,0
sl 0
ro 270
xt "90500,111000,91000,111000"
pts [
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"91000,111000"
]
)
]
)
tg (WTG
uid 15574,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15575,0
va (VaSet
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font "Verdana,12,0"
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xt "77700,110500,88000,111900"
st "interpolateLin"
ju 2
blo "88000,111700"
tm "WireNameMgr"
)
)
)
*73 (PortIoIn
uid 15582,0
shape (CompositeShape
uid 15583,0
va (VaSet
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fg "0,0,32768"
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optionalChildren [
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uid 15584,0
sl 0
ro 270
xt "121000,153625,122500,154375"
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(Line
uid 15585,0
sl 0
ro 270
xt "122500,154000,123000,154000"
pts [
"122500,154000"
"123000,154000"
]
)
]
)
tg (WTG
uid 15586,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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font "Verdana,12,0"
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xt "95800,153500,120000,154900"
st "memX : (signalBitNb-1 DOWNTO 0)"
ju 2
blo "120000,154700"
tm "WireNameMgr"
)
)
)
*74 (PortIoIn
uid 15594,0
shape (CompositeShape
uid 15595,0
va (VaSet
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optionalChildren [
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uid 15596,0
sl 0
ro 270
xt "49000,114625,50500,115375"
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(Line
uid 15597,0
sl 0
ro 270
xt "50500,115000,51000,115000"
pts [
"50500,115000"
"51000,115000"
]
)
]
)
tg (WTG
uid 15598,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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font "Verdana,12,0"
)
xt "43900,114500,48000,115900"
st "reset"
ju 2
blo "48000,115700"
tm "WireNameMgr"
)
)
)
*75 (PortIoIn
uid 15606,0
shape (CompositeShape
uid 15607,0
va (VaSet
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fg "0,0,32768"
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optionalChildren [
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uid 15608,0
sl 0
ro 270
xt "49000,106625,50500,107375"
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(Line
uid 15609,0
sl 0
ro 270
xt "50500,107000,51000,107000"
pts [
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"51000,107000"
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)
]
)
tg (WTG
uid 15610,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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font "Verdana,12,0"
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xt "45100,106500,48000,107900"
st "run"
ju 2
blo "48000,107700"
tm "WireNameMgr"
)
)
)
*76 (PortIoIn
uid 15632,0
shape (CompositeShape
uid 15633,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
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uid 15634,0
sl 0
ro 270
xt "49000,108625,50500,109375"
)
(Line
uid 15635,0
sl 0
ro 270
xt "50500,109000,51000,109000"
pts [
"50500,109000"
"51000,109000"
]
)
]
)
tg (WTG
uid 15636,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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font "Verdana,12,0"
)
xt "13500,108500,48000,109900"
st "updatePeriod : (updatePeriodBitNb-1 DOWNTO 0)"
ju 2
blo "48000,109700"
tm "WireNameMgr"
)
)
)
*77 (PortIoIn
uid 16404,0
shape (CompositeShape
uid 16405,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 16406,0
sl 0
ro 270
xt "121000,116625,122500,117375"
)
(Line
uid 16407,0
sl 0
ro 270
xt "122500,117000,123000,117000"
pts [
"122500,117000"
"123000,117000"
]
)
]
)
tg (WTG
uid 16408,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16409,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "95900,116500,120000,117900"
st "memY : (signalBitNb-1 DOWNTO 0)"
ju 2
blo "120000,117700"
tm "WireNameMgr"
)
)
)
*78 (PortIoOut
uid 16674,0
shape (CompositeShape
uid 16675,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 16676,0
sl 0
ro 270
xt "209500,175625,211000,176375"
)
(Line
uid 16677,0
sl 0
ro 270
xt "209000,176000,209500,176000"
pts [
"209000,176000"
"209500,176000"
]
)
]
)
tg (WTG
uid 16678,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16679,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "212000,175500,221600,176900"
st "newPolynom"
blo "212000,176700"
tm "WireNameMgr"
)
)
)
*79 (SaComponent
uid 17519,0
optionalChildren [
*80 (CptPort
uid 17499,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17500,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "75000,106625,75750,107375"
)
tg (CPTG
uid 17501,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17502,0
va (VaSet
)
xt "68100,106400,74000,107600"
st "enableOut"
ju 2
blo "74000,107400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "enableOut"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*81 (CptPort
uid 17503,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17504,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58250,112625,59000,113375"
)
tg (CPTG
uid 17505,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17506,0
va (VaSet
)
xt "60000,112400,63400,113600"
st "clock"
blo "60000,113400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*82 (CptPort
uid 17507,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17508,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58250,114625,59000,115375"
)
tg (CPTG
uid 17509,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17510,0
va (VaSet
)
xt "60000,114400,63300,115600"
st "reset"
blo "60000,115400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*83 (CptPort
uid 17511,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17512,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58250,108625,59000,109375"
)
tg (CPTG
uid 17513,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17514,0
va (VaSet
)
xt "60000,108400,68000,109600"
st "updatePeriod"
blo "60000,109400"
)
)
thePort (LogicalPort
decl (Decl
n "updatePeriod"
t "unsigned"
b "(updatePeriodBitNb-1 DOWNTO 0)"
o 4
suid 4,0
)
)
)
*84 (CptPort
uid 17515,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17516,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58250,106625,59000,107375"
)
tg (CPTG
uid 17517,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17518,0
va (VaSet
)
xt "60000,106400,65100,107600"
st "enableIn"
blo "60000,107400"
)
)
thePort (LogicalPort
decl (Decl
n "enableIn"
t "std_ulogic"
o 5
suid 5,0
)
)
)
]
shape (Rectangle
uid 17520,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "59000,103000,75000,117000"
)
oxt "40000,11000,56000,25000"
ttg (MlTextGroup
uid 17521,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*85 (Text
uid 17522,0
va (VaSet
font "Verdana,9,1"
)
xt "59600,116800,68000,118000"
st "SystemOnChip"
blo "59600,117800"
tm "BdLibraryNameMgr"
)
*86 (Text
uid 17523,0
va (VaSet
font "Verdana,9,1"
)
xt "59600,117700,72400,118900"
st "periphSpeedController"
blo "59600,118700"
tm "CptNameMgr"
)
*87 (Text
uid 17524,0
va (VaSet
font "Verdana,9,1"
)
xt "59600,118600,64200,119800"
st "I_speed"
blo "59600,119600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 17525,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 17526,0
text (MLText
uid 17527,0
va (VaSet
font "Verdana,8,0"
)
xt "59000,120600,83400,121600"
st "updatePeriodBitNb = updatePeriodBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "updatePeriodBitNb"
type "positive"
value "updatePeriodBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*88 (SaComponent
uid 17540,0
optionalChildren [
*89 (CptPort
uid 17528,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17529,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "115000,149625,115750,150375"
)
tg (CPTG
uid 17530,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17531,0
va (VaSet
)
xt "111200,149400,114000,150600"
st "sine"
ju 2
blo "114000,150400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sine"
t "signed"
b "(outputBitNb-1 DOWNTO 0)"
o 1
suid 1,0
)
)
)
*90 (CptPort
uid 17532,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17533,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "98250,149625,99000,150375"
)
tg (CPTG
uid 17534,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17535,0
va (VaSet
)
xt "100000,149400,103700,150600"
st "phase"
blo "100000,150400"
)
)
thePort (LogicalPort
decl (Decl
n "phase"
t "unsigned"
b "(inputBitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*91 (CptPort
uid 17536,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17537,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "115000,151625,115750,152375"
)
tg (CPTG
uid 17538,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17539,0
va (VaSet
)
xt "110000,151400,114000,152600"
st "cosine"
ju 2
blo "114000,152400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "cosine"
t "signed"
b "(outputBitNb-1 DOWNTO 0)"
o 3
suid 3,0
)
)
)
]
shape (Rectangle
uid 17541,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "99000,146000,115000,156000"
)
oxt "32000,8000,48000,18000"
ttg (MlTextGroup
uid 17542,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*92 (Text
uid 17543,0
va (VaSet
font "Verdana,9,1"
)
xt "99600,155800,108000,157000"
st "SystemOnChip"
blo "99600,156800"
tm "BdLibraryNameMgr"
)
*93 (Text
uid 17544,0
va (VaSet
font "Verdana,9,1"
)
xt "99600,156700,106600,157900"
st "sinCosTable"
blo "99600,157700"
tm "CptNameMgr"
)
*94 (Text
uid 17545,0
va (VaSet
font "Verdana,9,1"
)
xt "99600,157600,102700,158800"
st "I_sin"
blo "99600,158600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 17546,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 17547,0
text (MLText
uid 17548,0
va (VaSet
font "Verdana,8,0"
)
xt "99000,159000,123000,162000"
st "inputBitNb        = phaseBitNb           ( positive )  
outputBitNb       = signalBitNb          ( positive )  
tableAddressBitNb = tableAddressBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "inputBitNb"
type "positive"
value "phaseBitNb"
)
(GiElement
name "outputBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "tableAddressBitNb"
type "positive"
value "tableAddressBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*95 (SaComponent
uid 17565,0
optionalChildren [
*96 (CptPort
uid 17549,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17550,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "264250,120625,265000,121375"
)
tg (CPTG
uid 17551,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17552,0
va (VaSet
)
xt "266000,120400,269400,121600"
st "clock"
blo "266000,121400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 3
suid 1,0
)
)
)
*97 (CptPort
uid 17553,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17554,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "264250,116625,265000,117375"
)
tg (CPTG
uid 17555,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17556,0
va (VaSet
)
xt "266000,116400,272200,117600"
st "parallelIn"
blo "266000,117400"
)
)
thePort (LogicalPort
decl (Decl
n "parallelIn"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*98 (CptPort
uid 17557,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17558,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "281000,116625,281750,117375"
)
tg (CPTG
uid 17559,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17560,0
va (VaSet
)
xt "274601,116400,280001,117600"
st "serialOut"
ju 2
blo "280001,117400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "serialOut"
t "std_ulogic"
o 1
suid 3,0
)
)
)
*99 (CptPort
uid 17561,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17562,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "264250,122625,265000,123375"
)
tg (CPTG
uid 17563,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17564,0
va (VaSet
)
xt "266000,122400,269300,123600"
st "reset"
blo "266000,123400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 4
suid 4,0
)
)
)
]
shape (Rectangle
uid 17566,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "265000,113000,281000,125000"
)
oxt "32000,14000,48000,26000"
ttg (MlTextGroup
uid 17567,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*100 (Text
uid 17568,0
va (VaSet
font "Verdana,9,1"
)
xt "265600,124800,280300,126000"
st "DigitalToAnalogConverter"
blo "265600,125800"
tm "BdLibraryNameMgr"
)
*101 (Text
uid 17569,0
va (VaSet
font "Verdana,9,1"
)
xt "265600,125700,268300,126900"
st "DAC"
blo "265600,126700"
tm "CptNameMgr"
)
*102 (Text
uid 17570,0
va (VaSet
font "Verdana,9,1"
)
xt "265600,126600,269600,127800"
st "I_dacy"
blo "265600,127600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 17571,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 17572,0
text (MLText
uid 17573,0
va (VaSet
font "Verdana,8,0"
)
xt "265000,128600,283400,129600"
st "signalBitNb = signalBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*103 (SaComponent
uid 17590,0
optionalChildren [
*104 (CptPort
uid 17574,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17575,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "264250,157625,265000,158375"
)
tg (CPTG
uid 17576,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17577,0
va (VaSet
)
xt "266000,157400,269400,158600"
st "clock"
blo "266000,158400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 3
suid 1,0
)
)
)
*105 (CptPort
uid 17578,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17579,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "264250,153625,265000,154375"
)
tg (CPTG
uid 17580,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17581,0
va (VaSet
)
xt "266000,153400,272200,154600"
st "parallelIn"
blo "266000,154400"
)
)
thePort (LogicalPort
decl (Decl
n "parallelIn"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*106 (CptPort
uid 17582,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17583,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "281000,153625,281750,154375"
)
tg (CPTG
uid 17584,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17585,0
va (VaSet
)
xt "274601,153400,280001,154600"
st "serialOut"
ju 2
blo "280001,154400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "serialOut"
t "std_ulogic"
o 1
suid 3,0
)
)
)
*107 (CptPort
uid 17586,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17587,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "264250,159625,265000,160375"
)
tg (CPTG
uid 17588,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17589,0
va (VaSet
)
xt "266000,159400,269300,160600"
st "reset"
blo "266000,160400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 4
suid 4,0
)
)
)
]
shape (Rectangle
uid 17591,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "265000,150000,281000,162000"
)
oxt "32000,14000,48000,26000"
ttg (MlTextGroup
uid 17592,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*108 (Text
uid 17593,0
va (VaSet
font "Verdana,9,1"
)
xt "265600,161800,280300,163000"
st "DigitalToAnalogConverter"
blo "265600,162800"
tm "BdLibraryNameMgr"
)
*109 (Text
uid 17594,0
va (VaSet
font "Verdana,9,1"
)
xt "265600,162700,268300,163900"
st "DAC"
blo "265600,163700"
tm "CptNameMgr"
)
*110 (Text
uid 17595,0
va (VaSet
font "Verdana,9,1"
)
xt "265600,163600,269600,164800"
st "I_dacx"
blo "265600,164600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 17596,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 17597,0
text (MLText
uid 17598,0
va (VaSet
font "Verdana,8,0"
)
xt "265000,165600,283400,166600"
st "signalBitNb = signalBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*111 (SaComponent
uid 17619,0
optionalChildren [
*112 (CptPort
uid 17599,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17600,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,155625,75000,156375"
)
tg (CPTG
uid 17601,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17602,0
va (VaSet
)
xt "76000,155400,79400,156600"
st "clock"
blo "76000,156400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 1,0
)
)
)
*113 (CptPort
uid 17603,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17604,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,149625,91750,150375"
)
tg (CPTG
uid 17605,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17606,0
va (VaSet
)
xt "84800,149400,90000,150600"
st "sawtooth"
ju 2
blo "90000,150400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sawtooth"
t "unsigned"
b "(bitNb-1 DOWNTO 0)"
o 1
suid 2,0
)
)
)
*114 (CptPort
uid 17607,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17608,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,157625,75000,158375"
)
tg (CPTG
uid 17609,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17610,0
va (VaSet
)
xt "76000,157400,79300,158600"
st "reset"
blo "76000,158400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*115 (CptPort
uid 17611,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17612,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,149625,75000,150375"
)
tg (CPTG
uid 17613,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17614,0
va (VaSet
)
xt "76000,149400,78900,150600"
st "step"
blo "76000,150400"
)
)
thePort (LogicalPort
decl (Decl
n "step"
t "unsigned"
b "(bitNb-1 DOWNTO 0)"
o 4
suid 4,0
)
)
)
*116 (CptPort
uid 17615,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17616,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,153625,75000,154375"
)
tg (CPTG
uid 17617,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17618,0
va (VaSet
)
xt "76000,153400,77900,154600"
st "en"
blo "76000,154400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 5
suid 5,0
)
)
)
]
shape (Rectangle
uid 17620,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "75000,146000,91000,160000"
)
oxt "32000,8000,48000,22000"
ttg (MlTextGroup
uid 17621,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*117 (Text
uid 17622,0
va (VaSet
font "Verdana,9,1"
)
xt "75600,159800,87100,161000"
st "WaveformGenerator"
blo "75600,160800"
tm "BdLibraryNameMgr"
)
*118 (Text
uid 17623,0
va (VaSet
font "Verdana,9,1"
)
xt "75600,160700,83500,161900"
st "sawtoothGen"
blo "75600,161700"
tm "CptNameMgr"
)
*119 (Text
uid 17624,0
va (VaSet
font "Verdana,9,1"
)
xt "75600,161600,80200,162800"
st "I_phase"
blo "75600,162600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 17625,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 17626,0
text (MLText
uid 17627,0
va (VaSet
font "Verdana,8,0"
)
xt "75000,163600,90700,164600"
st "bitNb = phaseBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "bitNb"
type "positive"
value "phaseBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*120 (SaComponent
uid 17644,0
optionalChildren [
*121 (CptPort
uid 17628,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17629,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,175625,177750,176375"
)
tg (CPTG
uid 17630,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17631,0
va (VaSet
)
xt "169400,175400,176000,176600"
st "triggerOut"
ju 2
blo "176000,176400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "triggerOut"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*122 (CptPort
uid 17632,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17633,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,179625,161000,180375"
)
tg (CPTG
uid 17634,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17635,0
va (VaSet
)
xt "162000,179400,165400,180600"
st "clock"
blo "162000,180400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*123 (CptPort
uid 17636,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17637,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,181625,161000,182375"
)
tg (CPTG
uid 17638,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17639,0
va (VaSet
)
xt "162000,181400,165300,182600"
st "reset"
blo "162000,182400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*124 (CptPort
uid 17640,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17641,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,175625,161000,176375"
)
tg (CPTG
uid 17642,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17643,0
va (VaSet
)
xt "162000,175400,163900,176600"
st "en"
blo "162000,176400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 4
suid 4,0
)
)
)
]
shape (Rectangle
uid 17645,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "161000,172000,177000,184000"
)
oxt "32000,6000,48000,18000"
ttg (MlTextGroup
uid 17646,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*125 (Text
uid 17647,0
va (VaSet
font "Verdana,9,1"
)
xt "161600,183800,172000,185000"
st "SplineInterpolator"
blo "161600,184800"
tm "BdLibraryNameMgr"
)
*126 (Text
uid 17648,0
va (VaSet
font "Verdana,9,1"
)
xt "161600,184700,172300,185900"
st "interpolatorTrigger"
blo "161600,185700"
tm "CptNameMgr"
)
*127 (Text
uid 17649,0
va (VaSet
font "Verdana,9,1"
)
xt "161600,185600,165100,186800"
st "I_trig"
blo "161600,186600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 17650,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 17651,0
text (MLText
uid 17652,0
va (VaSet
font "Verdana,8,0"
)
xt "161000,187600,183100,188600"
st "counterBitNb = sampleCountBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "counterBitNb"
type "positive"
value "sampleCountBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*128 (SaComponent
uid 17685,0
optionalChildren [
*129 (CptPort
uid 17653,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17654,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,159625,161000,160375"
)
tg (CPTG
uid 17655,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17656,0
va (VaSet
)
xt "162000,159400,165400,160600"
st "clock"
blo "162000,160400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*130 (CptPort
uid 17657,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17658,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,161625,161000,162375"
)
tg (CPTG
uid 17659,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17660,0
va (VaSet
)
xt "162000,161400,165300,162600"
st "reset"
blo "162000,162400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*131 (CptPort
uid 17661,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17662,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,155625,161000,156375"
)
tg (CPTG
uid 17663,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17664,0
va (VaSet
)
xt "162000,155400,169900,156600"
st "shiftSamples"
blo "162000,156400"
)
)
thePort (LogicalPort
decl (Decl
n "shiftSamples"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*132 (CptPort
uid 17665,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17666,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,153625,161000,154375"
)
tg (CPTG
uid 17667,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17668,0
va (VaSet
)
xt "162000,153400,167400,154600"
st "sampleIn"
blo "162000,154400"
)
)
thePort (LogicalPort
decl (Decl
n "sampleIn"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 4
suid 4,0
)
)
)
*133 (CptPort
uid 17669,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17670,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,153625,177750,154375"
)
tg (CPTG
uid 17671,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17672,0
va (VaSet
)
xt "171000,153400,176000,154600"
st "sample1"
ju 2
blo "176000,154400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample1"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 5
suid 5,0
)
)
)
*134 (CptPort
uid 17673,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17674,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,155625,177750,156375"
)
tg (CPTG
uid 17675,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17676,0
va (VaSet
)
xt "171000,155400,176000,156600"
st "sample2"
ju 2
blo "176000,156400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample2"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 6
suid 6,0
)
)
)
*135 (CptPort
uid 17677,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17678,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,157625,177750,158375"
)
tg (CPTG
uid 17679,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17680,0
va (VaSet
)
xt "171000,157400,176000,158600"
st "sample3"
ju 2
blo "176000,158400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample3"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 7
suid 7,0
)
)
)
*136 (CptPort
uid 17681,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17682,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,159625,177750,160375"
)
tg (CPTG
uid 17683,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17684,0
va (VaSet
)
xt "171000,159400,176000,160600"
st "sample4"
ju 2
blo "176000,160400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample4"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 8
suid 8,0
)
)
)
]
shape (Rectangle
uid 17686,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "161000,150000,177000,164000"
)
oxt "35000,9000,51000,23000"
ttg (MlTextGroup
uid 17687,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*137 (Text
uid 17688,0
va (VaSet
font "Verdana,9,1"
)
xt "161600,163800,172000,165000"
st "SplineInterpolator"
blo "161600,164800"
tm "BdLibraryNameMgr"
)
*138 (Text
uid 17689,0
va (VaSet
font "Verdana,9,1"
)
xt "161600,164700,176100,165900"
st "interpolatorShiftRegister"
blo "161600,165700"
tm "CptNameMgr"
)
*139 (Text
uid 17690,0
va (VaSet
font "Verdana,9,1"
)
xt "161600,165600,164800,166800"
st "I_srx"
blo "161600,166600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 17691,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 17692,0
text (MLText
uid 17693,0
va (VaSet
font "Verdana,8,0"
)
xt "161000,167600,179400,168600"
st "signalBitNb = signalBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*140 (SaComponent
uid 17730,0
optionalChildren [
*141 (CptPort
uid 17694,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17695,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,153625,185000,154375"
)
tg (CPTG
uid 17696,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17697,0
va (VaSet
)
xt "186000,153400,191000,154600"
st "sample1"
blo "186000,154400"
)
)
thePort (LogicalPort
decl (Decl
n "sample1"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 1
suid 1,0
)
)
)
*142 (CptPort
uid 17698,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17699,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,155625,185000,156375"
)
tg (CPTG
uid 17700,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17701,0
va (VaSet
)
xt "186000,155400,191000,156600"
st "sample2"
blo "186000,156400"
)
)
thePort (LogicalPort
decl (Decl
n "sample2"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*143 (CptPort
uid 17702,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17703,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,157625,185000,158375"
)
tg (CPTG
uid 17704,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17705,0
va (VaSet
)
xt "186000,157400,191000,158600"
st "sample3"
blo "186000,158400"
)
)
thePort (LogicalPort
decl (Decl
n "sample3"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 3
suid 3,0
)
)
)
*144 (CptPort
uid 17706,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17707,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,159625,185000,160375"
)
tg (CPTG
uid 17708,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17709,0
va (VaSet
)
xt "186000,159400,191000,160600"
st "sample4"
blo "186000,160400"
)
)
thePort (LogicalPort
decl (Decl
n "sample4"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 4
suid 4,0
)
)
)
*145 (CptPort
uid 17710,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17711,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,153625,201750,154375"
)
tg (CPTG
uid 17712,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17713,0
va (VaSet
)
xt "198700,153400,200000,154600"
st "a"
ju 2
blo "200000,154400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "a"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 5
suid 5,0
)
)
)
*146 (CptPort
uid 17714,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17715,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,155625,201750,156375"
)
tg (CPTG
uid 17716,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17717,0
va (VaSet
)
xt "198700,155400,200000,156600"
st "b"
ju 2
blo "200000,156400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "b"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 6
suid 6,0
)
)
)
*147 (CptPort
uid 17718,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17719,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,159625,201750,160375"
)
tg (CPTG
uid 17720,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17721,0
va (VaSet
)
xt "198700,159400,200000,160600"
st "d"
ju 2
blo "200000,160400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "d"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 8
suid 7,0
)
)
)
*148 (CptPort
uid 17722,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17723,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,157625,201750,158375"
)
tg (CPTG
uid 17724,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17725,0
va (VaSet
)
xt "198700,157400,200000,158600"
st "c"
ju 2
blo "200000,158400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "c"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 7
suid 8,0
)
)
)
*149 (CptPort
uid 17726,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17727,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,161625,185000,162375"
)
tg (CPTG
uid 17728,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17729,0
va (VaSet
)
xt "186000,161400,195900,162600"
st "interpolateLinear"
blo "186000,162400"
)
)
thePort (LogicalPort
decl (Decl
n "interpolateLinear"
t "std_ulogic"
o 9
suid 9,0
)
)
)
]
shape (Rectangle
uid 17731,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "185000,150000,201000,166000"
)
oxt "33000,11000,49000,27000"
ttg (MlTextGroup
uid 17732,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*150 (Text
uid 17733,0
va (VaSet
font "Verdana,9,1"
)
xt "185600,165800,196000,167000"
st "SplineInterpolator"
blo "185600,166800"
tm "BdLibraryNameMgr"
)
*151 (Text
uid 17734,0
va (VaSet
font "Verdana,9,1"
)
xt "185600,166700,199500,167900"
st "interpolatorCoefficients"
blo "185600,167700"
tm "CptNameMgr"
)
*152 (Text
uid 17735,0
va (VaSet
font "Verdana,9,1"
)
xt "185600,167600,190600,168800"
st "I_coeffx"
blo "185600,168600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 17736,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 17737,0
text (MLText
uid 17738,0
va (VaSet
font "Verdana,8,0"
)
xt "185000,169800,203100,171800"
st "bitNb      = signalBitNb    ( positive )  
coeffBitNb = coeffBitNb     ( positive )  "
)
header ""
)
elements [
(GiElement
name "bitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "coeffBitNb"
type "positive"
value "coeffBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*153 (SaComponent
uid 17775,0
optionalChildren [
*154 (CptPort
uid 17739,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17740,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,167625,217000,168375"
)
tg (CPTG
uid 17741,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17742,0
va (VaSet
)
xt "218000,167400,221400,168600"
st "clock"
blo "218000,168400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*155 (CptPort
uid 17743,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17744,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,169625,217000,170375"
)
tg (CPTG
uid 17745,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17746,0
va (VaSet
)
xt "218000,169400,221300,170600"
st "reset"
blo "218000,170400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*156 (CptPort
uid 17747,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17748,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,161625,217000,162375"
)
tg (CPTG
uid 17749,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17750,0
va (VaSet
)
xt "218000,161400,227100,162600"
st "restartPolynom"
blo "218000,162400"
)
)
thePort (LogicalPort
decl (Decl
n "restartPolynom"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*157 (CptPort
uid 17751,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17752,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,159625,217000,160375"
)
tg (CPTG
uid 17753,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17754,0
va (VaSet
)
xt "218000,159400,219300,160600"
st "d"
blo "218000,160400"
)
)
thePort (LogicalPort
decl (Decl
n "d"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 4
suid 4,0
)
)
)
*158 (CptPort
uid 17755,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17756,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "233000,153625,233750,154375"
)
tg (CPTG
uid 17757,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17758,0
va (VaSet
)
xt "225800,153400,232000,154600"
st "sampleOut"
ju 2
blo "232000,154400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sampleOut"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 5
suid 5,0
)
)
)
*159 (CptPort
uid 17759,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17760,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,157625,217000,158375"
)
tg (CPTG
uid 17761,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17762,0
va (VaSet
)
xt "218000,157400,219300,158600"
st "c"
blo "218000,158400"
)
)
thePort (LogicalPort
decl (Decl
n "c"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 6
suid 6,0
)
)
)
*160 (CptPort
uid 17763,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17764,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,155625,217000,156375"
)
tg (CPTG
uid 17765,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17766,0
va (VaSet
)
xt "218000,155400,219300,156600"
st "b"
blo "218000,156400"
)
)
thePort (LogicalPort
decl (Decl
n "b"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 7
suid 7,0
)
)
)
*161 (CptPort
uid 17767,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17768,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,153625,217000,154375"
)
tg (CPTG
uid 17769,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17770,0
va (VaSet
)
xt "218000,153400,219300,154600"
st "a"
blo "218000,154400"
)
)
thePort (LogicalPort
decl (Decl
n "a"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 8
suid 8,0
)
)
)
*162 (CptPort
uid 17771,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17772,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,165625,217000,166375"
)
tg (CPTG
uid 17773,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17774,0
va (VaSet
)
xt "218000,165400,219900,166600"
st "en"
blo "218000,166400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 9
suid 9,0
)
)
)
]
shape (Rectangle
uid 17776,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "217000,150000,233000,173000"
)
oxt "37000,7000,53000,30000"
ttg (MlTextGroup
uid 17777,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*163 (Text
uid 17778,0
va (VaSet
font "Verdana,9,1"
)
xt "217600,172800,228000,174000"
st "SplineInterpolator"
blo "217600,173800"
tm "BdLibraryNameMgr"
)
*164 (Text
uid 17779,0
va (VaSet
font "Verdana,9,1"
)
xt "217600,173700,234300,174900"
st "interpolatorCalculatePolynom"
blo "217600,174700"
tm "CptNameMgr"
)
*165 (Text
uid 17780,0
va (VaSet
font "Verdana,9,1"
)
xt "217600,174600,222000,175800"
st "I_polyx"
blo "217600,175600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 17781,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 17782,0
text (MLText
uid 17783,0
va (VaSet
font "Verdana,8,0"
)
xt "217000,177000,241500,180000"
st "signalBitNb       = signalBitNb         ( positive )  
coeffBitNb        = coeffBitNb          ( positive )  
oversamplingBitNb = sampleCountBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "coeffBitNb"
type "positive"
value "coeffBitNb"
)
(GiElement
name "oversamplingBitNb"
type "positive"
value "sampleCountBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*166 (SaComponent
uid 17792,0
optionalChildren [
*167 (CptPort
uid 17784,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17785,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "257000,153625,257750,154375"
)
tg (CPTG
uid 17786,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17787,0
va (VaSet
)
xt "248200,153400,256000,154600"
st "unsignedOut"
ju 2
blo "256000,154400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "unsignedOut"
t "unsigned"
b "(bitNb-1 DOWNTO 0)"
o 1
suid 1,0
)
)
)
*168 (CptPort
uid 17788,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17789,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "240250,153625,241000,154375"
)
tg (CPTG
uid 17790,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17791,0
va (VaSet
)
xt "242000,153400,247100,154600"
st "signedIn"
blo "242000,154400"
)
)
thePort (LogicalPort
decl (Decl
n "signedIn"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
]
shape (Rectangle
uid 17793,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "241000,150000,257000,158000"
)
oxt "32000,10000,48000,18000"
ttg (MlTextGroup
uid 17794,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*169 (Text
uid 17795,0
va (VaSet
font "Verdana,9,1"
)
xt "241600,157800,252000,159000"
st "SplineInterpolator"
blo "241600,158800"
tm "BdLibraryNameMgr"
)
*170 (Text
uid 17796,0
va (VaSet
font "Verdana,9,1"
)
xt "241600,158700,251700,159900"
st "offsetToUnsigned"
blo "241600,159700"
tm "CptNameMgr"
)
*171 (Text
uid 17797,0
va (VaSet
font "Verdana,9,1"
)
xt "241600,159600,246000,160800"
st "I_offsx"
blo "241600,160600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 17798,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 17799,0
text (MLText
uid 17800,0
va (VaSet
font "Verdana,8,0"
)
xt "241000,161800,256600,162800"
st "bitNb = signalBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "bitNb"
type "positive"
value "signalBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*172 (SaComponent
uid 17809,0
optionalChildren [
*173 (CptPort
uid 17801,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17802,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "257000,116625,257750,117375"
)
tg (CPTG
uid 17803,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17804,0
va (VaSet
)
xt "248200,116400,256000,117600"
st "unsignedOut"
ju 2
blo "256000,117400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "unsignedOut"
t "unsigned"
b "(bitNb-1 DOWNTO 0)"
o 1
suid 1,0
)
)
)
*174 (CptPort
uid 17805,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17806,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "240250,116625,241000,117375"
)
tg (CPTG
uid 17807,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17808,0
va (VaSet
)
xt "242000,116400,247100,117600"
st "signedIn"
blo "242000,117400"
)
)
thePort (LogicalPort
decl (Decl
n "signedIn"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
]
shape (Rectangle
uid 17810,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "241000,113000,257000,121000"
)
oxt "32000,10000,48000,18000"
ttg (MlTextGroup
uid 17811,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*175 (Text
uid 17812,0
va (VaSet
font "Verdana,9,1"
)
xt "241600,120800,252000,122000"
st "SplineInterpolator"
blo "241600,121800"
tm "BdLibraryNameMgr"
)
*176 (Text
uid 17813,0
va (VaSet
font "Verdana,9,1"
)
xt "241600,121700,251700,122900"
st "offsetToUnsigned"
blo "241600,122700"
tm "CptNameMgr"
)
*177 (Text
uid 17814,0
va (VaSet
font "Verdana,9,1"
)
xt "241600,122600,246000,123800"
st "I_offsy"
blo "241600,123600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 17815,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 17816,0
text (MLText
uid 17817,0
va (VaSet
font "Verdana,8,0"
)
xt "241000,124800,256600,125800"
st "bitNb = signalBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "bitNb"
type "positive"
value "signalBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*178 (SaComponent
uid 17854,0
optionalChildren [
*179 (CptPort
uid 17818,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17819,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,130625,217000,131375"
)
tg (CPTG
uid 17820,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17821,0
va (VaSet
)
xt "218000,130400,221400,131600"
st "clock"
blo "218000,131400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*180 (CptPort
uid 17822,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17823,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,132625,217000,133375"
)
tg (CPTG
uid 17824,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17825,0
va (VaSet
)
xt "218000,132400,221300,133600"
st "reset"
blo "218000,133400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*181 (CptPort
uid 17826,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17827,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,124625,217000,125375"
)
tg (CPTG
uid 17828,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17829,0
va (VaSet
)
xt "218000,124400,227100,125600"
st "restartPolynom"
blo "218000,125400"
)
)
thePort (LogicalPort
decl (Decl
n "restartPolynom"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*182 (CptPort
uid 17830,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17831,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,122625,217000,123375"
)
tg (CPTG
uid 17832,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17833,0
va (VaSet
)
xt "218000,122400,219300,123600"
st "d"
blo "218000,123400"
)
)
thePort (LogicalPort
decl (Decl
n "d"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 4
suid 4,0
)
)
)
*183 (CptPort
uid 17834,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17835,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "233000,116625,233750,117375"
)
tg (CPTG
uid 17836,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17837,0
va (VaSet
)
xt "225800,116400,232000,117600"
st "sampleOut"
ju 2
blo "232000,117400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sampleOut"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 5
suid 5,0
)
)
)
*184 (CptPort
uid 17838,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17839,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,120625,217000,121375"
)
tg (CPTG
uid 17840,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17841,0
va (VaSet
)
xt "218000,120400,219300,121600"
st "c"
blo "218000,121400"
)
)
thePort (LogicalPort
decl (Decl
n "c"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 6
suid 6,0
)
)
)
*185 (CptPort
uid 17842,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17843,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,118625,217000,119375"
)
tg (CPTG
uid 17844,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17845,0
va (VaSet
)
xt "218000,118400,219300,119600"
st "b"
blo "218000,119400"
)
)
thePort (LogicalPort
decl (Decl
n "b"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 7
suid 7,0
)
)
)
*186 (CptPort
uid 17846,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17847,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,116625,217000,117375"
)
tg (CPTG
uid 17848,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17849,0
va (VaSet
)
xt "218000,116400,219300,117600"
st "a"
blo "218000,117400"
)
)
thePort (LogicalPort
decl (Decl
n "a"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 8
suid 8,0
)
)
)
*187 (CptPort
uid 17850,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17851,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,128625,217000,129375"
)
tg (CPTG
uid 17852,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17853,0
va (VaSet
)
xt "218000,128400,219900,129600"
st "en"
blo "218000,129400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 9
suid 9,0
)
)
)
]
shape (Rectangle
uid 17855,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "217000,113000,233000,136000"
)
oxt "37000,7000,53000,30000"
ttg (MlTextGroup
uid 17856,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*188 (Text
uid 17857,0
va (VaSet
font "Verdana,9,1"
)
xt "217600,135800,228000,137000"
st "SplineInterpolator"
blo "217600,136800"
tm "BdLibraryNameMgr"
)
*189 (Text
uid 17858,0
va (VaSet
font "Verdana,9,1"
)
xt "217600,136700,234300,137900"
st "interpolatorCalculatePolynom"
blo "217600,137700"
tm "CptNameMgr"
)
*190 (Text
uid 17859,0
va (VaSet
font "Verdana,9,1"
)
xt "217600,137600,222000,138800"
st "I_polyy"
blo "217600,138600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 17860,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 17861,0
text (MLText
uid 17862,0
va (VaSet
font "Verdana,8,0"
)
xt "217000,140000,241500,143000"
st "signalBitNb       = signalBitNb         ( positive )  
coeffBitNb        = coeffBitNb          ( positive )  
oversamplingBitNb = sampleCountBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "coeffBitNb"
type "positive"
value "coeffBitNb"
)
(GiElement
name "oversamplingBitNb"
type "positive"
value "sampleCountBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*191 (SaComponent
uid 17899,0
optionalChildren [
*192 (CptPort
uid 17863,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17864,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,116625,185000,117375"
)
tg (CPTG
uid 17865,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17866,0
va (VaSet
)
xt "186000,116400,191000,117600"
st "sample1"
blo "186000,117400"
)
)
thePort (LogicalPort
decl (Decl
n "sample1"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 1
suid 1,0
)
)
)
*193 (CptPort
uid 17867,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17868,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,118625,185000,119375"
)
tg (CPTG
uid 17869,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17870,0
va (VaSet
)
xt "186000,118400,191000,119600"
st "sample2"
blo "186000,119400"
)
)
thePort (LogicalPort
decl (Decl
n "sample2"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*194 (CptPort
uid 17871,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17872,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,120625,185000,121375"
)
tg (CPTG
uid 17873,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17874,0
va (VaSet
)
xt "186000,120400,191000,121600"
st "sample3"
blo "186000,121400"
)
)
thePort (LogicalPort
decl (Decl
n "sample3"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 3
suid 3,0
)
)
)
*195 (CptPort
uid 17875,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17876,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,122625,185000,123375"
)
tg (CPTG
uid 17877,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17878,0
va (VaSet
)
xt "186000,122400,191000,123600"
st "sample4"
blo "186000,123400"
)
)
thePort (LogicalPort
decl (Decl
n "sample4"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 4
suid 4,0
)
)
)
*196 (CptPort
uid 17879,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17880,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,116625,201750,117375"
)
tg (CPTG
uid 17881,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17882,0
va (VaSet
)
xt "198700,116400,200000,117600"
st "a"
ju 2
blo "200000,117400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "a"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 5
suid 5,0
)
)
)
*197 (CptPort
uid 17883,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17884,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,118625,201750,119375"
)
tg (CPTG
uid 17885,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17886,0
va (VaSet
)
xt "198700,118400,200000,119600"
st "b"
ju 2
blo "200000,119400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "b"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 6
suid 6,0
)
)
)
*198 (CptPort
uid 17887,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17888,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,122625,201750,123375"
)
tg (CPTG
uid 17889,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17890,0
va (VaSet
)
xt "198700,122400,200000,123600"
st "d"
ju 2
blo "200000,123400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "d"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 8
suid 7,0
)
)
)
*199 (CptPort
uid 17891,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17892,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,120625,201750,121375"
)
tg (CPTG
uid 17893,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17894,0
va (VaSet
)
xt "198700,120400,200000,121600"
st "c"
ju 2
blo "200000,121400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "c"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 7
suid 8,0
)
)
)
*200 (CptPort
uid 17895,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17896,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,124625,185000,125375"
)
tg (CPTG
uid 17897,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17898,0
va (VaSet
)
xt "186000,124400,195900,125600"
st "interpolateLinear"
blo "186000,125400"
)
)
thePort (LogicalPort
decl (Decl
n "interpolateLinear"
t "std_ulogic"
o 9
suid 9,0
)
)
)
]
shape (Rectangle
uid 17900,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "185000,113000,201000,129000"
)
oxt "33000,11000,49000,27000"
ttg (MlTextGroup
uid 17901,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*201 (Text
uid 17902,0
va (VaSet
font "Verdana,9,1"
)
xt "185600,128800,196000,130000"
st "SplineInterpolator"
blo "185600,129800"
tm "BdLibraryNameMgr"
)
*202 (Text
uid 17903,0
va (VaSet
font "Verdana,9,1"
)
xt "185600,129700,199500,130900"
st "interpolatorCoefficients"
blo "185600,130700"
tm "CptNameMgr"
)
*203 (Text
uid 17904,0
va (VaSet
font "Verdana,9,1"
)
xt "185600,130600,190600,131800"
st "I_coeffy"
blo "185600,131600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 17905,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 17906,0
text (MLText
uid 17907,0
va (VaSet
font "Verdana,8,0"
)
xt "185000,132800,203100,134800"
st "bitNb      = signalBitNb    ( positive )  
coeffBitNb = coeffBitNb     ( positive )  "
)
header ""
)
elements [
(GiElement
name "bitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "coeffBitNb"
type "positive"
value "coeffBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*204 (SaComponent
uid 18037,0
optionalChildren [
*205 (CptPort
uid 18005,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18006,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,122625,161000,123375"
)
tg (CPTG
uid 18007,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18008,0
va (VaSet
)
xt "162000,122400,165400,123600"
st "clock"
blo "162000,123400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*206 (CptPort
uid 18009,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18010,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,124625,161000,125375"
)
tg (CPTG
uid 18011,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18012,0
va (VaSet
)
xt "162000,124400,165300,125600"
st "reset"
blo "162000,125400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*207 (CptPort
uid 18013,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18014,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,118625,161000,119375"
)
tg (CPTG
uid 18015,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18016,0
va (VaSet
)
xt "162000,118400,169900,119600"
st "shiftSamples"
blo "162000,119400"
)
)
thePort (LogicalPort
decl (Decl
n "shiftSamples"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*208 (CptPort
uid 18017,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18018,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,116625,161000,117375"
)
tg (CPTG
uid 18019,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 18020,0
va (VaSet
)
xt "162000,116400,167400,117600"
st "sampleIn"
blo "162000,117400"
)
)
thePort (LogicalPort
decl (Decl
n "sampleIn"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 4
suid 4,0
)
)
)
*209 (CptPort
uid 18021,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18022,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,116625,177750,117375"
)
tg (CPTG
uid 18023,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18024,0
va (VaSet
)
xt "171000,116400,176000,117600"
st "sample1"
ju 2
blo "176000,117400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample1"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 5
suid 5,0
)
)
)
*210 (CptPort
uid 18025,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18026,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,118625,177750,119375"
)
tg (CPTG
uid 18027,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18028,0
va (VaSet
)
xt "171000,118400,176000,119600"
st "sample2"
ju 2
blo "176000,119400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample2"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 6
suid 6,0
)
)
)
*211 (CptPort
uid 18029,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18030,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,120625,177750,121375"
)
tg (CPTG
uid 18031,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18032,0
va (VaSet
)
xt "171000,120400,176000,121600"
st "sample3"
ju 2
blo "176000,121400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample3"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 7
suid 7,0
)
)
)
*212 (CptPort
uid 18033,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18034,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,122625,177750,123375"
)
tg (CPTG
uid 18035,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18036,0
va (VaSet
)
xt "171000,122400,176000,123600"
st "sample4"
ju 2
blo "176000,123400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample4"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 8
suid 8,0
)
)
)
]
shape (Rectangle
uid 18038,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "161000,113000,177000,127000"
)
oxt "35000,9000,51000,23000"
ttg (MlTextGroup
uid 18039,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*213 (Text
uid 18040,0
va (VaSet
font "Verdana,9,1"
)
xt "161600,126800,172000,128000"
st "SplineInterpolator"
blo "161600,127800"
tm "BdLibraryNameMgr"
)
*214 (Text
uid 18041,0
va (VaSet
font "Verdana,9,1"
)
xt "161600,127700,176100,128900"
st "interpolatorShiftRegister"
blo "161600,128700"
tm "CptNameMgr"
)
*215 (Text
uid 18042,0
va (VaSet
font "Verdana,9,1"
)
xt "161600,128600,164800,129800"
st "I_sry"
blo "161600,129600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 18043,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 18044,0
text (MLText
uid 18045,0
va (VaSet
font "Verdana,8,0"
)
xt "161000,130600,179400,131600"
st "signalBitNb = signalBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*216 (Wire
uid 115,0
shape (OrthoPolyLine
uid 116,0
va (VaSet
vasetType 3
)
xt "281750,154000,289000,154000"
pts [
"281750,154000"
"289000,154000"
]
)
start &106
end &13
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 119,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 120,0
va (VaSet
font "Verdana,12,0"
)
xt "286000,152600,289700,154000"
st "outX"
blo "286000,153800"
tm "WireNameMgr"
)
)
on &14
)
*217 (Wire
uid 129,0
shape (OrthoPolyLine
uid 130,0
va (VaSet
vasetType 3
)
xt "281750,117000,289000,117000"
pts [
"281750,117000"
"289000,117000"
]
)
start &98
end &15
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 133,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 134,0
va (VaSet
font "Verdana,12,0"
)
xt "286000,115600,289600,117000"
st "outY"
blo "286000,116800"
tm "WireNameMgr"
)
)
on &16
)
*218 (Wire
uid 354,0
optionalChildren [
*219 (BdJunction
uid 9152,0
ps "OnConnectorStrategy"
shape (Circle
uid 9153,0
va (VaSet
vasetType 1
)
xt "152600,155600,153400,156400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 355,0
va (VaSet
vasetType 3
)
xt "153000,156000,181000,176000"
pts [
"181000,176000"
"181000,169000"
"153000,169000"
"153000,156000"
"160250,156000"
]
)
start *220 (BdJunction
uid 564,0
ps "OnConnectorStrategy"
shape (Circle
uid 565,0
va (VaSet
vasetType 1
)
xt "180600,175600,181400,176400"
radius 400
)
)
end &131
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 356,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 357,0
va (VaSet
font "Verdana,12,0"
)
xt "152000,154600,161600,156000"
st "newPolynom"
blo "152000,155800"
tm "WireNameMgr"
)
)
on &18
)
*221 (Wire
uid 360,0
optionalChildren [
&220
*222 (BdJunction
uid 9244,0
ps "OnConnectorStrategy"
shape (Circle
uid 9245,0
va (VaSet
vasetType 1
)
xt "204600,161600,205400,162400"
radius 400
)
)
*223 (BdJunction
uid 16692,0
ps "OnConnectorStrategy"
shape (Circle
uid 16693,0
va (VaSet
vasetType 1
)
xt "204600,175600,205400,176400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 361,0
va (VaSet
vasetType 3
)
xt "177750,162000,216250,176000"
pts [
"177750,176000"
"205000,176000"
"205000,162000"
"216250,162000"
]
)
start &121
end &156
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 362,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 363,0
va (VaSet
font "Verdana,12,0"
)
xt "207000,160600,216600,162000"
st "newPolynom"
blo "207000,161800"
tm "WireNameMgr"
)
)
on &18
)
*224 (Wire
uid 364,0
shape (OrthoPolyLine
uid 365,0
va (VaSet
vasetType 3
)
xt "157000,182000,160250,182000"
pts [
"157000,182000"
"160250,182000"
]
)
end &123
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 368,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 369,0
va (VaSet
font "Verdana,12,0"
)
xt "156000,180600,160100,182000"
st "reset"
blo "156000,181800"
tm "WireNameMgr"
)
)
on &17
)
*225 (Wire
uid 370,0
shape (OrthoPolyLine
uid 371,0
va (VaSet
vasetType 3
)
xt "157000,180000,160250,180000"
pts [
"157000,180000"
"160250,180000"
]
)
end &122
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 374,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 375,0
va (VaSet
font "Verdana,12,0"
)
xt "156000,178600,159800,180000"
st "clock"
blo "156000,179800"
tm "WireNameMgr"
)
)
on &12
)
*226 (Wire
uid 376,0
shape (OrthoPolyLine
uid 377,0
va (VaSet
vasetType 3
)
xt "157000,162000,160250,162000"
pts [
"157000,162000"
"160250,162000"
]
)
end &130
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 380,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 381,0
va (VaSet
font "Verdana,12,0"
)
xt "156000,160600,160100,162000"
st "reset"
blo "156000,161800"
tm "WireNameMgr"
)
)
on &17
)
*227 (Wire
uid 382,0
shape (OrthoPolyLine
uid 383,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "147000,154000,160250,154000"
pts [
"147000,154000"
"160250,154000"
]
)
start &44
end &132
sat 2
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 384,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 385,0
va (VaSet
font "Verdana,12,0"
)
xt "149000,152600,155800,154000"
st "samplesX"
blo "149000,153800"
tm "WireNameMgr"
)
)
on &21
)
*228 (Wire
uid 386,0
shape (OrthoPolyLine
uid 387,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,156000,184250,156000"
pts [
"177750,156000"
"184250,156000"
]
)
start &134
end &142
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 388,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 389,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,154600,184900,156000"
st "sampleX2"
blo "178000,155800"
tm "WireNameMgr"
)
)
on &23
)
*229 (Wire
uid 390,0
shape (OrthoPolyLine
uid 391,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,154000,184250,154000"
pts [
"177750,154000"
"184250,154000"
]
)
start &133
end &141
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 392,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 393,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,152600,184900,154000"
st "sampleX1"
blo "178000,153800"
tm "WireNameMgr"
)
)
on &22
)
*230 (Wire
uid 394,0
shape (OrthoPolyLine
uid 395,0
va (VaSet
vasetType 3
)
xt "157000,160000,160250,160000"
pts [
"157000,160000"
"160250,160000"
]
)
end &129
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 398,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 399,0
va (VaSet
font "Verdana,12,0"
)
xt "156000,158600,159800,160000"
st "clock"
blo "156000,159800"
tm "WireNameMgr"
)
)
on &12
)
*231 (Wire
uid 400,0
shape (OrthoPolyLine
uid 401,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "201750,154000,216250,154000"
pts [
"201750,154000"
"216250,154000"
]
)
start &145
end &161
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 402,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 403,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,152600,206150,154000"
st "aX"
blo "203750,153800"
tm "WireNameMgr"
)
)
on &26
)
*232 (Wire
uid 404,0
shape (OrthoPolyLine
uid 405,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,160000,184250,160000"
pts [
"177750,160000"
"184250,160000"
]
)
start &136
end &144
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 406,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 407,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,158600,184900,160000"
st "sampleX4"
blo "178000,159800"
tm "WireNameMgr"
)
)
on &25
)
*233 (Wire
uid 408,0
shape (OrthoPolyLine
uid 409,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,158000,184250,158000"
pts [
"177750,158000"
"184250,158000"
]
)
start &135
end &143
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 410,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 411,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,156600,184900,158000"
st "sampleX3"
blo "178000,157800"
tm "WireNameMgr"
)
)
on &24
)
*234 (Wire
uid 412,0
shape (OrthoPolyLine
uid 413,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "201750,160000,216250,160000"
pts [
"201750,160000"
"216250,160000"
]
)
start &147
end &157
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 414,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 415,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,158600,206150,160000"
st "dX"
blo "203750,159800"
tm "WireNameMgr"
)
)
on &29
)
*235 (Wire
uid 416,0
shape (OrthoPolyLine
uid 417,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "201750,158000,216250,158000"
pts [
"201750,158000"
"216250,158000"
]
)
start &148
end &159
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 418,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 419,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,156600,205950,158000"
st "cX"
blo "203750,157800"
tm "WireNameMgr"
)
)
on &28
)
*236 (Wire
uid 420,0
shape (OrthoPolyLine
uid 421,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "201750,156000,216250,156000"
pts [
"201750,156000"
"216250,156000"
]
)
start &146
end &160
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 422,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 423,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,154600,206150,156000"
st "bX"
blo "203750,155800"
tm "WireNameMgr"
)
)
on &27
)
*237 (Wire
uid 424,0
shape (OrthoPolyLine
uid 425,0
va (VaSet
vasetType 3
)
xt "213000,170000,216250,170000"
pts [
"213000,170000"
"216250,170000"
]
)
end &155
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 428,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 429,0
va (VaSet
font "Verdana,12,0"
)
xt "212000,168600,216100,170000"
st "reset"
blo "212000,169800"
tm "WireNameMgr"
)
)
on &17
)
*238 (Wire
uid 430,0
shape (OrthoPolyLine
uid 431,0
va (VaSet
vasetType 3
)
xt "213000,168000,216250,168000"
pts [
"213000,168000"
"216250,168000"
]
)
end &154
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 434,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 435,0
va (VaSet
font "Verdana,12,0"
)
xt "212000,166600,215800,168000"
st "clock"
blo "212000,167800"
tm "WireNameMgr"
)
)
on &12
)
*239 (Wire
uid 497,0
shape (OrthoPolyLine
uid 498,0
va (VaSet
vasetType 3
)
xt "261000,160000,264250,160000"
pts [
"261000,160000"
"264250,160000"
]
)
end &107
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 503,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 504,0
va (VaSet
font "Verdana,12,0"
)
xt "260000,158600,264100,160000"
st "reset"
blo "260000,159800"
tm "WireNameMgr"
)
)
on &17
)
*240 (Wire
uid 505,0
shape (OrthoPolyLine
uid 506,0
va (VaSet
vasetType 3
)
xt "261000,158000,264250,158000"
pts [
"261000,158000"
"264250,158000"
]
)
end &104
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 511,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 512,0
va (VaSet
font "Verdana,12,0"
)
xt "260000,156600,263800,158000"
st "clock"
blo "260000,157800"
tm "WireNameMgr"
)
)
on &12
)
*241 (Wire
uid 532,0
shape (OrthoPolyLine
uid 533,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "233750,154000,240250,154000"
pts [
"233750,154000"
"240250,154000"
]
)
start &158
end &168
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 534,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 535,0
va (VaSet
font "Verdana,12,0"
)
xt "234000,152600,240100,154000"
st "sampleX"
blo "234000,153800"
tm "WireNameMgr"
)
)
on &19
)
*242 (Wire
uid 538,0
shape (OrthoPolyLine
uid 539,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "257750,154000,264250,154000"
pts [
"257750,154000"
"264250,154000"
]
)
start &167
end &105
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 540,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 541,0
va (VaSet
font "Verdana,12,0"
)
xt "258000,152600,265400,154000"
st "unsignedX"
blo "258000,153800"
tm "WireNameMgr"
)
)
on &20
)
*243 (Wire
uid 767,0
shape (OrthoPolyLine
uid 768,0
va (VaSet
vasetType 3
)
xt "205000,125000,216250,162000"
pts [
"205000,162000"
"205000,125000"
"216250,125000"
]
)
start &222
end &181
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 771,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 772,0
va (VaSet
font "Verdana,12,0"
)
xt "205000,123600,214600,125000"
st "newPolynom"
blo "205000,124800"
tm "WireNameMgr"
)
)
on &18
)
*244 (Wire
uid 775,0
shape (OrthoPolyLine
uid 776,0
va (VaSet
vasetType 3
)
xt "153000,119000,160250,156000"
pts [
"153000,156000"
"153000,119000"
"160250,119000"
]
)
start &219
end &207
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 777,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 778,0
va (VaSet
font "Verdana,12,0"
)
xt "152000,117600,161600,119000"
st "newPolynom"
blo "152000,118800"
tm "WireNameMgr"
)
)
on &18
)
*245 (Wire
uid 779,0
shape (OrthoPolyLine
uid 780,0
va (VaSet
vasetType 3
)
xt "157000,125000,160250,125000"
pts [
"157000,125000"
"160250,125000"
]
)
end &206
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 783,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 784,0
va (VaSet
font "Verdana,12,0"
)
xt "156000,123600,160100,125000"
st "reset"
blo "156000,124800"
tm "WireNameMgr"
)
)
on &17
)
*246 (Wire
uid 785,0
shape (OrthoPolyLine
uid 786,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,117000,184250,117000"
pts [
"177750,117000"
"184250,117000"
]
)
start &209
end &192
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 787,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 788,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,115600,184800,117000"
st "sampleY1"
blo "178000,116800"
tm "WireNameMgr"
)
)
on &31
)
*247 (Wire
uid 789,0
shape (OrthoPolyLine
uid 790,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,119000,184250,119000"
pts [
"177750,119000"
"184250,119000"
]
)
start &210
end &193
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 791,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 792,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,117600,184800,119000"
st "sampleY2"
blo "178000,118800"
tm "WireNameMgr"
)
)
on &32
)
*248 (Wire
uid 793,0
shape (OrthoPolyLine
uid 794,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "147000,117000,160250,117000"
pts [
"147000,117000"
"160250,117000"
]
)
start &49
end &208
sat 2
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 797,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 798,0
va (VaSet
font "Verdana,12,0"
)
xt "148000,115600,154700,117000"
st "samplesY"
blo "148000,116800"
tm "WireNameMgr"
)
)
on &30
)
*249 (Wire
uid 799,0
shape (OrthoPolyLine
uid 800,0
va (VaSet
vasetType 3
)
xt "157000,123000,160250,123000"
pts [
"157000,123000"
"160250,123000"
]
)
end &205
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 803,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 804,0
va (VaSet
font "Verdana,12,0"
)
xt "156000,121600,159800,123000"
st "clock"
blo "156000,122800"
tm "WireNameMgr"
)
)
on &12
)
*250 (Wire
uid 805,0
shape (OrthoPolyLine
uid 806,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "201750,123000,216250,123000"
pts [
"201750,123000"
"216250,123000"
]
)
start &198
end &182
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 807,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 808,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,121600,206050,123000"
st "dY"
blo "203750,122800"
tm "WireNameMgr"
)
)
on &38
)
*251 (Wire
uid 809,0
shape (OrthoPolyLine
uid 810,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,121000,184250,121000"
pts [
"177750,121000"
"184250,121000"
]
)
start &211
end &194
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 811,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 812,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,119600,184800,121000"
st "sampleY3"
blo "178000,120800"
tm "WireNameMgr"
)
)
on &33
)
*252 (Wire
uid 813,0
shape (OrthoPolyLine
uid 814,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,123000,184250,123000"
pts [
"177750,123000"
"184250,123000"
]
)
start &212
end &195
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 815,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 816,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,121600,184800,123000"
st "sampleY4"
blo "178000,122800"
tm "WireNameMgr"
)
)
on &34
)
*253 (Wire
uid 817,0
shape (OrthoPolyLine
uid 818,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "201750,117000,216250,117000"
pts [
"201750,117000"
"216250,117000"
]
)
start &196
end &186
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 819,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 820,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,115600,206050,117000"
st "aY"
blo "203750,116800"
tm "WireNameMgr"
)
)
on &35
)
*254 (Wire
uid 821,0
shape (OrthoPolyLine
uid 822,0
va (VaSet
vasetType 3
)
xt "213000,133000,216250,133000"
pts [
"213000,133000"
"216250,133000"
]
)
end &180
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 825,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 826,0
va (VaSet
font "Verdana,12,0"
)
xt "212000,131600,216100,133000"
st "reset"
blo "212000,132800"
tm "WireNameMgr"
)
)
on &17
)
*255 (Wire
uid 827,0
shape (OrthoPolyLine
uid 828,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "201750,119000,216250,119000"
pts [
"201750,119000"
"216250,119000"
]
)
start &197
end &185
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 829,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 830,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,117600,206050,119000"
st "bY"
blo "203750,118800"
tm "WireNameMgr"
)
)
on &36
)
*256 (Wire
uid 831,0
shape (OrthoPolyLine
uid 832,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "201750,121000,216250,121000"
pts [
"201750,121000"
"216250,121000"
]
)
start &199
end &184
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 833,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 834,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,119600,205850,121000"
st "cY"
blo "203750,120800"
tm "WireNameMgr"
)
)
on &37
)
*257 (Wire
uid 835,0
shape (OrthoPolyLine
uid 836,0
va (VaSet
vasetType 3
)
xt "261000,123000,264250,123000"
pts [
"261000,123000"
"264250,123000"
]
)
end &99
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 839,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 840,0
va (VaSet
font "Verdana,12,0"
)
xt "260000,121600,264100,123000"
st "reset"
blo "260000,122800"
tm "WireNameMgr"
)
)
on &17
)
*258 (Wire
uid 841,0
shape (OrthoPolyLine
uid 842,0
va (VaSet
vasetType 3
)
xt "213000,131000,216250,131000"
pts [
"213000,131000"
"216250,131000"
]
)
end &179
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 845,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 846,0
va (VaSet
font "Verdana,12,0"
)
xt "212000,129600,215800,131000"
st "clock"
blo "212000,130800"
tm "WireNameMgr"
)
)
on &12
)
*259 (Wire
uid 847,0
shape (OrthoPolyLine
uid 848,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "233750,117000,240250,117000"
pts [
"233750,117000"
"240250,117000"
]
)
start &183
end &174
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 849,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 850,0
va (VaSet
font "Verdana,12,0"
)
xt "234000,115600,240000,117000"
st "sampleY"
blo "234000,116800"
tm "WireNameMgr"
)
)
on &39
)
*260 (Wire
uid 851,0
shape (OrthoPolyLine
uid 852,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "257750,117000,264250,117000"
pts [
"257750,117000"
"264250,117000"
]
)
start &173
end &97
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 853,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 854,0
va (VaSet
font "Verdana,12,0"
)
xt "258000,115600,265300,117000"
st "unsignedY"
blo "258000,116800"
tm "WireNameMgr"
)
)
on &40
)
*261 (Wire
uid 855,0
shape (OrthoPolyLine
uid 856,0
va (VaSet
vasetType 3
)
xt "261000,121000,264250,121000"
pts [
"261000,121000"
"264250,121000"
]
)
end &96
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 859,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 860,0
va (VaSet
font "Verdana,12,0"
)
xt "260000,119600,263800,121000"
st "clock"
blo "260000,120800"
tm "WireNameMgr"
)
)
on &12
)
*262 (Wire
uid 1995,0
shape (OrthoPolyLine
uid 1996,0
va (VaSet
vasetType 3
)
xt "153000,176000,160250,176000"
pts [
"153000,176000"
"160250,176000"
]
)
end &124
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2001,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2002,0
va (VaSet
font "Verdana,12,0"
)
xt "148000,174600,161900,176000"
st "interpolationEnable"
blo "148000,175800"
tm "WireNameMgr"
)
)
on &43
)
*263 (Wire
uid 3146,0
shape (OrthoPolyLine
uid 3147,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "123000,154000,131000,154000"
pts [
"123000,154000"
"131000,154000"
]
)
start &73
end &44
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3150,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3151,0
va (VaSet
font "Verdana,12,0"
)
xt "124000,152600,128600,154000"
st "memX"
blo "124000,153800"
tm "WireNameMgr"
)
)
on &48
)
*264 (Wire
uid 3432,0
shape (OrthoPolyLine
uid 3433,0
va (VaSet
vasetType 3
)
xt "209000,166000,216250,166000"
pts [
"209000,166000"
"216250,166000"
]
)
end &162
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3438,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3439,0
va (VaSet
font "Verdana,12,0"
)
xt "204000,164600,217900,166000"
st "interpolationEnable"
blo "204000,165800"
tm "WireNameMgr"
)
)
on &43
)
*265 (Wire
uid 3485,0
shape (OrthoPolyLine
uid 3486,0
va (VaSet
vasetType 3
)
xt "209000,129000,216250,129000"
pts [
"209000,129000"
"216250,129000"
]
)
end &187
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3491,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3492,0
va (VaSet
font "Verdana,12,0"
)
xt "204000,127600,217900,129000"
st "interpolationEnable"
blo "204000,128800"
tm "WireNameMgr"
)
)
on &43
)
*266 (Wire
uid 3907,0
shape (OrthoPolyLine
uid 3908,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "123000,117000,131000,117000"
pts [
"123000,117000"
"131000,117000"
]
)
start &77
end &49
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3911,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3912,0
va (VaSet
font "Verdana,12,0"
)
xt "125750,115600,130250,117000"
st "memY"
blo "125750,116800"
tm "WireNameMgr"
)
)
on &53
)
*267 (Wire
uid 4770,0
shape (OrthoPolyLine
uid 4771,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "91750,150000,98250,150000"
pts [
"91750,150000"
"98250,150000"
]
)
start &113
end &90
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4774,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4775,0
va (VaSet
font "Verdana,12,0"
)
xt "92000,148600,96700,150000"
st "phase"
blo "92000,149800"
tm "WireNameMgr"
)
)
on &58
)
*268 (Wire
uid 4782,0
shape (OrthoPolyLine
uid 4783,0
va (VaSet
vasetType 3
)
xt "71000,158000,74250,158000"
pts [
"71000,158000"
"74250,158000"
]
)
end &114
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4786,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4787,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,156600,75100,158000"
st "reset"
blo "71000,157800"
tm "WireNameMgr"
)
)
on &17
)
*269 (Wire
uid 4788,0
shape (OrthoPolyLine
uid 4789,0
va (VaSet
vasetType 3
)
xt "71000,156000,74250,156000"
pts [
"71000,156000"
"74250,156000"
]
)
end &112
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4792,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4793,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,154600,74800,156000"
st "clock"
blo "71000,155800"
tm "WireNameMgr"
)
)
on &12
)
*270 (Wire
uid 4794,0
shape (OrthoPolyLine
uid 4795,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "71000,144000,74250,150000"
pts [
"74250,150000"
"71000,150000"
"71000,144000"
]
)
start &115
end &54
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4798,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4799,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,148600,74600,150000"
st "step"
blo "71000,149800"
tm "WireNameMgr"
)
)
on &59
)
*271 (Wire
uid 4860,0
shape (OrthoPolyLine
uid 4861,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "115750,115000,131000,150000"
pts [
"115750,150000"
"119000,150000"
"119000,115000"
"131000,115000"
]
)
start &89
end &49
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4864,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4865,0
va (VaSet
font "Verdana,12,0"
)
xt "117750,148600,121150,150000"
st "sine"
blo "117750,149800"
tm "WireNameMgr"
)
)
on &60
)
*272 (Wire
uid 4866,0
shape (OrthoPolyLine
uid 4867,0
va (VaSet
vasetType 3
)
xt "67000,154000,74250,154000"
pts [
"67000,154000"
"74250,154000"
]
)
end &116
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4872,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4873,0
va (VaSet
font "Verdana,12,0"
)
xt "63000,152600,76900,154000"
st "interpolationEnable"
blo "63000,153800"
tm "WireNameMgr"
)
)
on &43
)
*273 (Wire
uid 5086,0
shape (OrthoPolyLine
uid 5087,0
va (VaSet
vasetType 3
)
xt "91000,109000,99000,109000"
pts [
"91000,109000"
"99000,109000"
]
)
start &61
end &62
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5090,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5091,0
va (VaSet
font "Verdana,12,0"
)
xt "91000,107600,97900,109000"
st "selSinCos"
blo "91000,108800"
tm "WireNameMgr"
)
)
on &68
)
*274 (Wire
uid 5253,0
shape (OrthoPolyLine
uid 5254,0
va (VaSet
vasetType 3
)
xt "115000,107000,123000,107000"
pts [
"115000,107000"
"123000,107000"
]
)
start &62
sat 2
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5259,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5260,0
va (VaSet
font "Verdana,12,0"
)
xt "117750,105600,131650,107000"
st "interpolationEnable"
blo "117750,106800"
tm "WireNameMgr"
)
)
on &43
)
*275 (Wire
uid 5263,0
shape (OrthoPolyLine
uid 5264,0
va (VaSet
vasetType 3
)
xt "75750,107000,99000,107000"
pts [
"75750,107000"
"99000,107000"
]
)
start &80
end &62
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5269,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5270,0
va (VaSet
font "Verdana,12,0"
)
xt "89000,105600,100200,107000"
st "interpolationEn"
blo "89000,106800"
tm "WireNameMgr"
)
)
on &66
)
*276 (Wire
uid 5938,0
shape (OrthoPolyLine
uid 5939,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "115750,152000,131000,152000"
pts [
"115750,152000"
"131000,152000"
]
)
start &91
end &44
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5942,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5943,0
va (VaSet
font "Verdana,12,0"
)
xt "117750,150600,122550,152000"
st "cosine"
blo "117750,151800"
tm "WireNameMgr"
)
)
on &67
)
*277 (Wire
uid 8248,0
optionalChildren [
*278 (BdJunction
uid 8258,0
ps "OnConnectorStrategy"
shape (Circle
uid 8259,0
va (VaSet
vasetType 1
)
xt "180600,124600,181400,125400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 8249,0
va (VaSet
vasetType 3
)
xt "115000,111000,184250,162000"
pts [
"184250,162000"
"181000,162000"
"181000,111000"
"115000,111000"
]
)
start &149
end &62
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 8252,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8253,0
va (VaSet
font "Verdana,12,0"
)
xt "117000,109600,129400,111000"
st "interpolateLinear"
blo "117000,110800"
tm "WireNameMgr"
)
)
on &69
)
*279 (Wire
uid 8254,0
shape (OrthoPolyLine
uid 8255,0
va (VaSet
vasetType 3
)
xt "181000,125000,184250,125000"
pts [
"184250,125000"
"181000,125000"
]
)
start &200
end &278
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 8256,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8257,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "171250,123600,183650,125000"
st "interpolateLinear"
blo "171250,124800"
tm "WireNameMgr"
)
)
on &69
)
*280 (Wire
uid 9246,0
shape (OrthoPolyLine
uid 9247,0
va (VaSet
vasetType 3
)
xt "139000,121000,139000,125000"
pts [
"139000,125000"
"139000,121000"
]
)
end &49
sat 16
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9252,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9253,0
va (VaSet
font "Verdana,12,0"
)
xt "139000,123600,145900,125000"
st "selSinCos"
blo "139000,124800"
tm "WireNameMgr"
)
)
on &68
)
*281 (Wire
uid 9254,0
shape (OrthoPolyLine
uid 9255,0
va (VaSet
vasetType 3
)
xt "139000,158000,139000,162000"
pts [
"139000,162000"
"139000,158000"
]
)
end &44
sat 16
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9260,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9261,0
va (VaSet
font "Verdana,12,0"
)
xt "139000,160600,145900,162000"
st "selSinCos"
blo "139000,161800"
tm "WireNameMgr"
)
)
on &68
)
*282 (Wire
uid 15564,0
shape (OrthoPolyLine
uid 15565,0
va (VaSet
vasetType 3
)
xt "51000,113000,58250,113000"
pts [
"51000,113000"
"58250,113000"
]
)
start &71
end &81
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 15568,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15569,0
va (VaSet
font "Verdana,12,0"
)
xt "53000,111600,56800,113000"
st "clock"
blo "53000,112800"
tm "WireNameMgr"
)
)
on &12
)
*283 (Wire
uid 15576,0
shape (OrthoPolyLine
uid 15577,0
va (VaSet
vasetType 3
)
xt "91000,111000,99000,111000"
pts [
"91000,111000"
"99000,111000"
]
)
start &72
end &62
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 15580,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15581,0
va (VaSet
font "Verdana,12,0"
)
xt "91000,109600,101300,111000"
st "interpolateLin"
blo "91000,110800"
tm "WireNameMgr"
)
)
on &70
)
*284 (Wire
uid 15600,0
shape (OrthoPolyLine
uid 15601,0
va (VaSet
vasetType 3
)
xt "51000,115000,58250,115000"
pts [
"51000,115000"
"58250,115000"
]
)
start &74
end &82
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 15604,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15605,0
va (VaSet
font "Verdana,12,0"
)
xt "53000,113600,57100,115000"
st "reset"
blo "53000,114800"
tm "WireNameMgr"
)
)
on &17
)
*285 (Wire
uid 15612,0
shape (OrthoPolyLine
uid 15613,0
va (VaSet
vasetType 3
)
xt "51000,107000,58250,107000"
pts [
"51000,107000"
"58250,107000"
]
)
start &75
end &84
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 15616,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15617,0
va (VaSet
font "Verdana,12,0"
)
xt "51000,105600,53900,107000"
st "run"
blo "51000,106800"
tm "WireNameMgr"
)
)
on &41
)
*286 (Wire
uid 15638,0
shape (OrthoPolyLine
uid 15639,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "51000,109000,58250,109000"
pts [
"51000,109000"
"58250,109000"
]
)
start &76
end &83
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 15642,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15643,0
va (VaSet
font "Verdana,12,0"
)
xt "49000,107600,59100,109000"
st "updatePeriod"
blo "49000,108800"
tm "WireNameMgr"
)
)
on &42
)
*287 (Wire
uid 16686,0
shape (OrthoPolyLine
uid 16687,0
va (VaSet
vasetType 3
)
xt "205000,176000,209000,176000"
pts [
"205000,176000"
"209000,176000"
"209000,176000"
]
)
start &223
end &78
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 16690,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16691,0
va (VaSet
font "Verdana,12,0"
)
xt "200000,174600,209600,176000"
st "newPolynom"
blo "200000,175800"
tm "WireNameMgr"
)
)
on &18
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 0
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *288 (PackageList
uid 42,0
stg "VerticalLayoutStrategy"
textVec [
*289 (Text
uid 43,0
va (VaSet
font "Verdana,8,1"
)
xt "17000,110400,23900,111400"
st "Package List"
blo "17000,111200"
)
*290 (MLText
uid 44,0
va (VaSet
)
xt "17000,111400,34500,115000"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 45,0
stg "VerticalLayoutStrategy"
textVec [
*291 (Text
uid 46,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,0,30200,1000"
st "Compiler Directives"
blo "20000,800"
)
*292 (Text
uid 47,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,1000,32200,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*293 (MLText
uid 48,0
va (VaSet
isHidden 1
)
xt "20000,2000,32100,4400"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*294 (Text
uid 49,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,4000,32800,5000"
st "Post-module directives:"
blo "20000,4800"
)
*295 (MLText
uid 50,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*296 (Text
uid 51,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,5000,32400,6000"
st "End-module directives:"
blo "20000,5800"
)
*297 (MLText
uid 52,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "-8,-8,1928,1048"
viewArea "13023,98875,296113,252685"
cachedDiagramExtent "13500,0,295700,188600"
pageSetupInfo (PageSetupInfo
ptrCmd "\\\\vmenpprint1.hevs.ch\\VS-FOLLOWME-PRN,winspool,"
fileName "ipp://ippsion.hevs.ch/ipp/PREA309_HPLJ3005DN"
toPrinter 1
colour 1
xMargin 46
yMargin 46
paperWidth 761
paperHeight 1077
unixPaperWidth 595
unixPaperHeight 842
windowsPaperWidth 761
windowsPaperHeight 1077
paperType "A4 (210 x 297 mm)"
unixPaperName "A4  (210mm x 297mm)"
windowsPaperName "A4 (210 x 297 mm)"
windowsPaperType 9
scale 50
useAdjustTo 0
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
)
hasePageBreakOrigin 1
pageBreakOrigin "0,99000"
lastUid 18336,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "65535,0,0"
)
xt "200,200,3200,1400"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "Verdana,8,0"
)
xt "450,2150,1450,3150"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Verdana,10,1"
)
xt "1000,1000,4400,2200"
st "Panel0"
blo "1000,2000"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "40000,56832,65535"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*298 (Text
va (VaSet
)
xt "1700,3200,6300,4400"
st "<library>"
blo "1700,4200"
tm "BdLibraryNameMgr"
)
*299 (Text
va (VaSet
)
xt "1700,4400,5800,5600"
st "<block>"
blo "1700,5400"
tm "BlkNameMgr"
)
*300 (Text
va (VaSet
)
xt "1700,5600,2900,6800"
st "I0"
blo "1700,6600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "1700,13200,1700,13200"
)
header ""
)
elements [
]
)
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*301 (Text
va (VaSet
)
xt "1000,3500,3300,4500"
st "Library"
blo "1000,4300"
)
*302 (Text
va (VaSet
)
xt "1000,4500,7000,5500"
st "MWComponent"
blo "1000,5300"
)
*303 (Text
va (VaSet
)
xt "1000,5500,1600,6500"
st "I0"
blo "1000,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6000,1500,-6000,1500"
)
header ""
)
elements [
]
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*304 (Text
va (VaSet
)
xt "1250,3500,3550,4500"
st "Library"
blo "1250,4300"
tm "BdLibraryNameMgr"
)
*305 (Text
va (VaSet
)
xt "1250,4500,6750,5500"
st "SaComponent"
blo "1250,5300"
tm "CptNameMgr"
)
*306 (Text
va (VaSet
)
xt "1250,5500,1850,6500"
st "I0"
blo "1250,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-5750,1500,-5750,1500"
)
header ""
)
elements [
]
)
archFileType "UNKNOWN"
)
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