1794 lines
22 KiB
Plaintext
1794 lines
22 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "27.1"
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appVersion "2019.2 (Build 5)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 41,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 88,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
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*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*12 (InitColHdr
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tm "InitColHdrMgr"
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)
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*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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*14 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 2
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suid 35,0
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)
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)
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uid 684,0
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)
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*15 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "reset"
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t "std_ulogic"
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o 1
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suid 36,0
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)
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)
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uid 686,0
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)
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*16 (LogPort
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port (LogicalPort
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decl (Decl
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n "triggerOut"
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t "std_ulogic"
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o 9
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suid 37,0
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)
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)
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uid 688,0
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)
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*17 (LogPort
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port (LogicalPort
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decl (Decl
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n "xLowapss"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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o 4
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suid 38,0
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)
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)
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uid 690,0
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)
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*18 (LogPort
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port (LogicalPort
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decl (Decl
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n "xSerial"
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t "std_ulogic"
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o 6
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suid 39,0
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)
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)
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uid 692,0
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)
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*19 (LogPort
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port (LogicalPort
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decl (Decl
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n "yLowpass"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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o 7
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suid 40,0
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)
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)
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uid 694,0
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)
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*20 (LogPort
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port (LogicalPort
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decl (Decl
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|
n "ySerial"
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t "std_ulogic"
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o 3
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suid 41,0
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)
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)
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uid 696,0
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)
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]
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)
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pdm (PhysicalDM
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displayShortBounds 1
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editShortBounds 1
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uid 101,0
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optionalChildren [
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*21 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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emptyMRCItem *22 (MRCItem
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litem &1
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pos 7
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dimension 20
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)
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uid 103,0
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optionalChildren [
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*23 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 104,0
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)
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*24 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 105,0
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)
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*25 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 106,0
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)
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*26 (MRCItem
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litem &14
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pos 0
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dimension 20
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uid 685,0
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)
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*27 (MRCItem
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litem &15
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pos 1
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dimension 20
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uid 687,0
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)
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*28 (MRCItem
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litem &16
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pos 2
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dimension 20
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uid 689,0
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)
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*29 (MRCItem
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litem &17
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pos 3
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dimension 20
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uid 691,0
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)
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*30 (MRCItem
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litem &18
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pos 4
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dimension 20
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uid 693,0
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)
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*31 (MRCItem
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litem &19
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pos 5
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dimension 20
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uid 695,0
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)
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*32 (MRCItem
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litem &20
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pos 6
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dimension 20
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uid 697,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 107,0
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optionalChildren [
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*33 (MRCItem
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litem &5
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pos 0
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dimension 20
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uid 108,0
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)
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*34 (MRCItem
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litem &7
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pos 1
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dimension 50
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uid 109,0
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)
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*35 (MRCItem
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litem &8
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pos 2
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dimension 100
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uid 110,0
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)
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*36 (MRCItem
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litem &9
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pos 3
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dimension 50
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uid 111,0
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)
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*37 (MRCItem
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litem &10
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pos 4
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dimension 100
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uid 112,0
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)
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*38 (MRCItem
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litem &11
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pos 5
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dimension 100
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uid 113,0
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)
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*39 (MRCItem
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litem &12
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pos 6
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dimension 50
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uid 114,0
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)
|
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*40 (MRCItem
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litem &13
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pos 7
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dimension 80
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|
uid 115,0
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)
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]
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)
|
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fixedCol 4
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fixedRow 2
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name "Ports"
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uid 102,0
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|
vaOverrides [
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]
|
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)
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]
|
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)
|
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uid 87,0
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)
|
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genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *41 (LEmptyRow
|
|
)
|
|
uid 117,0
|
|
optionalChildren [
|
|
*42 (RefLabelRowHdr
|
|
)
|
|
*43 (TitleRowHdr
|
|
)
|
|
*44 (FilterRowHdr
|
|
)
|
|
*45 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*46 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*47 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*48 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*49 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*50 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*51 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*52 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*53 (LogGeneric
|
|
generic (GiElement
|
|
name "signalBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
uid 166,0
|
|
)
|
|
*54 (LogGeneric
|
|
generic (GiElement
|
|
name "clockFrequency"
|
|
type "real"
|
|
value "60.0E6"
|
|
)
|
|
uid 624,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 129,0
|
|
optionalChildren [
|
|
*55 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *56 (MRCItem
|
|
litem &41
|
|
pos 2
|
|
dimension 20
|
|
)
|
|
uid 131,0
|
|
optionalChildren [
|
|
*57 (MRCItem
|
|
litem &42
|
|
pos 0
|
|
dimension 20
|
|
uid 132,0
|
|
)
|
|
*58 (MRCItem
|
|
litem &43
|
|
pos 1
|
|
dimension 23
|
|
uid 133,0
|
|
)
|
|
*59 (MRCItem
|
|
litem &44
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 134,0
|
|
)
|
|
*60 (MRCItem
|
|
litem &53
|
|
pos 0
|
|
dimension 20
|
|
uid 167,0
|
|
)
|
|
*61 (MRCItem
|
|
litem &54
|
|
pos 1
|
|
dimension 20
|
|
uid 625,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 135,0
|
|
optionalChildren [
|
|
*62 (MRCItem
|
|
litem &45
|
|
pos 0
|
|
dimension 20
|
|
uid 136,0
|
|
)
|
|
*63 (MRCItem
|
|
litem &47
|
|
pos 1
|
|
dimension 50
|
|
uid 137,0
|
|
)
|
|
*64 (MRCItem
|
|
litem &48
|
|
pos 2
|
|
dimension 100
|
|
uid 138,0
|
|
)
|
|
*65 (MRCItem
|
|
litem &49
|
|
pos 3
|
|
dimension 100
|
|
uid 139,0
|
|
)
|
|
*66 (MRCItem
|
|
litem &50
|
|
pos 4
|
|
dimension 50
|
|
uid 140,0
|
|
)
|
|
*67 (MRCItem
|
|
litem &51
|
|
pos 5
|
|
dimension 50
|
|
uid 141,0
|
|
)
|
|
*68 (MRCItem
|
|
litem &52
|
|
pos 6
|
|
dimension 80
|
|
uid 142,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 130,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 116,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajous@generator_tester\\interface.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajous@generator_tester\\interface.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajous@generator_tester"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajousGenerator_tester"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "ven."
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "vendredi"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "lissajousGenerator_tester"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "28.04.2023"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "14:48:11"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE7860"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "Lissajous_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Concatenation"
|
|
value "$HDS_PROJECT_DIR/../Lissajous_test/concat"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/Lissajous_test"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "04"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "lissajousGenerator_tester"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "avr."
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "avril"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajous@generator_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajousGenerator_tester\\interface"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "C:\\eda\\MentorGraphics\\ModelSim\\win64"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "14:48:11"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "lissajousGenerator_tester"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2023"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "23"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 86,0
|
|
optionalChildren [
|
|
*69 (SymbolBody
|
|
uid 8,0
|
|
optionalChildren [
|
|
*70 (CptPort
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|
uid 649,0
|
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ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 650,0
|
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va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "22625,5250,23375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 651,0
|
|
ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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|
f (Text
|
|
uid 652,0
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ro 270
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va (VaSet
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font "Verdana,12,0"
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)
|
|
xt "22300,7000,23700,10800"
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|
st "clock"
|
|
ju 2
|
|
blo "23500,7000"
|
|
tm "CptPortNameMgr"
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|
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)
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|
dt (MLText
|
|
uid 653,0
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va (VaSet
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|
font "Courier New,8,0"
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)
|
|
xt "44000,6000,62000,6800"
|
|
st "clock : OUT std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 35,0
|
|
)
|
|
)
|
|
)
|
|
*71 (CptPort
|
|
uid 654,0
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ps "OnEdgeStrategy"
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shape (Triangle
|
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uid 655,0
|
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va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
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|
)
|
|
xt "24625,5250,25375,6000"
|
|
)
|
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tg (CPTG
|
|
uid 656,0
|
|
ps "CptPortTextPlaceStrategy"
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|
stg "RightVerticalLayoutStrategy"
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f (Text
|
|
uid 657,0
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ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
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)
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xt "24300,7000,25700,11100"
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|
st "reset"
|
|
ju 2
|
|
blo "25500,7000"
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|
tm "CptPortNameMgr"
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|
)
|
|
)
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dt (MLText
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uid 658,0
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va (VaSet
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font "Courier New,8,0"
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)
|
|
xt "44000,6800,61000,7600"
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|
st "reset : OUT std_ulogic
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 36,0
|
|
)
|
|
)
|
|
)
|
|
*72 (CptPort
|
|
uid 659,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
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|
uid 660,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "46625,5250,47375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 661,0
|
|
ps "CptPortTextPlaceStrategy"
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|
stg "RightVerticalLayoutStrategy"
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|
f (Text
|
|
uid 662,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "46300,7000,47700,15100"
|
|
st "triggerOut"
|
|
ju 2
|
|
blo "47500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 663,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,2000,62000,2800"
|
|
st "triggerOut : IN std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "triggerOut"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 37,0
|
|
)
|
|
)
|
|
)
|
|
*73 (CptPort
|
|
uid 664,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 665,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "86625,5250,87375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 666,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 667,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "86300,7000,87700,14100"
|
|
st "xLowapss"
|
|
ju 2
|
|
blo "87500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 668,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,2800,73500,3600"
|
|
st "xLowapss : IN unsigned (signalBitNb-1 DOWNTO 0) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "xLowapss"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 38,0
|
|
)
|
|
)
|
|
)
|
|
*74 (CptPort
|
|
uid 669,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 670,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "48625,5250,49375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 671,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 672,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "48300,7000,49700,12000"
|
|
st "xSerial"
|
|
ju 2
|
|
blo "49500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 673,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,3600,62000,4400"
|
|
st "xSerial : IN std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "xSerial"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 39,0
|
|
)
|
|
)
|
|
)
|
|
*75 (CptPort
|
|
uid 674,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 675,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "88625,5250,89375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 676,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
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|
f (Text
|
|
uid 677,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "88300,7000,89700,14100"
|
|
st "yLowpass"
|
|
ju 2
|
|
blo "89500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 678,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "44000,4400,73500,5200"
|
|
st "yLowpass : IN unsigned (signalBitNb-1 DOWNTO 0) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "yLowpass"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 7
|
|
suid 40,0
|
|
)
|
|
)
|
|
)
|
|
*76 (CptPort
|
|
uid 679,0
|
|
ps "OnEdgeStrategy"
|
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shape (Triangle
|
|
uid 680,0
|
|
ro 180
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va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "50625,5250,51375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 681,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 682,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "50300,7000,51700,12000"
|
|
st "ySerial"
|
|
ju 2
|
|
blo "51500,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 683,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
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)
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|
xt "44000,5200,62000,6000"
|
|
st "ySerial : IN std_ulogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "ySerial"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 41,0
|
|
)
|
|
)
|
|
)
|
|
]
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|
shape (Rectangle
|
|
uid 9,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
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lineColor "0,32896,0"
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lineWidth 2
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)
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|
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|
|
)
|
|
oxt "15000,6000,93000,14000"
|
|
biTextGroup (BiTextGroup
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|
uid 10,0
|
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ps "CenterOffsetStrategy"
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|
stg "VerticalLayoutStrategy"
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first (Text
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|
uid 11,0
|
|
va (VaSet
|
|
font "Arial,8,1"
|
|
)
|
|
xt "49650,9000,55850,10000"
|
|
st "Lissajous_test"
|
|
blo "49650,9800"
|
|
)
|
|
second (Text
|
|
uid 12,0
|
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va (VaSet
|
|
font "Arial,8,1"
|
|
)
|
|
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|
|
st "lissajousGenerator_tester"
|
|
blo "49650,10800"
|
|
)
|
|
)
|
|
gi *77 (GenericInterface
|
|
uid 13,0
|
|
ps "CenterOffsetStrategy"
|
|
matrix (Matrix
|
|
uid 14,0
|
|
text (MLText
|
|
uid 15,0
|
|
va (VaSet
|
|
)
|
|
xt "28000,6000,46100,10800"
|
|
st "Generic Declarations
|
|
|
|
signalBitNb positive 16
|
|
clockFrequency real 60.0E6 "
|
|
)
|
|
header "Generic Declarations"
|
|
showHdrWhenContentsEmpty 1
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "signalBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
(GiElement
|
|
name "clockFrequency"
|
|
type "real"
|
|
value "60.0E6"
|
|
)
|
|
]
|
|
)
|
|
portInstanceVisAsIs 1
|
|
portInstanceVis (PortSigDisplay
|
|
sTC 0
|
|
sF 0
|
|
)
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
sF 0
|
|
)
|
|
)
|
|
*78 (Grouping
|
|
uid 16,0
|
|
optionalChildren [
|
|
*79 (CommentText
|
|
uid 18,0
|
|
shape (Rectangle
|
|
uid 19,0
|
|
sl 0
|
|
va (VaSet
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vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
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|
|
)
|
|
oxt "18000,70000,35000,71000"
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|
text (MLText
|
|
uid 20,0
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va (VaSet
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fg "0,0,32768"
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bg "0,0,32768"
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|
)
|
|
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|
|
st "
|
|
by %user on %dd %month %year
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 17000
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|
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|
position 1
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
)
|
|
*80 (CommentText
|
|
uid 21,0
|
|
shape (Rectangle
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uid 22,0
|
|
sl 0
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va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
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|
|
)
|
|
oxt "35000,66000,39000,67000"
|
|
text (MLText
|
|
uid 23,0
|
|
va (VaSet
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fg "0,0,32768"
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bg "0,0,32768"
|
|
)
|
|
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|
|
st "
|
|
Project:
|
|
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|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 4000
|
|
)
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|
position 1
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
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|
|
*81 (CommentText
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uid 24,0
|
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shape (Rectangle
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uid 25,0
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|
sl 0
|
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va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
)
|
|
xt "32000,48000,49000,49000"
|
|
)
|
|
oxt "18000,68000,35000,69000"
|
|
text (MLText
|
|
uid 26,0
|
|
va (VaSet
|
|
fg "0,0,32768"
|
|
bg "0,0,32768"
|
|
)
|
|
xt "32200,48500,32200,48500"
|
|
st "
|
|
<enter diagram title here>
|
|
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|
|
tm "CommentText"
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|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 17000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
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|
|
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|
|
uid 27,0
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|
shape (Rectangle
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|
uid 28,0
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|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65280,65280,46080"
|
|
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|
|
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|
|
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|
|
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|
|
text (MLText
|
|
uid 29,0
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va (VaSet
|
|
fg "0,0,32768"
|
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bg "0,0,32768"
|
|
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|
|
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|
|
st "
|
|
Title:
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|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
visibleHeight 1000
|
|
visibleWidth 4000
|
|
)
|
|
position 1
|
|
ignorePrefs 1
|
|
titleBlock 1
|
|
)
|
|
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