2792 lines
34 KiB
Plaintext
2792 lines
34 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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instances [
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(Instance
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name "I_tester"
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duLibraryName "pipelinedOperators_test"
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duName "parallelAdder_tester"
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elements [
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(GiElement
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name "adderBitNb"
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type "positive"
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value "adderBitNb"
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)
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(GiElement
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name "clockFrequency"
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type "real"
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value "clockFrequency"
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)
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mwi 0
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uid 2178,0
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)
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(Instance
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name "I_DUT"
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duLibraryName "pipelinedOperators"
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duName "parallelAdder"
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elements [
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(GiElement
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name "bitNb"
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type "positive"
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value "adderBitNb"
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)
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]
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mwi 0
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uid 2425,0
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]
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libraryRefs [
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"ieee"
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]
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)
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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model (BlockDiag
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VExpander (VariableExpander
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vvMap [
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(vvPair
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variable " "
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value " "
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)
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(vvPair
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variable "HDLDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hdl"
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)
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(vvPair
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variable "HDSDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds"
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)
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(vvPair
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variable "SideDataDesignDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\parallel@adder_tb\\struct.bd.info"
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)
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(vvPair
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variable "SideDataUserDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\parallel@adder_tb\\struct.bd.user"
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)
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(vvPair
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variable "SourceDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds"
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)
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(vvPair
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variable "appl"
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value "HDL Designer"
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)
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(vvPair
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variable "arch_name"
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value "struct"
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)
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(vvPair
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variable "asm_file"
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value "beamer.asm"
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)
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(vvPair
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variable "concat_file"
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value "concatenated"
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)
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(vvPair
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variable "config"
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value "%(unit)_%(view)_config"
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)
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(vvPair
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variable "d"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\parallel@adder_tb"
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)
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(vvPair
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variable "d_logical"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\parallelAdder_tb"
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)
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(vvPair
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variable "date"
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value "28.04.2023"
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(vvPair
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variable "day"
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value "ven."
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)
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(vvPair
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variable "day_long"
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value "vendredi"
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)
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(vvPair
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variable "dd"
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value "28"
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)
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(vvPair
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variable "designName"
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value "$DESIGN_NAME"
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)
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(vvPair
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variable "entity_name"
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value "parallelAdder_tb"
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)
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(vvPair
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variable "ext"
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value "<TBD>"
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)
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(vvPair
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variable "f"
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value "struct.bd"
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)
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(vvPair
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variable "f_logical"
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value "struct.bd"
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)
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(vvPair
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variable "f_noext"
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value "struct"
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(vvPair
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variable "graphical_source_author"
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value "axel.amand"
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variable "graphical_source_date"
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value "28.04.2023"
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value "UNKNOWN"
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variable "graphical_source_host"
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value "WE7860"
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(vvPair
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variable "graphical_source_time"
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value "15:19:47"
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(vvPair
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variable "group"
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value "UNKNOWN"
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(vvPair
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variable "host"
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value "WE7860"
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(vvPair
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variable "language"
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value "VHDL"
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(vvPair
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variable "library"
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value "PipelinedOperators_test"
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)
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(vvPair
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variable "library_downstream_ModelSim"
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value "D:\\Users\\ELN_labs\\VHDL_comp"
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)
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(vvPair
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variable "library_downstream_ModelSimCompiler"
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value "$SCRATCH_DIR/PipelinedOperators_test"
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)
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(vvPair
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variable "mm"
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value "04"
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)
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(vvPair
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variable "module_name"
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value "parallelAdder_tb"
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)
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(vvPair
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variable "month"
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value "avr."
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)
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(vvPair
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variable "month_long"
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value "avril"
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)
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(vvPair
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variable "p"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\parallel@adder_tb\\struct.bd"
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)
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(vvPair
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variable "p_logical"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\parallelAdder_tb\\struct.bd"
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)
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(vvPair
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variable "package_name"
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value "<Undefined Variable>"
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)
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(vvPair
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variable "project_name"
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value "hds"
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)
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(vvPair
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variable "series"
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value "HDL Designer Series"
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)
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(vvPair
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variable "task_ADMS"
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value "<TBD>"
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)
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(vvPair
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variable "task_AsmPath"
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value "$HEI_LIBS_DIR/NanoBlaze/hdl"
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)
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(vvPair
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variable "task_DesignCompilerPath"
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value "<TBD>"
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(vvPair
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variable "task_HDSPath"
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value "$HDS_HOME"
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(vvPair
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variable "task_ISEBinPath"
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value "$ISE_HOME"
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(vvPair
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variable "task_ISEPath"
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value "$ISE_WORK_DIR"
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(vvPair
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variable "task_LeonardoPath"
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value "<TBD>"
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(vvPair
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variable "task_ModelSimPath"
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value "/usr/opt/Modelsim/modeltech/bin"
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(vvPair
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variable "task_NC"
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value "<TBD>"
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)
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(vvPair
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variable "task_PrecisionRTLPath"
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value "<TBD>"
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)
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(vvPair
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variable "task_QuestaSimPath"
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value "<TBD>"
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(vvPair
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variable "task_VCSPath"
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value "<TBD>"
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(vvPair
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variable "this_ext"
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value "bd"
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(vvPair
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variable "this_file"
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value "struct"
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(vvPair
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variable "this_file_logical"
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value "struct"
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(vvPair
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variable "time"
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value "15:19:47"
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)
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(vvPair
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variable "unit"
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value "parallelAdder_tb"
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(vvPair
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variable "user"
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value "axel.amand"
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variable "version"
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value "2019.2 (Build 5)"
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(vvPair
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variable "view"
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value "struct"
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(vvPair
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variable "year"
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value "2023"
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(vvPair
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variable "yy"
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value "23"
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|
|
shape (GroupingShape
|
|
uid 111,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
lineWidth 2
|
|
)
|
|
xt "32000,44000,73000,49000"
|
|
)
|
|
oxt "14000,66000,55000,71000"
|
|
)
|
|
*12 (Blk
|
|
uid 2178,0
|
|
shape (Rectangle
|
|
uid 2179,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "40000,56832,65535"
|
|
)
|
|
xt "19000,29000,59000,37000"
|
|
)
|
|
oxt "0,0,8000,10000"
|
|
ttg (MlTextGroup
|
|
uid 2180,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*13 (Text
|
|
uid 2181,0
|
|
va (VaSet
|
|
)
|
|
xt "18850,37200,30850,38100"
|
|
st "pipelinedOperators_test"
|
|
blo "18850,37900"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*14 (Text
|
|
uid 2182,0
|
|
va (VaSet
|
|
)
|
|
xt "18850,38400,29350,39300"
|
|
st "parallelAdder_tester"
|
|
blo "18850,39100"
|
|
tm "BlkNameMgr"
|
|
)
|
|
*15 (Text
|
|
uid 2183,0
|
|
va (VaSet
|
|
)
|
|
xt "18850,39600,22850,40500"
|
|
st "I_tester"
|
|
blo "18850,40300"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 2184,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 2185,0
|
|
text (MLText
|
|
uid 2186,0
|
|
va (VaSet
|
|
)
|
|
xt "19000,41000,45200,43400"
|
|
st "adderBitNb = adderBitNb ( positive )
|
|
clockFrequency = clockFrequency ( real )
|
|
"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "adderBitNb"
|
|
type "positive"
|
|
value "adderBitNb"
|
|
)
|
|
(GiElement
|
|
name "clockFrequency"
|
|
type "real"
|
|
value "clockFrequency"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
*16 (Net
|
|
uid 2240,0
|
|
decl (Decl
|
|
n "cOut"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 20,0
|
|
)
|
|
declText (MLText
|
|
uid 2241,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,14800,13500,15800"
|
|
st "SIGNAL cOut : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*17 (Net
|
|
uid 2248,0
|
|
decl (Decl
|
|
n "cIn"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 21,0
|
|
)
|
|
declText (MLText
|
|
uid 2249,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,13800,13200,14800"
|
|
st "SIGNAL cIn : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*18 (Net
|
|
uid 2256,0
|
|
decl (Decl
|
|
n "b"
|
|
t "signed"
|
|
b "(adderBitNb-1 DOWNTO 0)"
|
|
o 2
|
|
suid 22,0
|
|
)
|
|
declText (MLText
|
|
uid 2257,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,12800,23100,13800"
|
|
st "SIGNAL b : signed(adderBitNb-1 DOWNTO 0)
|
|
"
|
|
)
|
|
)
|
|
*19 (Net
|
|
uid 2264,0
|
|
decl (Decl
|
|
n "a"
|
|
t "signed"
|
|
b "(adderBitNb-1 DOWNTO 0)"
|
|
o 1
|
|
suid 23,0
|
|
)
|
|
declText (MLText
|
|
uid 2265,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,11800,23100,12800"
|
|
st "SIGNAL a : signed(adderBitNb-1 DOWNTO 0)
|
|
"
|
|
)
|
|
)
|
|
*20 (Net
|
|
uid 2284,0
|
|
decl (Decl
|
|
n "sum"
|
|
t "signed"
|
|
b "(adderBitNb-1 DOWNTO 0)"
|
|
o 5
|
|
suid 24,0
|
|
)
|
|
declText (MLText
|
|
uid 2285,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,15800,23700,16800"
|
|
st "SIGNAL sum : signed(adderBitNb-1 DOWNTO 0)
|
|
"
|
|
)
|
|
)
|
|
*21 (SaComponent
|
|
uid 2425,0
|
|
optionalChildren [
|
|
*22 (CptPort
|
|
uid 2405,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 2406,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "36625,21000,37375,21750"
|
|
)
|
|
tg (CPTG
|
|
uid 2407,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 2408,0
|
|
va (VaSet
|
|
)
|
|
xt "36000,19800,37500,20700"
|
|
st "sum"
|
|
blo "36000,20500"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "sum"
|
|
t "signed"
|
|
b "(bitNb-1 downto 0)"
|
|
o 1
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*23 (CptPort
|
|
uid 2409,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 2410,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "42334,16625,43084,17375"
|
|
)
|
|
tg (CPTG
|
|
uid 2411,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 2412,0
|
|
va (VaSet
|
|
)
|
|
xt "39834,16400,41334,17300"
|
|
st "cIn"
|
|
ju 2
|
|
blo "41334,17100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "cIn"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
*24 (CptPort
|
|
uid 2413,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 2414,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "30917,16625,31667,17375"
|
|
)
|
|
tg (CPTG
|
|
uid 2415,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 2416,0
|
|
va (VaSet
|
|
)
|
|
xt "32667,16400,34667,17300"
|
|
st "cOut"
|
|
blo "32667,17100"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "cOut"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 2005,0
|
|
)
|
|
)
|
|
)
|
|
*25 (CptPort
|
|
uid 2417,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 2418,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "32625,12250,33375,13000"
|
|
)
|
|
tg (CPTG
|
|
uid 2419,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 2420,0
|
|
va (VaSet
|
|
)
|
|
xt "32800,13000,33300,13900"
|
|
st "a"
|
|
ju 2
|
|
blo "33300,13700"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "a"
|
|
t "signed"
|
|
b "(bitNb-1 downto 0)"
|
|
o 4
|
|
suid 2006,0
|
|
)
|
|
)
|
|
)
|
|
*26 (CptPort
|
|
uid 2421,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 2422,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "40625,12250,41375,13000"
|
|
)
|
|
tg (CPTG
|
|
uid 2423,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 2424,0
|
|
va (VaSet
|
|
)
|
|
xt "40800,13000,41300,13900"
|
|
st "b"
|
|
ju 2
|
|
blo "41300,13700"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "b"
|
|
t "signed"
|
|
b "(bitNb-1 downto 0)"
|
|
o 5
|
|
suid 2007,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Alu
|
|
uid 2426,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
bg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "29000,13000,45000,21000"
|
|
)
|
|
oxt "32000,15000,48000,23000"
|
|
ttg (MlTextGroup
|
|
uid 2427,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*27 (Text
|
|
uid 2428,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "38600,20800,48100,21700"
|
|
st "pipelinedOperators"
|
|
blo "38600,21500"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*28 (Text
|
|
uid 2429,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "38600,22000,45600,22900"
|
|
st "parallelAdder"
|
|
blo "38600,22700"
|
|
tm "CptNameMgr"
|
|
)
|
|
*29 (Text
|
|
uid 2430,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "38600,23200,41100,24100"
|
|
st "I_DUT"
|
|
blo "38600,23900"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 2431,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 2432,0
|
|
text (MLText
|
|
uid 2433,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "39000,24600,54600,25600"
|
|
st "bitNb = adderBitNb ( positive ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "bitNb"
|
|
type "positive"
|
|
value "adderBitNb"
|
|
)
|
|
]
|
|
)
|
|
ordering 1
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*30 (Wire
|
|
uid 2242,0
|
|
shape (OrthoPolyLine
|
|
uid 2243,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "27000,17000,30917,29000"
|
|
pts [
|
|
"30917,17000"
|
|
"27000,17000"
|
|
"27000,29000"
|
|
]
|
|
)
|
|
start &24
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2246,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2247,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "25917,15600,29617,17000"
|
|
st "cOut"
|
|
blo "25917,16800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &16
|
|
)
|
|
*31 (Wire
|
|
uid 2250,0
|
|
shape (OrthoPolyLine
|
|
uid 2251,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "43084,17000,47000,29000"
|
|
pts [
|
|
"43084,17000"
|
|
"47000,17000"
|
|
"47000,29000"
|
|
]
|
|
)
|
|
start &23
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2254,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2255,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "45084,15600,47784,17000"
|
|
st "cIn"
|
|
blo "45084,16800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &17
|
|
)
|
|
*32 (Wire
|
|
uid 2258,0
|
|
shape (OrthoPolyLine
|
|
uid 2259,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "41000,9000,49000,29000"
|
|
pts [
|
|
"41000,12250"
|
|
"41000,9000"
|
|
"49000,9000"
|
|
"49000,29000"
|
|
]
|
|
)
|
|
start &26
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2262,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2263,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "39500,9350,41100,10750"
|
|
st "b"
|
|
blo "39500,10550"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &18
|
|
)
|
|
*33 (Wire
|
|
uid 2266,0
|
|
shape (OrthoPolyLine
|
|
uid 2267,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "33000,7000,51000,29000"
|
|
pts [
|
|
"33000,12250"
|
|
"33000,7000"
|
|
"51000,7000"
|
|
"51000,29000"
|
|
]
|
|
)
|
|
start &25
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2270,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2271,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "31500,9350,33100,10750"
|
|
st "a"
|
|
blo "31500,10550"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &19
|
|
)
|
|
*34 (Wire
|
|
uid 2286,0
|
|
shape (OrthoPolyLine
|
|
uid 2287,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "37000,21750,37000,29000"
|
|
pts [
|
|
"37000,21750"
|
|
"37000,29000"
|
|
]
|
|
)
|
|
start &22
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 2290,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 2291,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "34000,25600,37400,27000"
|
|
st "sum"
|
|
blo "34000,26800"
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|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "625,-1000,625,-1000"
|
|
blo "625,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoInOut (PortIoInOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoBuffer (PortIoBuffer
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultSignal (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,2600,1400"
|
|
st "sig0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBus (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,3900,1400"
|
|
st "dbus0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineStyle 3
|
|
lineWidth 1
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,2600,1000"
|
|
st "bundle0"
|
|
blo "0,800"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,1500,2200"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,50000"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,0,5000,1200"
|
|
st "Auto list"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,9600,2200"
|
|
st "User defined list"
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,18500,100"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*62 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*63 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,11000,100"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*64 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*65 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,5200,6500,6100"
|
|
st "Declarations"
|
|
blo "0,5900"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,6100,3000,7000"
|
|
st "Ports:"
|
|
blo "0,6800"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,7000,4500,7900"
|
|
st "Pre User:"
|
|
blo "0,7700"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,7900,22100,10900"
|
|
st "constant adderBitNb: positive := 8;
|
|
constant clockFrequency : real := 60.0E6;
|
|
--constant clockFrequency : real := 66.0E6;"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,10900,8500,11800"
|
|
st "Diagram Signals:"
|
|
blo "0,11600"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,5200,5500,6100"
|
|
st "Post User:"
|
|
blo "0,5900"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,5200,0,5200"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 24,0
|
|
usingSuid 1
|
|
emptyRow *66 (LEmptyRow
|
|
)
|
|
uid 1321,0
|
|
optionalChildren [
|
|
*67 (RefLabelRowHdr
|
|
)
|
|
*68 (TitleRowHdr
|
|
)
|
|
*69 (FilterRowHdr
|
|
)
|
|
*70 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*71 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*72 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*73 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*74 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*75 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*76 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*77 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*78 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*79 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "cOut"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 20,0
|
|
)
|
|
)
|
|
uid 2276,0
|
|
)
|
|
*80 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "cIn"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 21,0
|
|
)
|
|
)
|
|
uid 2278,0
|
|
)
|
|
*81 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "b"
|
|
t "signed"
|
|
b "(adderBitNb-1 DOWNTO 0)"
|
|
o 2
|
|
suid 22,0
|
|
)
|
|
)
|
|
uid 2280,0
|
|
)
|
|
*82 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "a"
|
|
t "signed"
|
|
b "(adderBitNb-1 DOWNTO 0)"
|
|
o 1
|
|
suid 23,0
|
|
)
|
|
)
|
|
uid 2282,0
|
|
)
|
|
*83 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "sum"
|
|
t "signed"
|
|
b "(adderBitNb-1 DOWNTO 0)"
|
|
o 5
|
|
suid 24,0
|
|
)
|
|
)
|
|
uid 2292,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 1334,0
|
|
optionalChildren [
|
|
*84 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *85 (MRCItem
|
|
litem &66
|
|
pos 5
|
|
dimension 20
|
|
)
|
|
uid 1336,0
|
|
optionalChildren [
|
|
*86 (MRCItem
|
|
litem &67
|
|
pos 0
|
|
dimension 20
|
|
uid 1337,0
|
|
)
|
|
*87 (MRCItem
|
|
litem &68
|
|
pos 1
|
|
dimension 23
|
|
uid 1338,0
|
|
)
|
|
*88 (MRCItem
|
|
litem &69
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 1339,0
|
|
)
|
|
*89 (MRCItem
|
|
litem &79
|
|
pos 0
|
|
dimension 20
|
|
uid 2277,0
|
|
)
|
|
*90 (MRCItem
|
|
litem &80
|
|
pos 1
|
|
dimension 20
|
|
uid 2279,0
|
|
)
|
|
*91 (MRCItem
|
|
litem &81
|
|
pos 2
|
|
dimension 20
|
|
uid 2281,0
|
|
)
|
|
*92 (MRCItem
|
|
litem &82
|
|
pos 3
|
|
dimension 20
|
|
uid 2283,0
|
|
)
|
|
*93 (MRCItem
|
|
litem &83
|
|
pos 4
|
|
dimension 20
|
|
uid 2293,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 1340,0
|
|
optionalChildren [
|
|
*94 (MRCItem
|
|
litem &70
|
|
pos 0
|
|
dimension 20
|
|
uid 1341,0
|
|
)
|
|
*95 (MRCItem
|
|
litem &72
|
|
pos 1
|
|
dimension 50
|
|
uid 1342,0
|
|
)
|
|
*96 (MRCItem
|
|
litem &73
|
|
pos 2
|
|
dimension 100
|
|
uid 1343,0
|
|
)
|
|
*97 (MRCItem
|
|
litem &74
|
|
pos 3
|
|
dimension 50
|
|
uid 1344,0
|
|
)
|
|
*98 (MRCItem
|
|
litem &75
|
|
pos 4
|
|
dimension 100
|
|
uid 1345,0
|
|
)
|
|
*99 (MRCItem
|
|
litem &76
|
|
pos 5
|
|
dimension 100
|
|
uid 1346,0
|
|
)
|
|
*100 (MRCItem
|
|
litem &77
|
|
pos 6
|
|
dimension 50
|
|
uid 1347,0
|
|
)
|
|
*101 (MRCItem
|
|
litem &78
|
|
pos 7
|
|
dimension 80
|
|
uid 1348,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 1335,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 1320,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *102 (LEmptyRow
|
|
)
|
|
uid 1350,0
|
|
optionalChildren [
|
|
*103 (RefLabelRowHdr
|
|
)
|
|
*104 (TitleRowHdr
|
|
)
|
|
*105 (FilterRowHdr
|
|
)
|
|
*106 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*107 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*108 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*109 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*110 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*111 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*112 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*113 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 1362,0
|
|
optionalChildren [
|
|
*114 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *115 (MRCItem
|
|
litem &102
|
|
pos 0
|
|
dimension 20
|
|
)
|
|
uid 1364,0
|
|
optionalChildren [
|
|
*116 (MRCItem
|
|
litem &103
|
|
pos 0
|
|
dimension 20
|
|
uid 1365,0
|
|
)
|
|
*117 (MRCItem
|
|
litem &104
|
|
pos 1
|
|
dimension 23
|
|
uid 1366,0
|
|
)
|
|
*118 (MRCItem
|
|
litem &105
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 1367,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 1368,0
|
|
optionalChildren [
|
|
*119 (MRCItem
|
|
litem &106
|
|
pos 0
|
|
dimension 20
|
|
uid 1369,0
|
|
)
|
|
*120 (MRCItem
|
|
litem &108
|
|
pos 1
|
|
dimension 50
|
|
uid 1370,0
|
|
)
|
|
*121 (MRCItem
|
|
litem &109
|
|
pos 2
|
|
dimension 100
|
|
uid 1371,0
|
|
)
|
|
*122 (MRCItem
|
|
litem &110
|
|
pos 3
|
|
dimension 100
|
|
uid 1372,0
|
|
)
|
|
*123 (MRCItem
|
|
litem &111
|
|
pos 4
|
|
dimension 50
|
|
uid 1373,0
|
|
)
|
|
*124 (MRCItem
|
|
litem &112
|
|
pos 5
|
|
dimension 50
|
|
uid 1374,0
|
|
)
|
|
*125 (MRCItem
|
|
litem &113
|
|
pos 6
|
|
dimension 80
|
|
uid 1375,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 1363,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 1349,0
|
|
type 1
|
|
)
|
|
activeModelName "BlockDiag"
|
|
)
|