128 lines
3.4 KiB
VHDL
128 lines
3.4 KiB
VHDL
--===========================================================================--
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-- Design units : CoCa.serialPortTransmitter.rtl
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--
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-- File name : serialPortTransmitter.vhd
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--
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-- Purpose : Transmit a 8 bit data word over a serial line
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-- add start and stop bits
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--
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-- Parameters : dataBitNb : number of data bits
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-- stopBitNb : number of stop bits
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--
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--
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--
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-- Errors: : None known
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--
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-- Library : Common
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--
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-- Dependencies : None
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--
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-- Author :
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-- Haute ecole d'ingenierie (HEI/HES-SO)
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-- Institut systemes industriels (ISI)
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-- Rue de l'industrie 23
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-- 1950 Sion
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-- Switzerland (CH)
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--
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-- Simulator : Mentor ModelSim V10.7c
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------------------------------------------------
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-- Revision list
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-- Version Author Date Changes
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--
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-- V1.0 04.04.2022 - First version
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--===========================================================================--
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library Common;
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use Common.CommonLib.all;
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architecture RTL of serialPortTransmitter is
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signal dividerCounter: unsigned(requiredBitNb(baudRateDivide)-1 downto 0);
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signal dividerCounterReset: std_uLogic;
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signal txData: unsigned(dataBitNb-1 downto 0);
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signal send1: std_uLogic;
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signal txShiftEnable: std_uLogic;
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signal txShiftReg: unsigned(dataBitNb+stopBitNb downto 0);
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signal txSendingByte: std_uLogic;
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signal txSendingByteAndStop: std_uLogic;
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begin
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divide: process(reset, clock)
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begin
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if reset = '1' then
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dividerCounter <= (others => '0');
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elsif rising_edge(clock) then
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if dividerCounterReset = '1' then
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dividerCounter <= to_unsigned(1, dividerCounter'length);
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else
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dividerCounter <= dividerCounter + 1;
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end if;
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end if;
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end process divide;
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endOfCount: process(dividerCounter, send1)
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begin
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if dividerCounter = baudRateDivide then
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dividerCounterReset <= '1';
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elsif send1 = '1' then
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dividerCounterReset <= '1';
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else
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dividerCounterReset <= '0';
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end if;
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end process endOfCount;
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txShiftEnable <= dividerCounterReset;
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storeData: process(reset, clock)
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begin
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if reset = '1' then
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txData <= (others => '1');
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elsif rising_edge(clock) then
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if send = '1' then
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txData <= unsigned(dataIn);
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end if;
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end if;
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end process storeData;
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delaySend: process(reset, clock)
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begin
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if reset = '1' then
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send1 <= '0';
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elsif rising_edge(clock) then
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send1 <= send;
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end if;
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end process delaySend;
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shiftReg: process(reset, clock)
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begin
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if reset = '1' then
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txShiftReg <= (others => '1');
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elsif rising_edge(clock) then
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if txShiftEnable = '1' then
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if send1 = '1' then
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txShiftReg <= (others => '1'); -- stop bits
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txShiftReg(0) <= '0'; -- start bit
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txShiftReg(txData'high+1 downto 1) <= txData; -- data
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txShiftReg(txShiftReg'high) <= '0'; -- end flag
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else
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txShiftReg <= shift_right(txShiftReg, 1);
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txShiftReg(txShiftReg'high) <= '1';
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end if;
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end if;
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end if;
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end process shiftReg;
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txSendingByte <= '1' when
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(txShiftReg(txShiftReg'high downto 1) /= (txShiftReg'high downto 1 => '1'))
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else '0';
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txSendingByteAndStop <= '1' when
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txShiftReg /= (txShiftReg'high downto 0 => '1')
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else '0';
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TxD <= txShiftReg(0) when txSendingByte = '1' else '1';
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busy <= txSendingByteAndStop or send1 or send;
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end RTL;
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