19 lines
344 B
VHDL
19 lines
344 B
VHDL
ARCHITECTURE RTL OF sdramControllerSR IS
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BEGIN
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setReset: process(reset, clock)
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begin
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if reset = '1' then
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flag <= '0';
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elsif rising_edge(clock) then
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if setFlag = '1' then
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flag <= '1';
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elsif resetFlag = '1' then
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flag <= '0';
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end if;
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end if;
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end process setReset;
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END ARCHITECTURE RTL;
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