74 lines
2.5 KiB
VHDL
74 lines
2.5 KiB
VHDL
-- ------------------------------------------------------------------------------
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-- Copyright 2013 HES-SO Valais Wallis (www.hevs.ch)
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-- ------------------------------------------------------------------------------
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-- FIFO bridge with bus width adaption
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-- A shift register that connects two FIFOs with different bus width.
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-- Many IP blocks nowadays have FIFO or FIFO-like interfaces and often they
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-- have to be connected. This block can the be used for this task, even if
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-- the bus size of the two FIFO interfaces is different.
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-- The Rx side bus width has to be a multiple of the Tx side bus width.
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--
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-- Created on 2013-10-18
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--
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-- Author: Oliver A. Gubler (oliver.gubler@hevs.ch)
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--
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-- 2014-10-06: *modify introduction text
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-- +add some comment
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-- *change readRx to a pulse
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-- *fix bug on shift of shiftreg_s
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-- 2013-10-18: +intital release
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-- ------------------------------------------------------------------------------
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--
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library Common;
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use Common.CommonLib.all;
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ARCHITECTURE behavioral OF fifoBridgeRxToTxBusWidthAdaptionRxBigger IS
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signal cnt_s: unsigned(requiredBitNb(dataBitNbRx)-1 downto 0);
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signal shiftreg_s: std_ulogic_vector(dataBitNbRx-1 downto 0);
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signal emptyRx_s: std_ulogic; -- internal empty signal
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signal writeTx_s: std_ulogic; -- internal write signal
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constant ratio_rxtx_c: positive range 1 to dataBitNbRx/dataBitNbTx:= dataBitNbRx/dataBitNbTx;
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BEGIN
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rx0: process(clock, reset)
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begin
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if reset = '1' then
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shiftreg_s <= (others => '0');
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emptyRx_s <= '1';
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cnt_s <= (others => '0');
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writeTx_s <= '0';
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dataTx <= (others => '0');
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readRx <= '0';
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elsif rising_edge(clock) then
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writeTx_s <= '0';
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readRx <= '0';
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-- fetch data
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if emptyRx_s = '1' and emptyRx = '0' then
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emptyRx_s <= '0';
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shiftreg_s <= dataRx;
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readRx <= '1';
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end if;
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-- shift data and put out
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-- after each write, wait one cylce to check if full gets high
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if emptyRx_s = '0' and fullTx = '0' and writeTx_s = '0' then
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shiftreg_s <= shiftreg_s(dataBitNbRx-dataBitNbTx-1 downto 0) & std_ulogic_vector(to_unsigned(0,dataBitNbTx));
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dataTx <= shiftreg_s(dataBitNbRx-1 downto dataBitNbRx-dataBitNbTx);
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writeTx_s <= '1';
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cnt_s <= cnt_s +1;
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if cnt_s >= ratio_rxtx_c-1 then
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cnt_s <= (others => '0');
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emptyRx_s <= '1';
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end if;
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end if;
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end if;
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end process;
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writeTx <= writeTx_s;
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END ARCHITECTURE behavioral;
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