94 lines
3.8 KiB
VHDL
94 lines
3.8 KiB
VHDL
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
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-- Module Version: 5.7
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--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc
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-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks
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library IEEE;
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use IEEE.std_logic_1164.all;
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library ECP5U;
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use ECP5U.components.all;
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ENTITY pll IS
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PORT(
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clkIn100M : IN std_ulogic;
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en75M : IN std_ulogic;
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en50M : IN std_ulogic;
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en10M : IN std_ulogic;
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clk60MHz : OUT std_ulogic;
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clk75MHz : OUT std_ulogic;
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clk50MHz : OUT std_ulogic;
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clk10MHz : OUT std_ulogic;
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pllLocked : OUT std_ulogic
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);
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-- Declarations
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END pll ;
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architecture rtl of pll is
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-- internal signal declarations
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signal REFCLK: std_logic;
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signal CLKOS3_t: std_logic;
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signal CLKOS2_t: std_logic;
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signal CLKOS_t: std_logic;
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signal CLKOP_t: std_logic;
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signal scuba_vhi: std_logic;
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signal scuba_vlo: std_logic;
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attribute FREQUENCY_PIN_CLKOS3 : string;
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attribute FREQUENCY_PIN_CLKOS2 : string;
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attribute FREQUENCY_PIN_CLKOS : string;
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attribute FREQUENCY_PIN_CLKOP : string;
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attribute FREQUENCY_PIN_CLKI : string;
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attribute ICP_CURRENT : string;
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attribute LPF_RESISTOR : string;
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attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000";
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attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000";
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attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000";
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attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000";
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attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
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attribute ICP_CURRENT of PLLInst_0 : label is "5";
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attribute LPF_RESISTOR of PLLInst_0 : label is "16";
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attribute syn_keep : boolean;
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attribute NGD_DRC_MASK : integer;
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attribute NGD_DRC_MASK of rtl : architecture is 1;
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begin
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-- component instantiation statements
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scuba_vhi_inst: VHI
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port map (Z=>scuba_vhi);
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scuba_vlo_inst: VLO
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port map (Z=>scuba_vlo);
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PLLInst_0: EHXPLLL
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generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
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STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
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CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0,
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CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7,
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CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0,
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CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
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CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
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OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED",
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OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED",
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OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED",
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OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60,
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CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3,
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CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP")
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port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
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PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
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PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
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STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
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ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M,
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ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
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CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked,
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INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open);
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clk10MHz <= CLKOS3_t;
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clk50MHz <= CLKOS2_t;
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clk75MHz <= CLKOS_t;
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clk60MHz <= CLKOP_t;
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end rtl;
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