71 lines
1.9 KiB
VHDL
71 lines
1.9 KiB
VHDL
ARCHITECTURE RTL OF ahbMasterInterface IS
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signal addressReg: unsigned(pAddress'range);
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signal newAddress: std_ulogic;
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signal writeReg: std_ulogic;
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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hReset_n <= not reset;
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hClk <= clock;
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------------------------------------------------------------------------------
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-- address and controls
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newAddress <= pReadStrobe or pWriteStrobe;
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storeAddress: process(reset, clock)
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begin
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if reset = '1' then
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addressReg <= (others => '0');
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elsif rising_edge(clock) then
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if newAddress = '1' then
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addressReg <= pAddress;
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end if;
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end if;
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end process storeAddress;
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hAddr <= pAddress when newAddress = '1'
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else addressReg;
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storeWrite: process(reset, clock)
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begin
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if reset = '1' then
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writeReg <= '0';
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elsif rising_edge(clock) then
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if newAddress = '1' then
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writeReg <= pWriteStrobe;
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end if;
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end if;
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end process storeWrite;
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hWrite <= pWriteStrobe when newAddress = '1'
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else writeReg;
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hTrans <= transNonSeq when newAddress = '1'
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else transIdle;
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hSize <= size16;
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hBurst <= burstSingle;
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hProt <= protDefault;
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hMastLock <= '0';
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------------------------------------------------------------------------------
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-- data out
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delayData: process(reset, clock)
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begin
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if reset = '1' then
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hWData <= (others => '0');
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elsif rising_edge(clock) then
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if pWriteStrobe = '1' then
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hWData <= pDataOut;
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end if;
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end if;
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end process delayData;
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------------------------------------------------------------------------------
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-- data in
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pDataIn <= hRData;
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END ARCHITECTURE RTL;
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