46 lines
1.4 KiB
Tcl
46 lines
1.4 KiB
Tcl
set board "A7-50"
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# create and clear output directory
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set outputdir work
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file mkdir $outputdir
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set files [glob -nocomplain "$outputdir/*"]
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if {[llength $files] != 0} {
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puts "deleting contents of $outputdir"
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file delete -force {*}[glob -directory $outputdir *]; # clear folder contents
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} else {
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puts "$outputdir is empty"
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}
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switch $board {
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"A7-50" {
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set a7part "xc7a50tcsg324-1"
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set a7prj "nexys-a7-50-test-setup"
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}
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"A7-100" {
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set a7part "xc7a100tcsg324-1"
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set a7prj "nexys-a7-100-test-setup"
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}
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}
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# create project
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create_project -part $a7part $a7prj $outputdir
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# add source files: core sources
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add_files [glob ./../../../rtl/core/*.vhd] ./../../../rtl/core/mem/neorv32_dmem.default.vhd ./../../../rtl/core/mem/neorv32_imem.default.vhd
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set_property library neorv32 [get_files [glob ./../../../rtl/core/*.vhd]]
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set_property library neorv32 [get_files [glob ./../../../rtl/core/mem/neorv32_*mem.default.vhd]]
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# add source file: top entity
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add_files [glob ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd]
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# add source files: simulation-only
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add_files -fileset sim_1 [list ./../../../sim/simple/neorv32_tb.simple.vhd ./../../../sim/simple/uart_rx.simple.vhd]
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# add source files: constraints
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add_files -fileset constrs_1 [glob ./*.xdc]
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# run synthesis, implementation and bitstream generation
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launch_runs impl_1 -to_step write_bitstream -jobs 4
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wait_on_run impl_1
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